Lines Matching +full:ecam +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
31 /* Egress - Bridge translation registers */
41 /* Ingress - address translations */
49 /* Rxed msg fifo - Interrupt status registers */
177 return readl(pcie->breg_base + off); in nwl_bridge_readl()
182 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
187 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
194 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
201 struct device *dev = pcie->dev; in nwl_wait_for_link()
212 return -ETIMEDOUT; in nwl_wait_for_link()
217 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device()
220 if (bus->number != pcie->root_busno) { in nwl_pcie_valid_device()
226 if (bus->number == pcie->root_busno && devfn > 0) in nwl_pcie_valid_device()
233 * nwl_pcie_map_bus - Get configuration base
245 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus()
251 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) | in nwl_pcie_map_bus()
254 return pcie->ecam_base + relbus + where; in nwl_pcie_map_bus()
267 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
295 dev_err(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
304 dev_err(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
335 virq = irq_find_mapping(pcie->legacy_irq_domain, bit); in nwl_pcie_leg_handler()
351 msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
356 virq = irq_find_mapping(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
385 struct irq_desc *desc = irq_to_desc(data->irq); in nwl_mask_leg_irq()
392 mask = 1 << (data->hwirq - 1); in nwl_mask_leg_irq()
393 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
396 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
401 struct irq_desc *desc = irq_to_desc(data->irq); in nwl_unmask_leg_irq()
408 mask = 1 << (data->hwirq - 1); in nwl_unmask_leg_irq()
409 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
412 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
427 irq_set_chip_data(irq, domain->host_data); in nwl_legacy_map()
458 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
460 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
461 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
462 msg->data = data->hwirq; in nwl_compose_msi_msg()
468 return -EINVAL; in nwl_msi_set_affinity()
480 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc()
481 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
485 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
486 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
489 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
490 return -ENOSPC; in nwl_irq_domain_alloc()
495 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
498 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
507 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
509 mutex_lock(&msi->lock); in nwl_irq_domain_free()
510 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
512 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
523 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
524 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in nwl_pcie_init_msi_irq_domain()
525 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
527 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, in nwl_pcie_init_msi_irq_domain()
529 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
531 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
533 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in nwl_pcie_init_msi_irq_domain()
535 msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
536 if (!msi->msi_domain) { in nwl_pcie_init_msi_irq_domain()
538 irq_domain_remove(msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
539 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
547 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
548 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
554 return -EINVAL; in nwl_pcie_init_irq_domain()
557 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, in nwl_pcie_init_irq_domain()
562 if (!pcie->legacy_irq_domain) { in nwl_pcie_init_irq_domain()
564 return -ENOMEM; in nwl_pcie_init_irq_domain()
567 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
574 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
576 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
581 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
583 msi->bitmap = kzalloc(size, GFP_KERNEL); in nwl_pcie_enable_msi()
584 if (!msi->bitmap) in nwl_pcie_enable_msi()
585 return -ENOMEM; in nwl_pcie_enable_msi()
588 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
589 if (msi->irq_msi1 < 0) { in nwl_pcie_enable_msi()
590 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi1); in nwl_pcie_enable_msi()
591 ret = -EINVAL; in nwl_pcie_enable_msi()
595 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
599 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
600 if (msi->irq_msi0 < 0) { in nwl_pcie_enable_msi()
601 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi0); in nwl_pcie_enable_msi()
602 ret = -EINVAL; in nwl_pcie_enable_msi()
606 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
613 ret = -EIO; in nwl_pcie_enable_msi()
626 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
654 kfree(msi->bitmap); in nwl_pcie_enable_msi()
655 msi->bitmap = NULL; in nwl_pcie_enable_msi()
661 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
673 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
675 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
699 dev_err(dev, "ECAM is not present\n"); in nwl_pcie_bridge_init()
703 /* Enable ECAM */ in nwl_pcie_bridge_init()
708 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), in nwl_pcie_bridge_init()
711 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
713 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
718 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; in nwl_pcie_bridge_init()
722 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); in nwl_pcie_bridge_init()
723 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); in nwl_pcie_bridge_init()
731 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
732 if (pcie->irq_misc < 0) { in nwl_pcie_bridge_init()
734 pcie->irq_misc); in nwl_pcie_bridge_init()
735 return -EINVAL; in nwl_pcie_bridge_init()
738 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
743 pcie->irq_misc); in nwl_pcie_bridge_init()
778 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
779 struct device_node *node = dev->of_node; in nwl_pcie_parse_dt()
787 return -EINVAL; in nwl_pcie_parse_dt()
791 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
792 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
793 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
794 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
797 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
798 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
799 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
800 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
803 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
804 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
805 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
806 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
809 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
810 if (pcie->irq_intx < 0) { in nwl_pcie_parse_dt()
811 dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx); in nwl_pcie_parse_dt()
812 return pcie->irq_intx; in nwl_pcie_parse_dt()
815 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
822 { .compatible = "xlnx,nwl-pcie-2.11", },
828 struct device *dev = &pdev->dev; in nwl_pcie_probe()
839 return -ENODEV; in nwl_pcie_probe()
843 pcie->dev = dev; in nwl_pcie_probe()
844 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; in nwl_pcie_probe()
875 list_splice_init(&res, &bridge->windows); in nwl_pcie_probe()
876 bridge->dev.parent = dev; in nwl_pcie_probe()
877 bridge->sysdata = pcie; in nwl_pcie_probe()
878 bridge->busnr = pcie->root_busno; in nwl_pcie_probe()
879 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
880 bridge->map_irq = of_irq_parse_and_map_pci; in nwl_pcie_probe()
881 bridge->swizzle_irq = pci_common_swizzle; in nwl_pcie_probe()
895 bus = bridge->bus; in nwl_pcie_probe()
898 list_for_each_entry(child, &bus->children, node) in nwl_pcie_probe()
910 .name = "nwl-pcie",