Lines Matching full:pcie
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
160 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
175 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
177 return readl(pcie->breg_base + off); in nwl_bridge_readl()
180 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
182 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
185 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
187 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
192 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
194 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
199 static int nwl_wait_for_link(struct nwl_pcie *pcie) in nwl_wait_for_link() argument
201 struct device *dev = pcie->dev; in nwl_wait_for_link()
206 if (nwl_phy_link_up(pcie)) in nwl_wait_for_link()
217 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device() local
220 if (bus->number != pcie->root_busno) { in nwl_pcie_valid_device()
221 if (!nwl_pcie_link_up(pcie)) in nwl_pcie_valid_device()
226 if (bus->number == pcie->root_busno && devfn > 0) in nwl_pcie_valid_device()
245 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus() local
254 return pcie->ecam_base + relbus + where; in nwl_pcie_map_bus()
257 /* PCIe operations */
266 struct nwl_pcie *pcie = data; in nwl_pcie_misc_handler() local
267 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
271 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_misc_handler()
316 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); in nwl_pcie_misc_handler()
324 struct nwl_pcie *pcie; in nwl_pcie_leg_handler() local
330 pcie = irq_desc_get_handler_data(desc); in nwl_pcie_leg_handler()
332 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_leg_handler()
335 virq = irq_find_mapping(pcie->legacy_irq_domain, bit); in nwl_pcie_leg_handler()
344 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) in nwl_pcie_handle_msi_irq() argument
351 msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
353 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { in nwl_pcie_handle_msi_irq()
355 nwl_bridge_writel(pcie, 1 << bit, status_reg); in nwl_pcie_handle_msi_irq()
366 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_high() local
369 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); in nwl_pcie_msi_handler_high()
376 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_low() local
379 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); in nwl_pcie_msi_handler_low()
386 struct nwl_pcie *pcie; in nwl_mask_leg_irq() local
391 pcie = irq_desc_get_chip_data(desc); in nwl_mask_leg_irq()
393 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
394 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_mask_leg_irq()
395 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); in nwl_mask_leg_irq()
396 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
402 struct nwl_pcie *pcie; in nwl_unmask_leg_irq() local
407 pcie = irq_desc_get_chip_data(desc); in nwl_unmask_leg_irq()
409 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
410 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_unmask_leg_irq()
411 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); in nwl_unmask_leg_irq()
412 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
457 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_compose_msi_msg() local
458 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
480 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc() local
481 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
506 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_irq_domain_free() local
507 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
520 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_msi_irq_domain() argument
523 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
525 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
528 &dev_msi_domain_ops, pcie); in nwl_pcie_init_msi_irq_domain()
545 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_irq_domain() argument
547 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
557 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, in nwl_pcie_init_irq_domain()
560 pcie); in nwl_pcie_init_irq_domain()
562 if (!pcie->legacy_irq_domain) { in nwl_pcie_init_irq_domain()
567 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
568 nwl_pcie_init_msi_irq_domain(pcie); in nwl_pcie_init_irq_domain()
572 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) in nwl_pcie_enable_msi() argument
574 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
576 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
596 nwl_pcie_msi_handler_high, pcie); in nwl_pcie_enable_msi()
607 nwl_pcie_msi_handler_low, pcie); in nwl_pcie_enable_msi()
610 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; in nwl_pcie_enable_msi()
618 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
622 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
626 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
627 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); in nwl_pcie_enable_msi()
628 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); in nwl_pcie_enable_msi()
634 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
636 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & in nwl_pcie_enable_msi()
639 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
645 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
647 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & in nwl_pcie_enable_msi()
650 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
659 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) in nwl_pcie_bridge_init() argument
661 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
666 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; in nwl_pcie_bridge_init()
673 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
675 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
679 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, in nwl_pcie_bridge_init()
683 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | in nwl_pcie_bridge_init()
687 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); in nwl_pcie_bridge_init()
690 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, in nwl_pcie_bridge_init()
693 err = nwl_wait_for_link(pcie); in nwl_pcie_bridge_init()
697 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; in nwl_pcie_bridge_init()
704 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
707 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
708 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), in nwl_pcie_bridge_init()
711 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
713 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
717 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); in nwl_pcie_bridge_init()
718 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; in nwl_pcie_bridge_init()
722 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); in nwl_pcie_bridge_init()
723 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); in nwl_pcie_bridge_init()
725 if (nwl_pcie_link_up(pcie)) in nwl_pcie_bridge_init()
731 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
732 if (pcie->irq_misc < 0) { in nwl_pcie_bridge_init()
734 pcie->irq_misc); in nwl_pcie_bridge_init()
738 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
740 "nwl_pcie:misc", pcie); in nwl_pcie_bridge_init()
743 pcie->irq_misc); in nwl_pcie_bridge_init()
748 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
751 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_bridge_init()
755 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
759 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
762 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_bridge_init()
766 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
769 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | in nwl_pcie_bridge_init()
775 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, in nwl_pcie_parse_dt() argument
778 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
791 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
792 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
793 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
794 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
797 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
798 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
799 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
800 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
803 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
804 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
805 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
806 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
809 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
810 if (pcie->irq_intx < 0) { in nwl_pcie_parse_dt()
811 dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx); in nwl_pcie_parse_dt()
812 return pcie->irq_intx; in nwl_pcie_parse_dt()
815 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
816 nwl_pcie_leg_handler, pcie); in nwl_pcie_parse_dt()
822 { .compatible = "xlnx,nwl-pcie-2.11", },
829 struct nwl_pcie *pcie; in nwl_pcie_probe() local
837 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in nwl_pcie_probe()
841 pcie = pci_host_bridge_priv(bridge); in nwl_pcie_probe()
843 pcie->dev = dev; in nwl_pcie_probe()
844 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; in nwl_pcie_probe()
846 err = nwl_pcie_parse_dt(pcie, pdev); in nwl_pcie_probe()
852 err = nwl_pcie_bridge_init(pcie); in nwl_pcie_probe()
869 err = nwl_pcie_init_irq_domain(pcie); in nwl_pcie_probe()
877 bridge->sysdata = pcie; in nwl_pcie_probe()
878 bridge->busnr = pcie->root_busno; in nwl_pcie_probe()
884 err = nwl_pcie_enable_msi(pcie); in nwl_pcie_probe()
910 .name = "nwl-pcie",