30 #define ASPM_STATE_L0S_UP	(1)	/* Upstream direction L0s state */
51 	struct pci_dev *pdev;		/* Upstream component of the Link */
73 	struct aspm_latency latency_up;	/* Upstream direction exit latency */
83 		u32 up_cap_ptr;		/* L1SS cap ptr in upstream dev */
261 	/* Check upstream component if bit Slot Clock Configuration is 1 */  in pcie_aspm_configure_common_clock()
295 	/* Configure upstream component */  in pcie_aspm_configure_common_clock()
455 		/* Check upstream direction L0s latency */  in pcie_aspm_check_latency()
564 	/* Get upstream/downstream components' register state */  in pcie_aspm_cap_init()
579 	 * Re-read upstream/downstream components' register state  in pcie_aspm_cap_init()
717 		/* Program Common_Mode_Restore_Time in upstream device */  in pcie_config_aspm_l1ss()
758 	u32 upstream = 0, dwstream = 0;  in pcie_config_aspm_link()  local
778 	/* Convert ASPM state to upstream/downstream ASPM register state */  in pcie_config_aspm_link()
782 		upstream |= PCI_EXP_LNKCTL_ASPM_L0S;  in pcie_config_aspm_link()
784 		upstream |= PCI_EXP_LNKCTL_ASPM_L1;  in pcie_config_aspm_link()
794 	 * upstream component first and then downstream, and vice  in pcie_config_aspm_link()
798 		pcie_config_aspm_dev(parent, upstream);  in pcie_config_aspm_link()
802 		pcie_config_aspm_dev(parent, upstream);  in pcie_config_aspm_link()
917 	 * We allocate pcie_link_state for the component on the upstream  in pcie_aspm_init_link_state()
939 	 * upstream links also because capable state of them can be  in pcie_aspm_init_link_state()
1020 	/* Recheck latencies and configure upstream links */  in pcie_aspm_exit_link_state()