31 #define ASPM_STATE_L0S_DW	(2)	/* Downstream direction L0s state */
52 	struct pci_dev *downstream;	/* Downstream component, function 0 */  member
74 	struct aspm_latency latency_dw;	/* Downstream direction exit latency */
76 	 * Endpoint acceptable latencies. A pcie downstream port only
84 		u32 dw_cap_ptr;		/* L1SS cap ptr in downstream dev */
256 	/* Check downstream component if bit Slot Clock Configuration is 1 */  in pcie_aspm_configure_common_clock()
284 	/* Configure downstream component, all functions */  in pcie_aspm_configure_common_clock()
460 		/* Check downstream direction L0s latency */  in pcie_aspm_check_latency()
528 	    calc_l1ss_pwron(link->downstream, scale2, val2)) {  in aspm_calc_l1ss_info()
533 		t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);  in aspm_calc_l1ss_info()
539 	 * downstream devices report (via LTR) that they can tolerate at  in aspm_calc_l1ss_info()
553 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_aspm_cap_init()
564 	/* Get upstream/downstream components' register state */  in pcie_aspm_cap_init()
579 	 * Re-read upstream/downstream components' register state  in pcie_aspm_cap_init()
674 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_l1ss()
759 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_link()
778 	/* Convert ASPM state to upstream/downstream ASPM register state */  in pcie_config_aspm_link()
794 	 * upstream component first and then downstream, and vice  in pcie_config_aspm_link()
868 	link->downstream = pci_function_0(pdev->subordinate);  in alloc_pcie_link_state()
873 	 * the root ports entirely, in which case a downstream port on  in alloc_pcie_link_state()
903  * @pdev: the root port or switch downstream port
1030 /* @pdev: the root port or switch downstream port */