3  * Enable PCIe link L0s/L1 state and Clock Power Management
32 #define ASPM_STATE_L1		(4)	/* L1 state */
33 #define ASPM_STATE_L1_1		(8)	/* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2		(0x10)	/* ASPM L1.2 state */
35 #define ASPM_STATE_L1_1_PCIPM	(0x20)	/* PCI PM L1.1 state */
36 #define ASPM_STATE_L1_2_PCIPM	(0x40)	/* PCI PM L1.2 state */
47 	u32 l1;				/* L1 latency (nsec) */  member
81 	/* L1 PM Substate info */
126 		/* Enable ASPM L0s/L1 */  in policy_to_aspm_state()
331 /* Convert L1 latency encoding to ns */
339 /* Convert L1 acceptable latency encoding to ns */
394 	/* L1 substates */
414 	/* Read L1 PM substate capabilities */  in pcie_get_aspm_reg()
428 	 * to this device, we can't use ASPM L1.2 because it relies on the  in pcie_get_aspm_reg()
465 		 * Check L1 latency.  in pcie_aspm_check_latency()
467 		 * more microsecond for L1. Spec doesn't mention L0s.  in pcie_aspm_check_latency()
469 		 * The exit latencies for L1 substates are not advertised  in pcie_aspm_check_latency()
471 		 * to determine max latencies introduced by enabling L1  in pcie_aspm_check_latency()
473 		 * a L1 substate exit latency check.  We assume that the  in pcie_aspm_check_latency()
474 		 * L1 exit latencies advertised by a device include L1  in pcie_aspm_check_latency()
477 		latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);  in pcie_aspm_check_latency()
479 		    (latency + l1_switch_latency > acceptable->l1))  in pcie_aspm_check_latency()
488  * The L1 PM substate capability is only implemented in function 0 in a
501 /* Calculate L1.2 PM substate timing parameters */
538 	 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if  in aspm_calc_l1ss_info()
543 	 * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at  in aspm_calc_l1ss_info()
601 	/* Setup L1 state */  in pcie_aspm_cap_init()
606 	link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);  in pcie_aspm_cap_init()
607 	link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);  in pcie_aspm_cap_init()
609 	/* Setup L1 substate */  in pcie_aspm_cap_init()
651 		/* Calculate endpoint L1 acceptable latency */  in pcie_aspm_cap_init()
653 		acceptable->l1 = calc_l1_acceptable(encoding);  in pcie_aspm_cap_init()
670 /* Configure the ASPM L1 substates */
682 	 * - When enabling L1.x, enable bit at parent first, then at child  in pcie_config_aspm_l1ss()
683 	 * - When disabling L1.x, disable bit at child first, then at parent  in pcie_config_aspm_l1ss()
684 	 * - When enabling ASPM L1.x, need to disable L1  in pcie_config_aspm_l1ss()
686 	 * - The ASPM/PCIPM L1.2 must be disabled while programming timing  in pcie_config_aspm_l1ss()
693 	/* Disable all L1 substates */  in pcie_config_aspm_l1ss()
699 	 * If needed, disable L1, and it gets enabled later  in pcie_config_aspm_l1ss()
765 	/* Can't enable any substates if L1 is not enabled */  in pcie_config_aspm_link()
793 	 * same setting for ASPM. Enabling ASPM L1 should be done in  in pcie_config_aspm_link()
795 	 * versa for disabling ASPM L1. Spec doesn't mention L0S.  in pcie_config_aspm_link()