Lines Matching +full:parent +full:- +full:child
1 // SPDX-License-Identifier: GPL-2.0
21 #include <linux/pci-aspm.h>
54 struct pcie_link_state *parent; /* pointer to the parent Link state */ member
56 struct list_head children; /* list of child link states */
57 struct list_head link; /* node in parent's children list */
132 return link->aspm_default; in policy_to_aspm_state()
148 return link->clkpm_default; in policy_to_clkpm_state()
155 struct pci_dev *child; in pcie_set_clkpm_nocheck() local
156 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
159 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_set_clkpm_nocheck()
160 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, in pcie_set_clkpm_nocheck()
163 link->clkpm_enabled = !!enable; in pcie_set_clkpm_nocheck()
172 if (!link->clkpm_capable || link->clkpm_disable) in pcie_set_clkpm()
175 if (link->clkpm_enabled == enable) in pcie_set_clkpm()
185 struct pci_dev *child; in pcie_clkpm_cap_init() local
186 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_clkpm_cap_init()
189 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_clkpm_cap_init()
190 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); in pcie_clkpm_cap_init()
196 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); in pcie_clkpm_cap_init()
200 link->clkpm_enabled = enabled; in pcie_clkpm_cap_init()
201 link->clkpm_default = enabled; in pcie_clkpm_cap_init()
202 link->clkpm_capable = capable; in pcie_clkpm_cap_init()
203 link->clkpm_disable = blacklist ? 1 : 0; in pcie_clkpm_cap_init()
208 struct pci_dev *parent = link->pdev; in pcie_retrain_link() local
212 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_retrain_link()
214 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_retrain_link()
215 if (parent->clear_retrain_link) { in pcie_retrain_link()
222 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_retrain_link()
228 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); in pcie_retrain_link()
247 struct pci_dev *child, *parent = link->pdev; in pcie_aspm_configure_common_clock() local
248 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_configure_common_clock()
253 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); in pcie_aspm_configure_common_clock()
254 BUG_ON(!pci_is_pcie(child)); in pcie_aspm_configure_common_clock()
257 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); in pcie_aspm_configure_common_clock()
262 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); in pcie_aspm_configure_common_clock()
267 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
271 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
272 pcie_capability_read_word(child, PCI_EXP_LNKCTL, in pcie_aspm_configure_common_clock()
281 pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n"); in pcie_aspm_configure_common_clock()
285 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
286 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
287 child_reg[PCI_FUNC(child->devfn)] = reg16; in pcie_aspm_configure_common_clock()
292 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); in pcie_aspm_configure_common_clock()
296 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
302 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_aspm_configure_common_clock()
308 pci_err(parent, "ASPM: Could not configure common clock\n"); in pcie_aspm_configure_common_clock()
309 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_aspm_configure_common_clock()
310 pcie_capability_write_word(child, PCI_EXP_LNKCTL, in pcie_aspm_configure_common_clock()
311 child_reg[PCI_FUNC(child->devfn)]); in pcie_aspm_configure_common_clock()
312 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); in pcie_aspm_configure_common_clock()
327 return -1U; in calc_l0s_acceptable()
343 return -1U; in calc_l1_acceptable()
408 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; in pcie_get_aspm_reg()
409 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; in pcie_get_aspm_reg()
410 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; in pcie_get_aspm_reg()
412 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; in pcie_get_aspm_reg()
415 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; in pcie_get_aspm_reg()
416 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pcie_get_aspm_reg()
417 if (!info->l1ss_cap_ptr) in pcie_get_aspm_reg()
419 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP, in pcie_get_aspm_reg()
420 &info->l1ss_cap); in pcie_get_aspm_reg()
421 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) { in pcie_get_aspm_reg()
422 info->l1ss_cap = 0; in pcie_get_aspm_reg()
431 if (!pdev->ltr_path) in pcie_get_aspm_reg()
432 info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; in pcie_get_aspm_reg()
434 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, in pcie_get_aspm_reg()
435 &info->l1ss_ctl1); in pcie_get_aspm_reg()
436 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, in pcie_get_aspm_reg()
437 &info->l1ss_ctl2); in pcie_get_aspm_reg()
447 if ((endpoint->current_state != PCI_D0) && in pcie_aspm_check_latency()
448 (endpoint->current_state != PCI_UNKNOWN)) in pcie_aspm_check_latency()
451 link = endpoint->bus->self->link_state; in pcie_aspm_check_latency()
452 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; in pcie_aspm_check_latency()
456 if ((link->aspm_capable & ASPM_STATE_L0S_UP) && in pcie_aspm_check_latency()
457 (link->latency_up.l0s > acceptable->l0s)) in pcie_aspm_check_latency()
458 link->aspm_capable &= ~ASPM_STATE_L0S_UP; in pcie_aspm_check_latency()
461 if ((link->aspm_capable & ASPM_STATE_L0S_DW) && in pcie_aspm_check_latency()
462 (link->latency_dw.l0s > acceptable->l0s)) in pcie_aspm_check_latency()
463 link->aspm_capable &= ~ASPM_STATE_L0S_DW; in pcie_aspm_check_latency()
477 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); in pcie_aspm_check_latency()
478 if ((link->aspm_capable & ASPM_STATE_L1) && in pcie_aspm_check_latency()
479 (latency + l1_switch_latency > acceptable->l1)) in pcie_aspm_check_latency()
480 link->aspm_capable &= ~ASPM_STATE_L1; in pcie_aspm_check_latency()
483 link = link->parent; in pcie_aspm_check_latency()
493 struct pci_dev *child; in pci_function_0() local
495 list_for_each_entry(child, &linkbus->devices, bus_list) in pci_function_0()
496 if (PCI_FUNC(child->devfn) == 0) in pci_function_0()
497 return child; in pci_function_0()
509 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr; in aspm_calc_l1ss_info()
510 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr; in aspm_calc_l1ss_info()
511 link->l1ss.ctl1 = link->l1ss.ctl2 = 0; in aspm_calc_l1ss_info()
513 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) in aspm_calc_l1ss_info()
517 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; in aspm_calc_l1ss_info()
518 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; in aspm_calc_l1ss_info()
522 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; in aspm_calc_l1ss_info()
523 scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; in aspm_calc_l1ss_info()
524 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; in aspm_calc_l1ss_info()
525 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; in aspm_calc_l1ss_info()
527 if (calc_l1ss_pwron(link->pdev, scale1, val1) > in aspm_calc_l1ss_info()
528 calc_l1ss_pwron(link->downstream, scale2, val2)) { in aspm_calc_l1ss_info()
529 link->l1ss.ctl2 |= scale1 | (val1 << 3); in aspm_calc_l1ss_info()
530 t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1); in aspm_calc_l1ss_info()
532 link->l1ss.ctl2 |= scale2 | (val2 << 3); in aspm_calc_l1ss_info()
533 t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2); in aspm_calc_l1ss_info()
542 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and in aspm_calc_l1ss_info()
543 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at in aspm_calc_l1ss_info()
548 link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; in aspm_calc_l1ss_info()
553 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_aspm_cap_init() local
554 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_cap_init()
559 link->aspm_enabled = ASPM_STATE_ALL; in pcie_aspm_cap_init()
560 link->aspm_disable = ASPM_STATE_ALL; in pcie_aspm_cap_init()
565 pcie_get_aspm_reg(parent, &upreg); in pcie_aspm_cap_init()
566 pcie_get_aspm_reg(child, &dwreg); in pcie_aspm_cap_init()
579 * Re-read upstream/downstream components' register state in pcie_aspm_cap_init()
582 pcie_get_aspm_reg(parent, &upreg); in pcie_aspm_cap_init()
583 pcie_get_aspm_reg(child, &dwreg); in pcie_aspm_cap_init()
593 link->aspm_support |= ASPM_STATE_L0S; in pcie_aspm_cap_init()
595 link->aspm_enabled |= ASPM_STATE_L0S_UP; in pcie_aspm_cap_init()
597 link->aspm_enabled |= ASPM_STATE_L0S_DW; in pcie_aspm_cap_init()
598 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); in pcie_aspm_cap_init()
599 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); in pcie_aspm_cap_init()
603 link->aspm_support |= ASPM_STATE_L1; in pcie_aspm_cap_init()
605 link->aspm_enabled |= ASPM_STATE_L1; in pcie_aspm_cap_init()
606 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); in pcie_aspm_cap_init()
607 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); in pcie_aspm_cap_init()
611 link->aspm_support |= ASPM_STATE_L1_1; in pcie_aspm_cap_init()
613 link->aspm_support |= ASPM_STATE_L1_2; in pcie_aspm_cap_init()
615 link->aspm_support |= ASPM_STATE_L1_1_PCIPM; in pcie_aspm_cap_init()
617 link->aspm_support |= ASPM_STATE_L1_2_PCIPM; in pcie_aspm_cap_init()
620 link->aspm_enabled |= ASPM_STATE_L1_1; in pcie_aspm_cap_init()
622 link->aspm_enabled |= ASPM_STATE_L1_2; in pcie_aspm_cap_init()
624 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; in pcie_aspm_cap_init()
626 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; in pcie_aspm_cap_init()
628 if (link->aspm_support & ASPM_STATE_L1SS) in pcie_aspm_cap_init()
632 link->aspm_default = link->aspm_enabled; in pcie_aspm_cap_init()
635 link->aspm_capable = link->aspm_support; in pcie_aspm_cap_init()
638 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_cap_init()
641 &link->acceptable[PCI_FUNC(child->devfn)]; in pcie_aspm_cap_init()
643 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && in pcie_aspm_cap_init()
644 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) in pcie_aspm_cap_init()
647 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); in pcie_aspm_cap_init()
650 acceptable->l0s = calc_l0s_acceptable(encoding); in pcie_aspm_cap_init()
653 acceptable->l1 = calc_l1_acceptable(encoding); in pcie_aspm_cap_init()
655 pcie_aspm_check_latency(child); in pcie_aspm_cap_init()
674 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_l1ss() local
675 u32 up_cap_ptr = link->l1ss.up_cap_ptr; in pcie_config_aspm_l1ss()
676 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr; in pcie_config_aspm_l1ss()
678 enable_req = (link->aspm_enabled ^ state) & state; in pcie_config_aspm_l1ss()
682 * - When enabling L1.x, enable bit at parent first, then at child in pcie_config_aspm_l1ss()
683 * - When disabling L1.x, disable bit at child first, then at parent in pcie_config_aspm_l1ss()
684 * - When enabling ASPM L1.x, need to disable L1 in pcie_config_aspm_l1ss()
685 * (at child followed by parent). in pcie_config_aspm_l1ss()
686 * - The ASPM/PCIPM L1.2 must be disabled while programming timing in pcie_config_aspm_l1ss()
694 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
696 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
703 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, in pcie_config_aspm_l1ss()
705 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, in pcie_config_aspm_l1ss()
712 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2, in pcie_config_aspm_l1ss()
713 link->l1ss.ctl2); in pcie_config_aspm_l1ss()
714 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2, in pcie_config_aspm_l1ss()
715 link->l1ss.ctl2); in pcie_config_aspm_l1ss()
718 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
720 link->l1ss.ctl1); in pcie_config_aspm_l1ss()
723 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
726 link->l1ss.ctl1); in pcie_config_aspm_l1ss()
727 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
730 link->l1ss.ctl1); in pcie_config_aspm_l1ss()
744 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
746 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
759 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_link() local
760 struct pci_bus *linkbus = parent->subordinate; in pcie_config_aspm_link()
763 state &= (link->aspm_capable & ~link->aspm_disable); in pcie_config_aspm_link()
770 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) { in pcie_config_aspm_link()
772 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM); in pcie_config_aspm_link()
776 if (link->aspm_enabled == state) in pcie_config_aspm_link()
788 if (link->aspm_capable & ASPM_STATE_L1SS) in pcie_config_aspm_link()
798 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
799 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_config_aspm_link()
800 pcie_config_aspm_dev(child, dwstream); in pcie_config_aspm_link()
802 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
804 link->aspm_enabled = state; in pcie_config_aspm_link()
811 link = link->parent; in pcie_config_aspm_path()
817 link->pdev->link_state = NULL; in free_link_state()
823 struct pci_dev *child; in pcie_aspm_sanity_check() local
830 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { in pcie_aspm_sanity_check()
831 if (!pci_is_pcie(child)) in pcie_aspm_sanity_check()
832 return -EINVAL; in pcie_aspm_sanity_check()
837 * pre-1.1 device in pcie_aspm_sanity_check()
844 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use in pcie_aspm_sanity_check()
847 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); in pcie_aspm_sanity_check()
849 …pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\… in pcie_aspm_sanity_check()
850 return -EINVAL; in pcie_aspm_sanity_check()
864 INIT_LIST_HEAD(&link->sibling); in alloc_pcie_link_state()
865 INIT_LIST_HEAD(&link->children); in alloc_pcie_link_state()
866 INIT_LIST_HEAD(&link->link); in alloc_pcie_link_state()
867 link->pdev = pdev; in alloc_pcie_link_state()
868 link->downstream = pci_function_0(pdev->subordinate); in alloc_pcie_link_state()
871 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe in alloc_pcie_link_state()
879 !pdev->bus->parent->self) { in alloc_pcie_link_state()
880 link->root = link; in alloc_pcie_link_state()
882 struct pcie_link_state *parent; in alloc_pcie_link_state() local
884 parent = pdev->bus->parent->self->link_state; in alloc_pcie_link_state()
885 if (!parent) { in alloc_pcie_link_state()
890 link->parent = parent; in alloc_pcie_link_state()
891 link->root = link->parent->root; in alloc_pcie_link_state()
892 list_add(&link->link, &parent->children); in alloc_pcie_link_state()
895 list_add(&link->sibling, &link_list); in alloc_pcie_link_state()
896 pdev->link_state = link; in alloc_pcie_link_state()
913 if (pdev->link_state) in pcie_aspm_init_link_state()
921 if (!pdev->has_secondary_link) in pcie_aspm_init_link_state()
926 pdev->bus->self) in pcie_aspm_init_link_state()
930 if (list_empty(&pdev->subordinate->devices)) in pcie_aspm_init_link_state()
971 BUG_ON(root->parent); in pcie_update_aspm_capable()
973 if (link->root != root) in pcie_update_aspm_capable()
975 link->aspm_capable = link->aspm_support; in pcie_update_aspm_capable()
978 struct pci_dev *child; in pcie_update_aspm_capable() local
979 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_update_aspm_capable()
980 if (link->root != root) in pcie_update_aspm_capable()
982 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_update_aspm_capable()
983 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) && in pcie_update_aspm_capable()
984 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)) in pcie_update_aspm_capable()
986 pcie_aspm_check_latency(child); in pcie_update_aspm_capable()
994 struct pci_dev *parent = pdev->bus->self; in pcie_aspm_exit_link_state() local
997 if (!parent || !parent->link_state) in pcie_aspm_exit_link_state()
1006 if (!list_empty(&parent->subordinate->devices)) in pcie_aspm_exit_link_state()
1009 link = parent->link_state; in pcie_aspm_exit_link_state()
1010 root = link->root; in pcie_aspm_exit_link_state()
1011 parent_link = link->parent; in pcie_aspm_exit_link_state()
1015 list_del(&link->sibling); in pcie_aspm_exit_link_state()
1016 list_del(&link->link); in pcie_aspm_exit_link_state()
1033 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_pm_state_change()
1043 pcie_update_aspm_capable(link->root); in pcie_aspm_pm_state_change()
1051 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_powersave_config_link()
1070 struct pci_dev *parent = pdev->bus->self; in __pci_disable_link_state() local
1076 if (pdev->has_secondary_link) in __pci_disable_link_state()
1077 parent = pdev; in __pci_disable_link_state()
1078 if (!parent || !parent->link_state) in __pci_disable_link_state()
1097 link = parent->link_state; in __pci_disable_link_state()
1099 link->aspm_disable |= ASPM_STATE_L0S; in __pci_disable_link_state()
1101 link->aspm_disable |= ASPM_STATE_L1; in __pci_disable_link_state()
1105 link->clkpm_disable = 1; in __pci_disable_link_state()
1119 * pci_disable_link_state - Disable device's link state, so the link will
1140 return -EPERM; in pcie_aspm_set_policy()
1180 struct pcie_link_state *link_state = pci_device->link_state; in link_state_show()
1182 return sprintf(buf, "%d\n", link_state->aspm_enabled); in link_state_show()
1191 struct pcie_link_state *link, *root = pdev->link_state->root; in link_state_store()
1195 return -EPERM; in link_state_store()
1198 return -EINVAL; in link_state_store()
1200 return -EINVAL; in link_state_store()
1205 if (link->root != root) in link_state_store()
1219 struct pcie_link_state *link_state = pci_device->link_state; in clk_ctl_show()
1221 return sprintf(buf, "%d\n", link_state->clkpm_enabled); in clk_ctl_show()
1233 return -EINVAL; in clk_ctl_store()
1237 pcie_set_clkpm_nocheck(pdev->link_state, state); in clk_ctl_store()
1250 struct pcie_link_state *link_state = pdev->link_state; in pcie_aspm_create_sysfs_dev_files()
1255 if (link_state->aspm_support) in pcie_aspm_create_sysfs_dev_files()
1256 sysfs_add_file_to_group(&pdev->dev.kobj, in pcie_aspm_create_sysfs_dev_files()
1258 if (link_state->clkpm_capable) in pcie_aspm_create_sysfs_dev_files()
1259 sysfs_add_file_to_group(&pdev->dev.kobj, in pcie_aspm_create_sysfs_dev_files()
1265 struct pcie_link_state *link_state = pdev->link_state; in pcie_aspm_remove_sysfs_dev_files()
1270 if (link_state->aspm_support) in pcie_aspm_remove_sysfs_dev_files()
1271 sysfs_remove_file_from_group(&pdev->dev.kobj, in pcie_aspm_remove_sysfs_dev_files()
1273 if (link_state->clkpm_capable) in pcie_aspm_remove_sysfs_dev_files()
1274 sysfs_remove_file_from_group(&pdev->dev.kobj, in pcie_aspm_remove_sysfs_dev_files()