Lines Matching +full:0 +full:x0000fc00
40 * indirectly from the SDS offset at 0x2000. It is only required for
42 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
43 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
48 * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
64 #define SERDES_PLL_INDIRECT_OFFSET 0x0000
65 #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
66 #define SERDES_INDIRECT_OFFSET 0x0400
67 #define SERDES_LANE_STRIDE 0x0200
70 #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
71 #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 }
72 #define DEFAULT_SATA_TXEYETUNING { 0xa, 0xa, 0xa }
73 #define DEFAULT_SATA_SPD_SEL { 0x1, 0x3, 0x7 }
74 #define DEFAULT_SATA_TXAMP { 0x8, 0x8, 0x8 }
75 #define DEFAULT_SATA_TXCN1 { 0x2, 0x2, 0x2 }
76 #define DEFAULT_SATA_TXCN2 { 0x0, 0x0, 0x0 }
77 #define DEFAULT_SATA_TXCP1 { 0xa, 0xa, 0xa }
79 #define SATA_SPD_SEL_GEN3 0x7
80 #define SATA_SPD_SEL_GEN2 0x3
81 #define SATA_SPD_SEL_GEN1 0x1
83 #define SSC_DISABLE 0
86 #define FBDIV_VAL_50M 0x77
87 #define REFDIV_VAL_50M 0x1
88 #define FBDIV_VAL_100M 0x3B
89 #define REFDIV_VAL_100M 0x0
92 #define SATACLKENREG 0x00000000
93 #define SATA0_CORE_CLKEN 0x00000002
94 #define SATA1_CORE_CLKEN 0x00000004
95 #define SATASRESETREG 0x00000004
96 #define SATA_MEM_RESET_MASK 0x00000020
97 #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5)
98 #define SATA_SDS_RESET_MASK 0x00000004
99 #define SATA_CSR_RESET_MASK 0x00000001
100 #define SATA_CORE_RESET_MASK 0x00000002
101 #define SATA_PMCLK_RESET_MASK 0x00000010
102 #define SATA_PCLK_RESET_MASK 0x00000008
105 #define SATA_ENET_SDS_PCS_CTL0 0x00000000
107 (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
109 (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
110 #define SATA_ENET_SDS_CTL0 0x0000000c
112 (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
113 #define SATA_ENET_SDS_CTL1 0x00000010
115 (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
116 #define SATA_ENET_SDS_RST_CTL 0x00000024
117 #define SATA_ENET_SDS_IND_CMD_REG 0x0000003c
118 #define CFG_IND_WR_CMD_MASK 0x00000001
119 #define CFG_IND_RD_CMD_MASK 0x00000002
120 #define CFG_IND_CMD_DONE_MASK 0x00000004
122 (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
123 #define SATA_ENET_SDS_IND_RDATA_REG 0x00000040
124 #define SATA_ENET_SDS_IND_WDATA_REG 0x00000044
125 #define SATA_ENET_CLK_MACRO_REG 0x0000004c
127 (((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001))
129 (((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000))
131 (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
132 #define O_PLL_LOCK_RD(src) (((src) & 0x40000000) >> 30)
133 #define O_PLL_READY_RD(src) (((src) & 0x80000000) >> 31)
136 #define CMU_REG0 0x00000
137 #define CMU_REG0_PLL_REF_SEL_MASK 0x00002000
139 (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
140 #define CMU_REG0_PDOWN_MASK 0x00004000
142 (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
143 #define CMU_REG1 0x00002
145 (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
147 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
149 (((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0))
150 #define CMU_REG1_REFCLK_CMOS_SEL_MASK 0x00000001
152 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
153 #define CMU_REG2 0x00004
155 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
157 (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
159 (((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0))
160 #define CMU_REG3 0x00006
162 (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
164 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
166 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
167 #define CMU_REG4 0x00008
168 #define CMU_REG5 0x0000a
170 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
172 (((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e))
174 (((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000))
175 #define CMU_REG5_PLL_RESETB_MASK 0x00000001
176 #define CMU_REG6 0x0000c
178 (((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600))
180 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
181 #define CMU_REG7 0x0000e
182 #define CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14)
183 #define CMU_REG7_VCO_CAL_FAIL_RD(src) ((0x00000c00 & (u32) (src)) >> 10)
184 #define CMU_REG8 0x00010
185 #define CMU_REG9 0x00012
186 #define CMU_REG9_WORD_LEN_8BIT 0x000
187 #define CMU_REG9_WORD_LEN_10BIT 0x001
188 #define CMU_REG9_WORD_LEN_16BIT 0x002
189 #define CMU_REG9_WORD_LEN_20BIT 0x003
190 #define CMU_REG9_WORD_LEN_32BIT 0x004
191 #define CMU_REG9_WORD_LEN_40BIT 0x005
192 #define CMU_REG9_WORD_LEN_64BIT 0x006
193 #define CMU_REG9_WORD_LEN_66BIT 0x007
195 (((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380))
197 (((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070))
199 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
201 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
203 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
204 #define CMU_REG10 0x00014
206 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
207 #define CMU_REG11 0x00016
208 #define CMU_REG12 0x00018
210 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
211 #define CMU_REG13 0x0001a
212 #define CMU_REG14 0x0001c
213 #define CMU_REG15 0x0001e
214 #define CMU_REG16 0x00020
215 #define CMU_REG16_PVT_DN_MAN_ENA_MASK 0x00000001
216 #define CMU_REG16_PVT_UP_MAN_ENA_MASK 0x00000002
218 (((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c))
220 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
222 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
223 #define CMU_REG17 0x00022
225 (((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00))
227 (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
228 #define CMU_REG17_PVT_TERM_MAN_ENA_MASK 0x00008000
229 #define CMU_REG18 0x00024
230 #define CMU_REG19 0x00026
231 #define CMU_REG20 0x00028
232 #define CMU_REG21 0x0002a
233 #define CMU_REG22 0x0002c
234 #define CMU_REG23 0x0002e
235 #define CMU_REG24 0x00030
236 #define CMU_REG25 0x00032
237 #define CMU_REG26 0x00034
239 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
240 #define CMU_REG27 0x00036
241 #define CMU_REG28 0x00038
242 #define CMU_REG29 0x0003a
243 #define CMU_REG30 0x0003c
245 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
247 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
248 #define CMU_REG31 0x0003e
249 #define CMU_REG32 0x00040
250 #define CMU_REG32_FORCE_VCOCAL_START_MASK 0x00004000
252 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
254 (((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180))
255 #define CMU_REG33 0x00042
256 #define CMU_REG34 0x00044
258 (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
260 (((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00))
262 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
264 (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
265 #define CMU_REG35 0x00046
267 (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
268 #define CMU_REG36 0x00048
270 (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
272 (((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0))
274 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
275 #define CMU_REG37 0x0004a
276 #define CMU_REG38 0x0004c
277 #define CMU_REG39 0x0004e
280 #define RXTX_REG0 0x000
282 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
284 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
286 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
287 #define RXTX_REG1 0x002
289 (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
291 (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
293 (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
295 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
296 #define RXTX_REG2 0x004
298 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
300 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
302 (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
303 #define RXTX_REG4 0x008
304 #define RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK 0x00000040
306 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
308 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
309 #define RXTX_REG5 0x00a
311 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
313 (((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0))
315 (((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f))
316 #define RXTX_REG6 0x00c
318 (((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780))
320 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
322 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
324 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
326 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
327 #define RXTX_REG7 0x00e
328 #define RXTX_REG7_RESETB_RXD_MASK 0x00000100
329 #define RXTX_REG7_RESETB_RXA_MASK 0x00000080
331 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
333 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
334 #define RXTX_REG8 0x010
336 (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
338 (((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800))
340 (((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200))
342 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
344 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
345 #define RXTX_REG7 0x00e
347 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
349 (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
350 #define RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK 0x00004000
352 (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
353 #define RXTX_REG11 0x016
355 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
356 #define RXTX_REG12 0x018
358 (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
360 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
361 #define RXTX_REG12_RX_DET_TERM_ENABLE_MASK 0x00000002
363 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
364 #define RXTX_REG13 0x01a
365 #define RXTX_REG14 0x01c
367 (((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f))
369 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
370 #define RXTX_REG26 0x034
372 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
374 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
375 #define RXTX_REG21 0x02a
376 #define RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
377 #define RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
378 #define RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src) ((0x0000000f & (u32)(src)))
379 #define RXTX_REG22 0x02c
380 #define RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
381 #define RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
382 #define RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src) ((0x0000000f & (u32)(src)))
383 #define RXTX_REG23 0x02e
384 #define RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
385 #define RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
386 #define RXTX_REG24 0x030
387 #define RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
388 #define RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
389 #define RXTX_REG27 0x036
390 #define RXTX_REG28 0x038
391 #define RXTX_REG31 0x03e
392 #define RXTX_REG38 0x04c
394 (((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe))
395 #define RXTX_REG39 0x04e
396 #define RXTX_REG40 0x050
397 #define RXTX_REG41 0x052
398 #define RXTX_REG42 0x054
399 #define RXTX_REG43 0x056
400 #define RXTX_REG44 0x058
401 #define RXTX_REG45 0x05a
402 #define RXTX_REG46 0x05c
403 #define RXTX_REG47 0x05e
404 #define RXTX_REG48 0x060
405 #define RXTX_REG49 0x062
406 #define RXTX_REG50 0x064
407 #define RXTX_REG51 0x066
408 #define RXTX_REG52 0x068
409 #define RXTX_REG53 0x06a
410 #define RXTX_REG54 0x06c
411 #define RXTX_REG55 0x06e
412 #define RXTX_REG61 0x07a
414 (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
416 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
418 (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
420 (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
421 #define RXTX_REG62 0x07c
423 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
424 #define RXTX_REG81 0x0a2
426 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
428 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
430 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
431 #define RXTX_REG96 0x0c0
433 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
435 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
437 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
438 #define RXTX_REG99 0x0c6
440 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
442 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
444 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
445 #define RXTX_REG102 0x0cc
447 (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
448 #define RXTX_REG114 0x0e4
449 #define RXTX_REG121 0x0f2
450 #define RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1)
451 #define RXTX_REG125 0x0fa
453 (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
455 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
457 (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
459 (((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c))
461 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
462 #define RXTX_REG127 0x0fe
463 #define RXTX_REG127_FORCE_SUM_CAL_START_MASK 0x00000002
464 #define RXTX_REG127_FORCE_LAT_CAL_START_MASK 0x00000004
466 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
468 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
470 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
472 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
474 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
475 #define RXTX_REG128 0x100
477 (((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c))
479 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
481 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
482 #define RXTX_REG129 0x102
484 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
486 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
487 #define RXTX_REG130 0x104
489 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
491 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
492 #define RXTX_REG145 0x122
494 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
496 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
498 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
500 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
501 #define RXTX_REG147 0x126
502 #define RXTX_REG148 0x128
506 REF_CMU = 0, /* Clock macro is the internal reference clock */
511 MUX_SELECT_ATA = 0, /* Switch the MUX to ATA */
512 MUX_SELECT_SGMMII = 0, /* Switch the MUX to SGMII */
516 CLK_EXT_DIFF = 0, /* External differential */
522 MODE_SATA = 0, /* List them for simple reference */
559 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
580 pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n", in sds_wr()
601 pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n", in sds_rd()
619 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
633 pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data); in cmu_rd()
680 pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, in serdes_wr()
692 pr_debug("SERDES RD addr 0x%X value 0x%08X\n", reg, *data); in serdes_rd()
723 val = CMU_REG12_STATE_DELAY9_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
726 cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222); in xgene_phy_cfg_cmu_clk_type()
727 cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225); in xgene_phy_cfg_cmu_clk_type()
733 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
737 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
743 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
747 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
758 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
762 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
779 val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
780 val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc); in xgene_phy_sata_cfg_cmu_core()
781 val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
782 val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8); in xgene_phy_sata_cfg_cmu_core()
789 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
791 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
796 val = CMU_REG1_PLL_CP_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
798 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5); in xgene_phy_sata_cfg_cmu_core()
800 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
802 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
804 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
813 val = CMU_REG2_PLL_LFRES_SET(val, 0xa); in xgene_phy_sata_cfg_cmu_core()
816 val = CMU_REG2_PLL_LFRES_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
818 ref_100MHz = 0; in xgene_phy_sata_cfg_cmu_core()
834 val = CMU_REG3_VCOVARSEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
835 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10); in xgene_phy_sata_cfg_cmu_core()
837 val = CMU_REG3_VCOVARSEL_SET(val, 0xF); in xgene_phy_sata_cfg_cmu_core()
839 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15); in xgene_phy_sata_cfg_cmu_core()
841 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a); in xgene_phy_sata_cfg_cmu_core()
842 val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15); in xgene_phy_sata_cfg_cmu_core()
848 val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
853 val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
854 val = CMU_REG5_PLL_LFCAP_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
856 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
858 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
863 val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2); in xgene_phy_sata_cfg_cmu_core()
864 val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0); in xgene_phy_sata_cfg_cmu_core()
874 val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
876 val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
877 val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0); in xgene_phy_sata_cfg_cmu_core()
883 val = CMU_REG10_VREG_REFSEL_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
889 val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
890 val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
892 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
894 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
899 val = CMU_REG30_PCIE_MODE_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
900 val = CMU_REG30_LOCK_COUNT_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
904 cmu_wr(ctx, cmu_type, CMU_REG31, 0xF); in xgene_phy_sata_cfg_cmu_core()
907 val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
909 val = CMU_REG32_IREF_ADJ_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
911 val = CMU_REG32_IREF_ADJ_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
916 cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27); in xgene_phy_sata_cfg_cmu_core()
918 cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c); in xgene_phy_sata_cfg_cmu_core()
921 cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F); in xgene_phy_sata_cfg_cmu_core()
957 for (lane = 0; lane < MAX_LANE; lane++) { in xgene_phy_sata_cfg_lanes()
958 serdes_wr(ctx, lane, RXTX_REG147, 0x6); in xgene_phy_sata_cfg_lanes()
962 val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
963 val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
964 val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
969 val = RXTX_REG1_RXACVCM_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
978 val = RXTX_REG2_VTT_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
979 val = RXTX_REG2_VTT_SEL_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
980 val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
990 val = RXTX_REG1_RXVREG1_SET(val, 0x2); in xgene_phy_sata_cfg_lanes()
991 val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2); in xgene_phy_sata_cfg_lanes()
1013 val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1014 val = RXTX_REG6_TX_IDLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1015 val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1016 val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1021 val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1027 val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1028 val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1029 val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1030 val = RXTX_REG8_SD_DISABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1031 val = RXTX_REG8_SD_VREF_SET(val, 0x4); in xgene_phy_sata_cfg_lanes()
1036 val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1041 val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1042 val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1043 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1048 val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1049 val = RXTX_REG26_BLWC_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1052 serdes_wr(ctx, lane, RXTX_REG28, 0x0); in xgene_phy_sata_cfg_lanes()
1055 serdes_wr(ctx, lane, RXTX_REG31, 0x0); in xgene_phy_sata_cfg_lanes()
1059 val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1060 val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1061 val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1065 val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1069 for (i = 0; i < 9; i++) { in xgene_phy_sata_cfg_lanes()
1072 val = RXTX_REG89_MU_TH7_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1073 val = RXTX_REG89_MU_TH8_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1074 val = RXTX_REG89_MU_TH9_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1079 for (i = 0; i < 3; i++) { in xgene_phy_sata_cfg_lanes()
1082 val = RXTX_REG96_MU_FREQ1_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1083 val = RXTX_REG96_MU_FREQ2_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1084 val = RXTX_REG96_MU_FREQ3_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1089 for (i = 0; i < 3; i++) { in xgene_phy_sata_cfg_lanes()
1092 val = RXTX_REG99_MU_PHASE1_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1093 val = RXTX_REG99_MU_PHASE2_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1094 val = RXTX_REG99_MU_PHASE3_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1099 val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1102 serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); in xgene_phy_sata_cfg_lanes()
1111 val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1115 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1119 val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_lanes()
1123 val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3); in xgene_phy_sata_cfg_lanes()
1124 val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1126 val = RXTX_REG145_RXES_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1127 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1129 val = RXTX_REG145_RXES_ENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1130 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1138 for (i = 0; i < 4; i++) { in xgene_phy_sata_cfg_lanes()
1140 serdes_wr(ctx, lane, reg, 0xFFFF); in xgene_phy_sata_cfg_lanes()
1154 writel(0xdf, csr_serdes + SATA_ENET_SDS_RST_CTL); in xgene_phy_cal_rdy_chk()
1166 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1192 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12); in xgene_phy_cal_rdy_chk()
1193 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1203 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29); in xgene_phy_cal_rdy_chk()
1204 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1210 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28); in xgene_phy_cal_rdy_chk()
1211 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1228 } while (--loop > 0); in xgene_phy_cal_rdy_chk()
1241 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1242 return 0; in xgene_phy_cal_rdy_chk()
1254 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); in xgene_phy_pdwn_force_vco()
1273 writel(0x0, sds_base + SATA_ENET_SDS_RST_CTL); in xgene_phy_hw_init_sata()
1276 writel(0x20, sds_base + SATA_ENET_SDS_RST_CTL); in xgene_phy_hw_init_sata()
1279 writel(0xde, sds_base + SATA_ENET_SDS_RST_CTL); in xgene_phy_hw_init_sata()
1285 ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); in xgene_phy_hw_init_sata()
1290 val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421); in xgene_phy_hw_init_sata()
1308 val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3); in xgene_phy_hw_init_sata()
1309 val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3); in xgene_phy_hw_init_sata()
1319 } while (--i > 0); in xgene_phy_hw_init_sata()
1321 if (i <= 0) in xgene_phy_hw_init_sata()
1324 return 0; in xgene_phy_hw_init_sata()
1345 return 0; in xgene_phy_hw_initialize()
1361 {RXTX_REG38, 0x0}, in xgene_phy_force_lat_summer_cal()
1362 {RXTX_REG39, 0xff00}, in xgene_phy_force_lat_summer_cal()
1363 {RXTX_REG40, 0xffff}, in xgene_phy_force_lat_summer_cal()
1364 {RXTX_REG41, 0xffff}, in xgene_phy_force_lat_summer_cal()
1365 {RXTX_REG42, 0xffff}, in xgene_phy_force_lat_summer_cal()
1366 {RXTX_REG43, 0xffff}, in xgene_phy_force_lat_summer_cal()
1367 {RXTX_REG44, 0xffff}, in xgene_phy_force_lat_summer_cal()
1368 {RXTX_REG45, 0xffff}, in xgene_phy_force_lat_summer_cal()
1369 {RXTX_REG46, 0xffff}, in xgene_phy_force_lat_summer_cal()
1370 {RXTX_REG47, 0xfffc}, in xgene_phy_force_lat_summer_cal()
1371 {RXTX_REG48, 0x0}, in xgene_phy_force_lat_summer_cal()
1372 {RXTX_REG49, 0x0}, in xgene_phy_force_lat_summer_cal()
1373 {RXTX_REG50, 0x0}, in xgene_phy_force_lat_summer_cal()
1374 {RXTX_REG51, 0x0}, in xgene_phy_force_lat_summer_cal()
1375 {RXTX_REG52, 0x0}, in xgene_phy_force_lat_summer_cal()
1376 {RXTX_REG53, 0x0}, in xgene_phy_force_lat_summer_cal()
1377 {RXTX_REG54, 0x0}, in xgene_phy_force_lat_summer_cal()
1378 {RXTX_REG55, 0x0}, in xgene_phy_force_lat_summer_cal()
1409 serdes_wr(ctx, lane, RXTX_REG28, 0x7); in xgene_phy_force_lat_summer_cal()
1410 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_force_lat_summer_cal()
1415 for (i = 0; i < ARRAY_SIZE(serdes_reg); i++) in xgene_phy_force_lat_summer_cal()
1437 int avg_loop = 0; in xgene_phy_gen_avg_val()
1438 int lat_do = 0, lat_xo = 0, lat_eo = 0, lat_so = 0; in xgene_phy_gen_avg_val()
1439 int lat_de = 0, lat_xe = 0, lat_ee = 0, lat_se = 0; in xgene_phy_gen_avg_val()
1440 int sum_cal = 0; in xgene_phy_gen_avg_val()
1455 serdes_wr(ctx, lane, RXTX_REG28, 0x0000); in xgene_phy_gen_avg_val()
1457 serdes_wr(ctx, lane, RXTX_REG31, 0x0000); in xgene_phy_gen_avg_val()
1492 if ((fail_even == 0 || fail_even == 1) && in xgene_phy_gen_avg_val()
1493 (fail_odd == 0 || fail_odd == 1)) { in xgene_phy_gen_avg_val()
1505 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1508 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1511 dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); in xgene_phy_gen_avg_val()
1557 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1562 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1567 dev_dbg(ctx->dev, "SUM 0x%x\n", in xgene_phy_gen_avg_val()
1571 val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1); in xgene_phy_gen_avg_val()
1576 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1); in xgene_phy_gen_avg_val()
1582 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0); in xgene_phy_gen_avg_val()
1585 serdes_wr(ctx, lane, RXTX_REG28, 0x0007); in xgene_phy_gen_avg_val()
1587 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_gen_avg_val()
1611 for (i = 0; i < MAX_LANE; i++) in xgene_phy_hw_init()
1615 return 0; in xgene_phy_hw_init()
1628 if (args->args_count <= 0) in xgene_phy_xlate()
1630 if (args->args[0] < MODE_SATA || args->args[0] >= MODE_MAX) in xgene_phy_xlate()
1633 ctx->mode = args->args[0]; in xgene_phy_xlate()
1646 for (i = 0; i < count; i++) in xgene_phy_get_param()
1651 for (i = 0; i < count; i++) in xgene_phy_get_param()
1676 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in xgene_phy_probe()
1701 for (i = 0; i < MAX_LANE; i++) in xgene_phy_probe()