Lines Matching +full:1 +full:- +full:lane
2 * AppliedMicro X-Gene Multi-purpose PHY driver
22 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
31 * -----------------
32 * | Internal | |------|
33 * | Ref PLL CMU |----| | ------------- ---------
34 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
35 * | | | | ---------
36 * External Clock ------| | -------------
37 * |------|
84 #define SSC_ENABLE 1
157 (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
172 (((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e))
203 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
245 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
252 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
279 /* PHY lane CSR accessing from SDS indirectly */
286 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
295 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
326 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
363 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
394 (((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe))
430 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
437 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
444 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
461 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
466 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
496 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
507 PHY_CMU = 1, /* Clock macro is the PLL for the Serdes */
517 CLK_INT_DIFF = 1, /* Internal differential */
523 MODE_SGMII = 1,
531 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
537 u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */
538 u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */
539 u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */
556 * To enable, pass boot argument phy_xgene.preA3Chip=1
559 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
608 void __iomem *sds_base = ctx->sds_base; in cmu_wr()
619 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
625 void __iomem *sds_base = ctx->sds_base; in cmu_rd()
669 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
671 void __iomem *sds_base = ctx->sds_base; in serdes_wr()
675 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
680 pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, in serdes_wr()
684 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
686 void __iomem *sds_base = ctx->sds_base; in serdes_rd()
689 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
695 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
700 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
702 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
705 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
710 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
712 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
739 dev_dbg(ctx->dev, "Set external reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
749 dev_dbg(ctx->dev, "Set internal reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
764 dev_dbg(ctx->dev, in xgene_phy_cfg_cmu_clk_type()
814 ref_100MHz = 1; in xgene_phy_sata_cfg_cmu_core()
820 ref_100MHz = 1; in xgene_phy_sata_cfg_cmu_core()
867 /* Configure lane for 20-bits */ in xgene_phy_sata_cfg_cmu_core()
937 val = CMU_REG36_PLL_SSC_EN_SET(val, 1); in xgene_phy_ssc_enable()
938 val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1); in xgene_phy_ssc_enable()
955 int lane; in xgene_phy_sata_cfg_lanes() local
957 for (lane = 0; lane < MAX_LANE; lane++) { in xgene_phy_sata_cfg_lanes()
958 serdes_wr(ctx, lane, RXTX_REG147, 0x6); in xgene_phy_sata_cfg_lanes()
961 serdes_rd(ctx, lane, RXTX_REG0, &val); in xgene_phy_sata_cfg_lanes()
965 serdes_wr(ctx, lane, RXTX_REG0, val); in xgene_phy_sata_cfg_lanes()
968 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
971 ctx->sata_param.txboostgain[lane * 3 + in xgene_phy_sata_cfg_lanes()
972 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
973 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
977 serdes_rd(ctx, lane, RXTX_REG2, &val); in xgene_phy_sata_cfg_lanes()
981 serdes_wr(ctx, lane, RXTX_REG2, val); in xgene_phy_sata_cfg_lanes()
983 /* Configure Tx for 20-bits */ in xgene_phy_sata_cfg_lanes()
984 serdes_rd(ctx, lane, RXTX_REG4, &val); in xgene_phy_sata_cfg_lanes()
986 serdes_wr(ctx, lane, RXTX_REG4, val); in xgene_phy_sata_cfg_lanes()
989 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
992 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
995 /* Set pre-emphasis first 1 and 2, and post-emphasis values */ in xgene_phy_sata_cfg_lanes()
996 serdes_rd(ctx, lane, RXTX_REG5, &val); in xgene_phy_sata_cfg_lanes()
998 ctx->sata_param.txprecursor_cn1[lane * 3 + in xgene_phy_sata_cfg_lanes()
999 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1001 ctx->sata_param.txpostcursor_cp1[lane * 3 + in xgene_phy_sata_cfg_lanes()
1002 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1004 ctx->sata_param.txprecursor_cn2[lane * 3 + in xgene_phy_sata_cfg_lanes()
1005 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1006 serdes_wr(ctx, lane, RXTX_REG5, val); in xgene_phy_sata_cfg_lanes()
1009 serdes_rd(ctx, lane, RXTX_REG6, &val); in xgene_phy_sata_cfg_lanes()
1011 ctx->sata_param.txamplitude[lane * 3 + in xgene_phy_sata_cfg_lanes()
1012 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1017 serdes_wr(ctx, lane, RXTX_REG6, val); in xgene_phy_sata_cfg_lanes()
1019 /* Configure Rx for 20-bits */ in xgene_phy_sata_cfg_lanes()
1020 serdes_rd(ctx, lane, RXTX_REG7, &val); in xgene_phy_sata_cfg_lanes()
1023 serdes_wr(ctx, lane, RXTX_REG7, val); in xgene_phy_sata_cfg_lanes()
1026 serdes_rd(ctx, lane, RXTX_REG8, &val); in xgene_phy_sata_cfg_lanes()
1032 serdes_wr(ctx, lane, RXTX_REG8, val); in xgene_phy_sata_cfg_lanes()
1035 serdes_rd(ctx, lane, RXTX_REG11, &val); in xgene_phy_sata_cfg_lanes()
1037 serdes_wr(ctx, lane, RXTX_REG11, val); in xgene_phy_sata_cfg_lanes()
1040 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_sata_cfg_lanes()
1044 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_sata_cfg_lanes()
1047 serdes_rd(ctx, lane, RXTX_REG26, &val); in xgene_phy_sata_cfg_lanes()
1050 serdes_wr(ctx, lane, RXTX_REG26, val); in xgene_phy_sata_cfg_lanes()
1052 serdes_wr(ctx, lane, RXTX_REG28, 0x0); in xgene_phy_sata_cfg_lanes()
1055 serdes_wr(ctx, lane, RXTX_REG31, 0x0); in xgene_phy_sata_cfg_lanes()
1057 /* Set Eye Monitor counter width to 12-bit */ in xgene_phy_sata_cfg_lanes()
1058 serdes_rd(ctx, lane, RXTX_REG61, &val); in xgene_phy_sata_cfg_lanes()
1062 serdes_wr(ctx, lane, RXTX_REG61, val); in xgene_phy_sata_cfg_lanes()
1064 serdes_rd(ctx, lane, RXTX_REG62, &val); in xgene_phy_sata_cfg_lanes()
1066 serdes_wr(ctx, lane, RXTX_REG62, val); in xgene_phy_sata_cfg_lanes()
1071 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1075 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1081 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1085 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1091 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1095 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1098 serdes_rd(ctx, lane, RXTX_REG102, &val); in xgene_phy_sata_cfg_lanes()
1100 serdes_wr(ctx, lane, RXTX_REG102, val); in xgene_phy_sata_cfg_lanes()
1102 serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); in xgene_phy_sata_cfg_lanes()
1104 serdes_rd(ctx, lane, RXTX_REG125, &val); in xgene_phy_sata_cfg_lanes()
1106 ctx->sata_param.txeyedirection[lane * 3 + in xgene_phy_sata_cfg_lanes()
1107 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1109 ctx->sata_param.txeyetuning[lane * 3 + in xgene_phy_sata_cfg_lanes()
1110 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1112 serdes_wr(ctx, lane, RXTX_REG125, val); in xgene_phy_sata_cfg_lanes()
1114 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_sata_cfg_lanes()
1116 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_sata_cfg_lanes()
1118 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_sata_cfg_lanes()
1120 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_sata_cfg_lanes()
1122 serdes_rd(ctx, lane, RXTX_REG145, &val); in xgene_phy_sata_cfg_lanes()
1132 serdes_wr(ctx, lane, RXTX_REG145, val); in xgene_phy_sata_cfg_lanes()
1140 serdes_wr(ctx, lane, reg, 0xFFFF); in xgene_phy_sata_cfg_lanes()
1149 void __iomem *csr_serdes = ctx->sds_base; in xgene_phy_cal_rdy_chk()
1198 * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN in xgene_phy_cal_rdy_chk()
1217 /* Poll the PLL calibration completion status for at least 1 ms */ in xgene_phy_cal_rdy_chk()
1228 } while (--loop > 0); in xgene_phy_cal_rdy_chk()
1231 dev_dbg(ctx->dev, "PLL calibration %s\n", in xgene_phy_cal_rdy_chk()
1234 dev_err(ctx->dev, in xgene_phy_cal_rdy_chk()
1236 return -1; in xgene_phy_cal_rdy_chk()
1238 dev_dbg(ctx->dev, "PLL calibration successful\n"); in xgene_phy_cal_rdy_chk()
1241 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1251 dev_dbg(ctx->dev, "Reset VCO and re-start again\n"); in xgene_phy_pdwn_force_vco()
1266 void __iomem *sds_base = ctx->sds_base; in xgene_phy_hw_init_sata()
1271 dev_dbg(ctx->dev, "Reset PHY\n"); in xgene_phy_hw_init_sata()
1275 /* Release PHY lane from reset (active high) */ in xgene_phy_hw_init_sata()
1285 ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); in xgene_phy_hw_init_sata()
1288 dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n"); in xgene_phy_hw_init_sata()
1306 /* Set Rx/Tx 20-bit */ in xgene_phy_hw_init_sata()
1319 } while (--i > 0); in xgene_phy_hw_init_sata()
1322 dev_err(ctx->dev, "PLL calibration failed\n"); in xgene_phy_hw_init_sata()
1333 dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); in xgene_phy_hw_initialize()
1335 if (ctx->mode == MODE_SATA) { in xgene_phy_hw_initialize()
1340 dev_err(ctx->dev, "Un-supported customer pin mode %d\n", in xgene_phy_hw_initialize()
1341 ctx->mode); in xgene_phy_hw_initialize()
1342 return -ENODEV; in xgene_phy_hw_initialize()
1351 * Calibrate the receiver signal path offset in two steps - summar and
1354 static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_force_lat_summer_cal() argument
1382 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1389 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1398 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1405 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1408 /* Configure the PHY lane for calibration */ in xgene_phy_force_lat_summer_cal()
1409 serdes_wr(ctx, lane, RXTX_REG28, 0x7); in xgene_phy_force_lat_summer_cal()
1410 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_force_lat_summer_cal()
1411 serdes_clrbits(ctx, lane, RXTX_REG4, in xgene_phy_force_lat_summer_cal()
1413 serdes_clrbits(ctx, lane, RXTX_REG7, in xgene_phy_force_lat_summer_cal()
1416 serdes_wr(ctx, lane, serdes_reg[i].reg, in xgene_phy_force_lat_summer_cal()
1420 static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_reset_rxd() argument
1423 serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1426 serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1434 static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_gen_avg_val() argument
1448 dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n", in xgene_phy_gen_avg_val()
1449 lane); in xgene_phy_gen_avg_val()
1451 /* Enable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1452 serdes_setbits(ctx, lane, RXTX_REG12, in xgene_phy_gen_avg_val()
1455 serdes_wr(ctx, lane, RXTX_REG28, 0x0000); in xgene_phy_gen_avg_val()
1457 serdes_wr(ctx, lane, RXTX_REG31, 0x0000); in xgene_phy_gen_avg_val()
1461 * Calibrate the receiver signal path offset in two steps - summar in xgene_phy_gen_avg_val()
1468 xgene_phy_force_lat_summer_cal(ctx, lane); in xgene_phy_gen_avg_val()
1470 serdes_rd(ctx, lane, RXTX_REG21, &val); in xgene_phy_gen_avg_val()
1475 serdes_rd(ctx, lane, RXTX_REG22, &val); in xgene_phy_gen_avg_val()
1480 serdes_rd(ctx, lane, RXTX_REG23, &val); in xgene_phy_gen_avg_val()
1484 serdes_rd(ctx, lane, RXTX_REG24, &val); in xgene_phy_gen_avg_val()
1488 serdes_rd(ctx, lane, RXTX_REG121, &val); in xgene_phy_gen_avg_val()
1492 if ((fail_even == 0 || fail_even == 1) && in xgene_phy_gen_avg_val()
1493 (fail_odd == 0 || fail_odd == 1)) { in xgene_phy_gen_avg_val()
1504 dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop); in xgene_phy_gen_avg_val()
1505 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1508 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1511 dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); in xgene_phy_gen_avg_val()
1514 dev_err(ctx->dev, in xgene_phy_gen_avg_val()
1518 xgene_phy_reset_rxd(ctx, lane); in xgene_phy_gen_avg_val()
1522 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1527 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1529 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_gen_avg_val()
1534 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_gen_avg_val()
1536 serdes_rd(ctx, lane, RXTX_REG129, &val); in xgene_phy_gen_avg_val()
1541 serdes_wr(ctx, lane, RXTX_REG129, val); in xgene_phy_gen_avg_val()
1543 serdes_rd(ctx, lane, RXTX_REG130, &val); in xgene_phy_gen_avg_val()
1548 serdes_wr(ctx, lane, RXTX_REG130, val); in xgene_phy_gen_avg_val()
1551 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1554 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1556 dev_dbg(ctx->dev, "Average Value:\n"); in xgene_phy_gen_avg_val()
1557 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1562 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1567 dev_dbg(ctx->dev, "SUM 0x%x\n", in xgene_phy_gen_avg_val()
1570 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1572 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1573 dev_dbg(ctx->dev, "Enable Manual Summer calibration\n"); in xgene_phy_gen_avg_val()
1575 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1577 dev_dbg(ctx->dev, "Enable Manual Latch calibration\n"); in xgene_phy_gen_avg_val()
1578 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1580 /* Disable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1581 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_gen_avg_val()
1583 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_gen_avg_val()
1585 serdes_wr(ctx, lane, RXTX_REG28, 0x0007); in xgene_phy_gen_avg_val()
1587 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_gen_avg_val()
1598 dev_err(ctx->dev, "PHY initialize failed %d\n", rc); in xgene_phy_hw_init()
1603 if (!IS_ERR(ctx->clk)) { in xgene_phy_hw_init()
1605 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1606 clk_disable_unprepare(ctx->clk); in xgene_phy_hw_init()
1607 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1614 dev_dbg(ctx->dev, "PHY initialized\n"); in xgene_phy_hw_init()
1628 if (args->args_count <= 0) in xgene_phy_xlate()
1629 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1630 if (args->args[0] < MODE_SATA || args->args[0] >= MODE_MAX) in xgene_phy_xlate()
1631 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1633 ctx->mode = args->args[0]; in xgene_phy_xlate()
1634 return ctx->phy; in xgene_phy_xlate()
1644 if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer, in xgene_phy_get_param()
1670 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in xgene_phy_probe()
1672 return -ENOMEM; in xgene_phy_probe()
1674 ctx->dev = &pdev->dev; in xgene_phy_probe()
1677 ctx->sds_base = devm_ioremap_resource(&pdev->dev, res); in xgene_phy_probe()
1678 if (IS_ERR(ctx->sds_base)) in xgene_phy_probe()
1679 return PTR_ERR(ctx->sds_base); in xgene_phy_probe()
1682 ctx->clk = clk_get(&pdev->dev, NULL); in xgene_phy_probe()
1685 xgene_phy_get_param(pdev, "apm,tx-eye-tuning", in xgene_phy_probe()
1686 ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1); in xgene_phy_probe()
1687 xgene_phy_get_param(pdev, "apm,tx-eye-direction", in xgene_phy_probe()
1688 ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1); in xgene_phy_probe()
1689 xgene_phy_get_param(pdev, "apm,tx-boost-gain", in xgene_phy_probe()
1690 ctx->sata_param.txboostgain, 6, default_txboost_gain, 1); in xgene_phy_probe()
1691 xgene_phy_get_param(pdev, "apm,tx-amplitude", in xgene_phy_probe()
1692 ctx->sata_param.txamplitude, 6, default_txamp, 13300); in xgene_phy_probe()
1693 xgene_phy_get_param(pdev, "apm,tx-pre-cursor1", in xgene_phy_probe()
1694 ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200); in xgene_phy_probe()
1695 xgene_phy_get_param(pdev, "apm,tx-pre-cursor2", in xgene_phy_probe()
1696 ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200); in xgene_phy_probe()
1697 xgene_phy_get_param(pdev, "apm,tx-post-cursor", in xgene_phy_probe()
1698 ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200); in xgene_phy_probe()
1699 xgene_phy_get_param(pdev, "apm,tx-speed", in xgene_phy_probe()
1700 ctx->sata_param.txspeed, 3, default_spd, 1); in xgene_phy_probe()
1702 ctx->sata_param.speed[i] = 2; /* Default to Gen3 */ in xgene_phy_probe()
1706 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops); in xgene_phy_probe()
1707 if (IS_ERR(ctx->phy)) { in xgene_phy_probe()
1708 dev_dbg(&pdev->dev, "Failed to create PHY\n"); in xgene_phy_probe()
1709 return PTR_ERR(ctx->phy); in xgene_phy_probe()
1711 phy_set_drvdata(ctx->phy, ctx); in xgene_phy_probe()
1713 phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate); in xgene_phy_probe()
1718 {.compatible = "apm,xgene-phy",},
1726 .name = "xgene-phy",
1732 MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver");