Lines Matching +full:pre +full:- +full:emphasis
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
93 * if yes, then offset gives index in the reg-layout
111 /* set of registers with offsets different per-PHY */
238 "vdda-pll", "vdda-phy-dpdm",
244 * struct qusb2_phy - structure holding qusb2 phy attributes
262 * @override_preemphasis: PHY should use different pre-amphasis amplitude
263 * @preemphasis_level: Amplitude Pre-Emphasis to be updated in TUNE1 register
264 * @override_preemphasis_width: PHY should use different pre-emphasis duration
265 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
268 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
359 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_override_phy_params()
361 if (qphy->override_imp_res_offset) in qusb2_phy_override_phy_params()
362 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, in qusb2_phy_override_phy_params()
363 qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
366 if (qphy->override_hstx_trim) in qusb2_phy_override_phy_params()
367 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
368 qphy->hstx_trim_value << HSTX_TRIM_SHIFT, in qusb2_phy_override_phy_params()
371 if (qphy->override_preemphasis) in qusb2_phy_override_phy_params()
372 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
373 qphy->preemphasis_level << PREEMPHASIS_EN_SHIFT, in qusb2_phy_override_phy_params()
376 if (qphy->override_preemphasis_width) { in qusb2_phy_override_phy_params()
377 if (qphy->preemphasis_width == in qusb2_phy_override_phy_params()
379 qusb2_setbits(qphy->base, in qusb2_phy_override_phy_params()
380 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
383 qusb2_clrbits(qphy->base, in qusb2_phy_override_phy_params()
384 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
396 struct device *dev = &qphy->phy->dev; in qusb2_phy_set_tune2_param()
397 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_set_tune2_param()
401 if (!qphy->cell) in qusb2_phy_set_tune2_param()
411 val = nvmem_cell_read(qphy->cell, NULL); in qusb2_phy_set_tune2_param()
413 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
418 if (cfg->update_tune1_with_efuse) in qusb2_phy_set_tune2_param()
419 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_set_tune2_param()
423 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_set_tune2_param()
432 qphy->mode = mode; in qusb2_phy_set_mode()
440 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_suspend()
443 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_suspend()
445 if (!qphy->phy_initialized) { in qusb2_phy_runtime_suspend()
453 * current D+/D- levels are e.g. if currently D+ high, D- low in qusb2_phy_runtime_suspend()
454 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high in qusb2_phy_runtime_suspend()
457 switch (qphy->mode) { in qusb2_phy_runtime_suspend()
475 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()
478 if (cfg->has_pll_override) { in qusb2_phy_runtime_suspend()
479 qusb2_setbits(qphy->base, in qusb2_phy_runtime_suspend()
480 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_suspend()
485 /* enable phy auto-resume only if device is connected on bus */ in qusb2_phy_runtime_suspend()
486 if (qphy->mode != PHY_MODE_INVALID) { in qusb2_phy_runtime_suspend()
487 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
488 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
490 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
491 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
494 if (!qphy->has_se_clk_scheme) in qusb2_phy_runtime_suspend()
495 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
497 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_suspend()
498 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_suspend()
506 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_resume()
509 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_resume()
511 if (!qphy->phy_initialized) { in qusb2_phy_runtime_resume()
516 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_runtime_resume()
522 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
528 if (!qphy->has_se_clk_scheme) { in qusb2_phy_runtime_resume()
529 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
536 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
539 if (cfg->has_pll_override) { in qusb2_phy_runtime_resume()
540 qusb2_clrbits(qphy->base, in qusb2_phy_runtime_resume()
541 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_resume()
548 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
550 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_resume()
558 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_init()
563 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); in qusb2_phy_init()
566 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
570 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_init()
572 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); in qusb2_phy_init()
577 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_init()
579 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); in qusb2_phy_init()
584 ret = reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
586 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); in qusb2_phy_init()
593 ret = reset_control_deassert(qphy->phy_reset); in qusb2_phy_init()
595 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); in qusb2_phy_init()
600 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
601 qphy->cfg->disable_ctrl); in qusb2_phy_init()
603 if (cfg->has_pll_test) { in qusb2_phy_init()
605 val = readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
608 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, in qusb2_phy_init()
609 cfg->tbl_num); in qusb2_phy_init()
618 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
624 /* Default is single-ended clock on msm8996 */ in qusb2_phy_init()
625 qphy->has_se_clk_scheme = true; in qusb2_phy_init()
627 * read TCSR_PHY_CLK_SCHEME register to check if single-ended in qusb2_phy_init()
629 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
632 if (qphy->tcsr) { in qusb2_phy_init()
633 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
636 dev_err(&phy->dev, "failed to read clk scheme reg\n"); in qusb2_phy_init()
642 dev_vdbg(&phy->dev, "%s(): select differential clk\n", in qusb2_phy_init()
644 qphy->has_se_clk_scheme = false; in qusb2_phy_init()
646 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", in qusb2_phy_init()
651 if (!qphy->has_se_clk_scheme) { in qusb2_phy_init()
652 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
654 dev_err(&phy->dev, "failed to enable ref clk, %d\n", in qusb2_phy_init()
660 if (cfg->has_pll_test) { in qusb2_phy_init()
661 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
666 writel(val, qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
669 readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
675 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); in qusb2_phy_init()
676 if (!(val & cfg->mask_core_ready)) { in qusb2_phy_init()
677 dev_err(&phy->dev, in qusb2_phy_init()
679 ret = -EBUSY; in qusb2_phy_init()
682 qphy->phy_initialized = true; in qusb2_phy_init()
687 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
688 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
690 reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
692 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_init()
694 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_init()
696 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
706 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_exit()
707 qphy->cfg->disable_ctrl); in qusb2_phy_exit()
709 if (!qphy->has_se_clk_scheme) in qusb2_phy_exit()
710 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
712 reset_control_assert(qphy->phy_reset); in qusb2_phy_exit()
714 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_exit()
715 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_exit()
717 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_exit()
719 qphy->phy_initialized = false; in qusb2_phy_exit()
733 .compatible = "qcom,msm8996-qusb2-phy",
736 .compatible = "qcom,sdm845-qusb2-phy",
750 struct device *dev = &pdev->dev; in qusb2_phy_probe()
761 return -ENOMEM; in qusb2_phy_probe()
764 qphy->base = devm_ioremap_resource(dev, res); in qusb2_phy_probe()
765 if (IS_ERR(qphy->base)) in qusb2_phy_probe()
766 return PTR_ERR(qphy->base); in qusb2_phy_probe()
768 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); in qusb2_phy_probe()
769 if (IS_ERR(qphy->cfg_ahb_clk)) { in qusb2_phy_probe()
770 ret = PTR_ERR(qphy->cfg_ahb_clk); in qusb2_phy_probe()
771 if (ret != -EPROBE_DEFER) in qusb2_phy_probe()
776 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
777 if (IS_ERR(qphy->ref_clk)) { in qusb2_phy_probe()
778 ret = PTR_ERR(qphy->ref_clk); in qusb2_phy_probe()
779 if (ret != -EPROBE_DEFER) in qusb2_phy_probe()
784 qphy->iface_clk = devm_clk_get(dev, "iface"); in qusb2_phy_probe()
785 if (IS_ERR(qphy->iface_clk)) { in qusb2_phy_probe()
786 ret = PTR_ERR(qphy->iface_clk); in qusb2_phy_probe()
787 if (ret == -EPROBE_DEFER) in qusb2_phy_probe()
789 qphy->iface_clk = NULL; in qusb2_phy_probe()
793 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); in qusb2_phy_probe()
794 if (IS_ERR(qphy->phy_reset)) { in qusb2_phy_probe()
796 return PTR_ERR(qphy->phy_reset); in qusb2_phy_probe()
799 num = ARRAY_SIZE(qphy->vregs); in qusb2_phy_probe()
801 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; in qusb2_phy_probe()
803 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); in qusb2_phy_probe()
810 qphy->cfg = of_device_get_match_data(dev); in qusb2_phy_probe()
812 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
813 "qcom,tcsr-syscon"); in qusb2_phy_probe()
814 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
816 qphy->tcsr = NULL; in qusb2_phy_probe()
819 qphy->cell = devm_nvmem_cell_get(dev, NULL); in qusb2_phy_probe()
820 if (IS_ERR(qphy->cell)) { in qusb2_phy_probe()
821 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) in qusb2_phy_probe()
822 return -EPROBE_DEFER; in qusb2_phy_probe()
823 qphy->cell = NULL; in qusb2_phy_probe()
827 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", in qusb2_phy_probe()
829 qphy->imp_res_offset_value = (u8)value; in qusb2_phy_probe()
830 qphy->override_imp_res_offset = true; in qusb2_phy_probe()
833 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
835 qphy->hstx_trim_value = (u8)value; in qusb2_phy_probe()
836 qphy->override_hstx_trim = true; in qusb2_phy_probe()
839 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", in qusb2_phy_probe()
841 qphy->preemphasis_level = (u8)value; in qusb2_phy_probe()
842 qphy->override_preemphasis = true; in qusb2_phy_probe()
845 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", in qusb2_phy_probe()
847 qphy->preemphasis_width = (u8)value; in qusb2_phy_probe()
848 qphy->override_preemphasis_width = true; in qusb2_phy_probe()
866 qphy->phy = generic_phy; in qusb2_phy_probe()
873 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); in qusb2_phy_probe()
883 .name = "qcom-qusb2-phy",