4  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
28  * The higher 16-bit of this register is used for write protection
105 	regmap_write(rk_phy->reg_base,  in rockchip_emmc_phy_power()
106 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,  in rockchip_emmc_phy_power()
110 	regmap_write(rk_phy->reg_base,  in rockchip_emmc_phy_power()
111 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,  in rockchip_emmc_phy_power()
120 	rate = clk_get_rate(rk_phy->emmcclk);  in rockchip_emmc_phy_power()
145 			rate - ideal_rate : ideal_rate - rate;  in rockchip_emmc_phy_power()
150 		 * far off.  Also warn if we're above the 200 MHz max.  Don't  in rockchip_emmc_phy_power()
154 			dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);  in rockchip_emmc_phy_power()
163 	regmap_write(rk_phy->reg_base,  in rockchip_emmc_phy_power()
164 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,  in rockchip_emmc_phy_power()
176 	ret = regmap_read_poll_timeout(rk_phy->reg_base,  in rockchip_emmc_phy_power()
177 				       rk_phy->reg_offset + GRF_EMMCPHY_STATUS,  in rockchip_emmc_phy_power()
186 	regmap_write(rk_phy->reg_base,  in rockchip_emmc_phy_power()
187 		     rk_phy->reg_offset + GRF_EMMCPHY_CON0,  in rockchip_emmc_phy_power()
192 	regmap_write(rk_phy->reg_base,  in rockchip_emmc_phy_power()
193 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,  in rockchip_emmc_phy_power()
224 	ret = regmap_read_poll_timeout(rk_phy->reg_base,  in rockchip_emmc_phy_power()
225 				       rk_phy->reg_offset + GRF_EMMCPHY_STATUS,  in rockchip_emmc_phy_power()
244 	 * - PHY driver to probe  in rockchip_emmc_phy_init()
245 	 * - SDHCI driver to start probe  in rockchip_emmc_phy_init()
246 	 * - SDHCI driver to register it's clock  in rockchip_emmc_phy_init()
247 	 * - SDHCI driver to get the PHY  in rockchip_emmc_phy_init()
248 	 * - SDHCI driver to init the PHY  in rockchip_emmc_phy_init()
256 	rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");  in rockchip_emmc_phy_init()
257 	if (IS_ERR(rk_phy->emmcclk)) {  in rockchip_emmc_phy_init()
258 		dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);  in rockchip_emmc_phy_init()
259 		rk_phy->emmcclk = NULL;  in rockchip_emmc_phy_init()
269 	clk_put(rk_phy->emmcclk);  in rockchip_emmc_phy_exit()
284 	/* Drive impedance: 50 Ohm */  in rockchip_emmc_phy_power_on()
285 	regmap_write(rk_phy->reg_base,  in rockchip_emmc_phy_power_on()
286 		     rk_phy->reg_offset + GRF_EMMCPHY_CON6,  in rockchip_emmc_phy_power_on()
291 	/* Output tap delay: enable */  in rockchip_emmc_phy_power_on()
292 	regmap_write(rk_phy->reg_base,  in rockchip_emmc_phy_power_on()
293 		     rk_phy->reg_offset + GRF_EMMCPHY_CON0,  in rockchip_emmc_phy_power_on()
298 	/* Output tap delay */  in rockchip_emmc_phy_power_on()
299 	regmap_write(rk_phy->reg_base,  in rockchip_emmc_phy_power_on()
300 		     rk_phy->reg_offset + GRF_EMMCPHY_CON0,  in rockchip_emmc_phy_power_on()
319 	struct device *dev = &pdev->dev;  in rockchip_emmc_phy_probe()
326 	if (!dev->parent || !dev->parent->of_node)  in rockchip_emmc_phy_probe()
327 		return -ENODEV;  in rockchip_emmc_phy_probe()
329 	grf = syscon_node_to_regmap(dev->parent->of_node);  in rockchip_emmc_phy_probe()
337 		return -ENOMEM;  in rockchip_emmc_phy_probe()
339 	if (of_property_read_u32(dev->of_node, "reg", &reg_offset)) {  in rockchip_emmc_phy_probe()
341 			dev->of_node->name);  in rockchip_emmc_phy_probe()
342 		return -EINVAL;  in rockchip_emmc_phy_probe()
345 	rk_phy->reg_offset = reg_offset;  in rockchip_emmc_phy_probe()
346 	rk_phy->reg_base = grf;  in rockchip_emmc_phy_probe()
348 	generic_phy = devm_phy_create(dev, dev->of_node, &ops);  in rockchip_emmc_phy_probe()
361 	{ .compatible = "rockchip,rk3399-emmc-phy" },
370 		.name	= "rockchip-emmc-phy",
377 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");