Lines Matching +full:ext +full:- +full:gen
28 #include <dt-bindings/phy/phy.h>
174 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
176 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
241 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
370 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
381 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
382 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
394 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
399 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_pll_calibration()
402 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); in miphy28lp_pll_calibration()
403 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); in miphy28lp_pll_calibration()
404 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); in miphy28lp_pll_calibration()
405 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); in miphy28lp_pll_calibration()
406 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL); in miphy28lp_pll_calibration()
415 if (miphy_phy->type != PHY_TYPE_SATA) in miphy28lp_pll_calibration()
420 if (miphy_phy->type == PHY_TYPE_USB3) { in miphy28lp_pll_calibration()
435 void __iomem *base = miphy_phy->base; in miphy28lp_sata_config_gen()
439 struct miphy28lp_pll_gen *gen = &sata_pll_gen[i]; in miphy28lp_sata_config_gen() local
442 writeb_relaxed(gen->bank, base + MIPHY_CONF); in miphy28lp_sata_config_gen()
443 writeb_relaxed(gen->speed, base + MIPHY_SPEED); in miphy28lp_sata_config_gen()
444 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); in miphy28lp_sata_config_gen()
445 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); in miphy28lp_sata_config_gen()
448 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); in miphy28lp_sata_config_gen()
449 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); in miphy28lp_sata_config_gen()
452 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_sata_config_gen()
453 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); in miphy28lp_sata_config_gen()
454 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_sata_config_gen()
455 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); in miphy28lp_sata_config_gen()
456 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3); in miphy28lp_sata_config_gen()
462 void __iomem *base = miphy_phy->base; in miphy28lp_pcie_config_gen()
466 struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i]; in miphy28lp_pcie_config_gen() local
469 writeb_relaxed(gen->bank, base + MIPHY_CONF); in miphy28lp_pcie_config_gen()
470 writeb_relaxed(gen->speed, base + MIPHY_SPEED); in miphy28lp_pcie_config_gen()
471 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); in miphy28lp_pcie_config_gen()
472 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); in miphy28lp_pcie_config_gen()
475 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1); in miphy28lp_pcie_config_gen()
476 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); in miphy28lp_pcie_config_gen()
477 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); in miphy28lp_pcie_config_gen()
479 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN); in miphy28lp_pcie_config_gen()
482 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_pcie_config_gen()
483 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); in miphy28lp_pcie_config_gen()
484 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_pcie_config_gen()
485 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); in miphy28lp_pcie_config_gen()
496 val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); in miphy28lp_wait_compensation()
499 return -EBUSY; in miphy28lp_wait_compensation()
510 void __iomem *base = miphy_phy->base; in miphy28lp_compensation()
517 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_compensation()
520 if (miphy_phy->type == PHY_TYPE_PCIE) in miphy28lp_compensation()
527 /* TX compensation offset to re-center TX impedance */ in miphy28lp_compensation()
530 if (miphy_phy->type == PHY_TYPE_PCIE) in miphy28lp_compensation()
538 void __iomem *base = miphy_phy->base; in miphy28_usb3_miphy_reset()
566 void __iomem *base = miphy_phy->base; in miphy_sata_tune_ssc()
604 void __iomem *base = miphy_phy->base; in miphy_pcie_tune_ssc()
645 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP); in miphy_tune_tx_impedance()
650 void __iomem *base = miphy_phy->base; in miphy28lp_configure_sata()
676 if (miphy_phy->px_rx_pol_inv) { in miphy28lp_configure_sata()
678 val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL); in miphy28lp_configure_sata()
680 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); in miphy28lp_configure_sata()
683 if (miphy_phy->ssc) in miphy28lp_configure_sata()
686 if (miphy_phy->tx_impedance) in miphy28lp_configure_sata()
694 void __iomem *base = miphy_phy->base; in miphy28lp_configure_pcie()
719 if (miphy_phy->ssc) in miphy28lp_configure_pcie()
722 if (miphy_phy->tx_impedance) in miphy28lp_configure_pcie()
731 void __iomem *base = miphy_phy->base; in miphy28lp_configure_usb3()
762 /* TX compensation offset to re-center TX impedance */ in miphy28lp_configure_usb3()
820 if (miphy_phy->type == PHY_TYPE_SATA) in miphy_is_ready()
824 val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); in miphy_is_ready()
831 return -EBUSY; in miphy_is_ready()
836 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy_osc_is_ready()
840 if (!miphy_phy->osc_rdy) in miphy_osc_is_ready()
843 if (!miphy_phy->syscfg_reg[SYSCFG_STATUS]) in miphy_osc_is_ready()
844 return -EINVAL; in miphy_osc_is_ready()
847 regmap_read(miphy_dev->regmap, in miphy_osc_is_ready()
848 miphy_phy->syscfg_reg[SYSCFG_STATUS], &val); in miphy_osc_is_ready()
856 return -EBUSY; in miphy_osc_is_ready()
864 index = of_property_match_string(child, "reg-names", rname); in miphy28lp_get_resource_byname()
866 return -ENODEV; in miphy28lp_get_resource_byname()
884 return -ENOENT; in miphy28lp_get_one_addr()
895 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_setup()
897 if (!miphy_phy->syscfg_reg[SYSCFG_CTRL]) in miphy28lp_setup()
898 return -EINVAL; in miphy28lp_setup()
900 err = reset_control_assert(miphy_phy->miphy_rst); in miphy28lp_setup()
902 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); in miphy28lp_setup()
906 if (miphy_phy->osc_force_ext) in miphy28lp_setup()
909 regmap_update_bits(miphy_dev->regmap, in miphy28lp_setup()
910 miphy_phy->syscfg_reg[SYSCFG_CTRL], in miphy28lp_setup()
913 err = reset_control_deassert(miphy_phy->miphy_rst); in miphy28lp_setup()
915 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); in miphy28lp_setup()
924 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_init_sata()
927 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) || in miphy28lp_init_sata()
928 (!miphy_phy->syscfg_reg[SYSCFG_PCI]) || in miphy28lp_init_sata()
929 (!miphy_phy->base)) in miphy28lp_init_sata()
930 return -EINVAL; in miphy28lp_init_sata()
932 dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base); in miphy28lp_init_sata()
934 /* Configure the glue-logic */ in miphy28lp_init_sata()
935 sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE); in miphy28lp_init_sata()
937 regmap_update_bits(miphy_dev->regmap, in miphy28lp_init_sata()
938 miphy_phy->syscfg_reg[SYSCFG_SATA], in miphy28lp_init_sata()
941 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI], in miphy28lp_init_sata()
948 dev_err(miphy_dev->dev, "SATA phy setup failed\n"); in miphy28lp_init_sata()
960 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_init_pcie()
963 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) || in miphy28lp_init_pcie()
964 (!miphy_phy->syscfg_reg[SYSCFG_PCI]) in miphy28lp_init_pcie()
965 || (!miphy_phy->base) || (!miphy_phy->pipebase)) in miphy28lp_init_pcie()
966 return -EINVAL; in miphy28lp_init_pcie()
968 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); in miphy28lp_init_pcie()
970 /* Configure the glue-logic */ in miphy28lp_init_pcie()
971 regmap_update_bits(miphy_dev->regmap, in miphy28lp_init_pcie()
972 miphy_phy->syscfg_reg[SYSCFG_SATA], in miphy28lp_init_pcie()
975 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI], in miphy28lp_init_pcie()
982 dev_err(miphy_dev->dev, "PCIe phy setup failed\n"); in miphy28lp_init_pcie()
992 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */ in miphy28lp_init_pcie()
993 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */ in miphy28lp_init_pcie()
994 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */ in miphy28lp_init_pcie()
995 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */ in miphy28lp_init_pcie()
996 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */ in miphy28lp_init_pcie()
997 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */ in miphy28lp_init_pcie()
1005 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_init_usb3()
1008 if ((!miphy_phy->base) || (!miphy_phy->pipebase)) in miphy28lp_init_usb3()
1009 return -EINVAL; in miphy28lp_init_usb3()
1011 dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base); in miphy28lp_init_usb3()
1016 dev_err(miphy_dev->dev, "USB3 phy setup failed\n"); in miphy28lp_init_usb3()
1024 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23); in miphy28lp_init_usb3()
1025 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24); in miphy28lp_init_usb3()
1026 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26); in miphy28lp_init_usb3()
1027 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27); in miphy28lp_init_usb3()
1028 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29); in miphy28lp_init_usb3()
1029 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a); in miphy28lp_init_usb3()
1031 /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */ in miphy28lp_init_usb3()
1032 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68); in miphy28lp_init_usb3()
1033 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69); in miphy28lp_init_usb3()
1034 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a); in miphy28lp_init_usb3()
1035 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b); in miphy28lp_init_usb3()
1036 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c); in miphy28lp_init_usb3()
1037 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d); in miphy28lp_init_usb3()
1038 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e); in miphy28lp_init_usb3()
1039 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f); in miphy28lp_init_usb3()
1047 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_init()
1050 mutex_lock(&miphy_dev->miphy_mutex); in miphy28lp_init()
1052 switch (miphy_phy->type) { in miphy28lp_init()
1064 ret = -EINVAL; in miphy28lp_init()
1068 mutex_unlock(&miphy_dev->miphy_mutex); in miphy28lp_init()
1075 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_get_addr()
1076 struct device_node *phynode = miphy_phy->phy->dev.of_node; in miphy28lp_get_addr()
1079 if ((miphy_phy->type != PHY_TYPE_SATA) && in miphy28lp_get_addr()
1080 (miphy_phy->type != PHY_TYPE_PCIE) && in miphy28lp_get_addr()
1081 (miphy_phy->type != PHY_TYPE_USB3)) { in miphy28lp_get_addr()
1082 return -EINVAL; in miphy28lp_get_addr()
1085 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, in miphy28lp_get_addr()
1086 PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA], in miphy28lp_get_addr()
1087 &miphy_phy->base); in miphy28lp_get_addr()
1091 if ((miphy_phy->type == PHY_TYPE_PCIE) || in miphy28lp_get_addr()
1092 (miphy_phy->type == PHY_TYPE_USB3)) { in miphy28lp_get_addr()
1093 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew", in miphy28lp_get_addr()
1094 &miphy_phy->pipebase); in miphy28lp_get_addr()
1107 struct device_node *phynode = args->np; in miphy28lp_xlate()
1110 if (args->args_count != 1) { in miphy28lp_xlate()
1112 return ERR_PTR(-EINVAL); in miphy28lp_xlate()
1115 for (index = 0; index < miphy_dev->nphys; index++) in miphy28lp_xlate()
1116 if (phynode == miphy_dev->phys[index]->phy->dev.of_node) { in miphy28lp_xlate()
1117 miphy_phy = miphy_dev->phys[index]; in miphy28lp_xlate()
1123 return ERR_PTR(-EINVAL); in miphy28lp_xlate()
1126 miphy_phy->type = args->args[0]; in miphy28lp_xlate()
1132 return miphy_phy->phy; in miphy28lp_xlate()
1143 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; in miphy28lp_probe_resets()
1146 miphy_phy->miphy_rst = in miphy28lp_probe_resets()
1147 of_reset_control_get_shared(node, "miphy-sw-rst"); in miphy28lp_probe_resets()
1149 if (IS_ERR(miphy_phy->miphy_rst)) { in miphy28lp_probe_resets()
1150 dev_err(miphy_dev->dev, in miphy28lp_probe_resets()
1152 return PTR_ERR(miphy_phy->miphy_rst); in miphy28lp_probe_resets()
1155 err = reset_control_deassert(miphy_phy->miphy_rst); in miphy28lp_probe_resets()
1157 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); in miphy28lp_probe_resets()
1170 miphy_phy->osc_force_ext = in miphy28lp_of_probe()
1171 of_property_read_bool(np, "st,osc-force-ext"); in miphy28lp_of_probe()
1173 miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy"); in miphy28lp_of_probe()
1175 miphy_phy->px_rx_pol_inv = in miphy28lp_of_probe()
1178 miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on"); in miphy28lp_of_probe()
1180 miphy_phy->tx_impedance = in miphy28lp_of_probe()
1181 of_property_read_bool(np, "st,tx-impedance-comp"); in miphy28lp_of_probe()
1183 of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen); in miphy28lp_of_probe()
1184 if (!miphy_phy->sata_gen) in miphy28lp_of_probe()
1185 miphy_phy->sata_gen = SATA_GEN1; in miphy28lp_of_probe()
1189 miphy_phy->syscfg_reg[i] = ctrlreg; in miphy28lp_of_probe()
1197 struct device_node *child, *np = pdev->dev.of_node; in miphy28lp_probe()
1203 miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL); in miphy28lp_probe()
1205 return -ENOMEM; in miphy28lp_probe()
1207 miphy_dev->nphys = of_get_child_count(np); in miphy28lp_probe()
1208 miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys, in miphy28lp_probe()
1209 sizeof(*miphy_dev->phys), GFP_KERNEL); in miphy28lp_probe()
1210 if (!miphy_dev->phys) in miphy28lp_probe()
1211 return -ENOMEM; in miphy28lp_probe()
1213 miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in miphy28lp_probe()
1214 if (IS_ERR(miphy_dev->regmap)) { in miphy28lp_probe()
1215 dev_err(miphy_dev->dev, "No syscfg phandle specified\n"); in miphy28lp_probe()
1216 return PTR_ERR(miphy_dev->regmap); in miphy28lp_probe()
1219 miphy_dev->dev = &pdev->dev; in miphy28lp_probe()
1221 dev_set_drvdata(&pdev->dev, miphy_dev); in miphy28lp_probe()
1223 mutex_init(&miphy_dev->miphy_mutex); in miphy28lp_probe()
1228 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy), in miphy28lp_probe()
1231 ret = -ENOMEM; in miphy28lp_probe()
1235 miphy_dev->phys[port] = miphy_phy; in miphy28lp_probe()
1237 phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops); in miphy28lp_probe()
1239 dev_err(&pdev->dev, "failed to create PHY\n"); in miphy28lp_probe()
1244 miphy_dev->phys[port]->phy = phy; in miphy28lp_probe()
1245 miphy_dev->phys[port]->phydev = miphy_dev; in miphy28lp_probe()
1251 ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]); in miphy28lp_probe()
1255 phy_set_drvdata(phy, miphy_dev->phys[port]); in miphy28lp_probe()
1260 provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate); in miphy28lp_probe()
1268 {.compatible = "st,miphy28lp-phy", },
1277 .name = "miphy28lp-phy",