Lines Matching +full:0 +full:x028
33 ((x) ? (11 + ((x) - 1) * 6) : 0)
34 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
36 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
38 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
39 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
41 #define XUSB_PADCTL_USB2_PAD_MUX 0x004
43 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
44 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
46 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3
47 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
49 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
50 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
51 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
53 #define XUSB_PADCTL_SS_PORT_MAP 0x014
56 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
57 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
59 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024
68 #define XUSB_PADCTL_USB3_PAD_MUX 0x028
72 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
74 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
77 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
81 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
82 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
84 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)
86 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f
88 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf
91 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
93 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
96 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
97 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7
98 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
99 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7
100 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2
102 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
105 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f
106 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a
108 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
109 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
111 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
128 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)
129 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0
130 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf
132 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)
134 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf
135 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
136 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff
138 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
141 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f
142 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a
144 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f
145 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e
147 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
149 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
151 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff
152 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19
153 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e
155 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3
160 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3
161 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
163 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
165 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff
166 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136
169 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
171 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
175 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3
176 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2
177 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0
180 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf
182 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
184 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff
185 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a
187 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
193 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)
195 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3
196 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1
200 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
202 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
204 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
206 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
208 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
210 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
212 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
214 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3
215 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2
217 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)
218 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0
219 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff
220 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc
222 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)
223 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f
225 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)
227 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff
228 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7
230 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
231 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
259 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
261 return 0; in tegra210_pex_uphy_enable()
265 if (err < 0) in tegra210_pex_uphy_enable()
269 if (err < 0) in tegra210_pex_uphy_enable()
452 return 0; in tegra210_pex_uphy_enable()
467 if (WARN_ON(pcie->enable == 0)) in tegra210_pex_uphy_disable()
470 if (--pcie->enable > 0) in tegra210_pex_uphy_disable()
488 if (sata->enable > 0) { in tegra210_sata_uphy_enable()
490 return 0; in tegra210_sata_uphy_enable()
494 if (err < 0) in tegra210_sata_uphy_enable()
498 if (err < 0) in tegra210_sata_uphy_enable()
694 return 0; in tegra210_sata_uphy_enable()
709 if (WARN_ON(sata->enable == 0)) in tegra210_sata_uphy_disable()
712 if (--sata->enable > 0) in tegra210_sata_uphy_disable()
728 if (padctl->enable++ > 0) in tegra210_xusb_padctl_enable()
749 return 0; in tegra210_xusb_padctl_enable()
758 if (WARN_ON(padctl->enable == 0)) in tegra210_xusb_padctl_disable()
761 if (--padctl->enable > 0) in tegra210_xusb_padctl_disable()
782 return 0; in tegra210_xusb_padctl_disable()
807 return 0; in tegra210_hsic_set_idle()
844 return 0; in tegra210_usb3_set_lfps_detect()
864 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
865 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
866 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
867 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
888 if (err < 0) { in tegra210_usb2_lane_probe()
1010 if (pad->enable > 0) { in tegra210_usb2_phy_power_on()
1013 return 0; in tegra210_usb2_phy_power_on()
1048 return 0; in tegra210_usb2_phy_power_on()
1073 if (WARN_ON(pad->enable == 0)) in tegra210_usb2_phy_power_off()
1076 if (--pad->enable > 0) in tegra210_usb2_phy_power_off()
1086 return 0; in tegra210_usb2_phy_power_off()
1115 if (err < 0) { in tegra210_usb2_pad_probe()
1128 if (err < 0) in tegra210_usb2_pad_probe()
1166 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1187 if (err < 0) { in tegra210_hsic_lane_probe()
1311 return 0; in tegra210_hsic_phy_power_on()
1340 return 0; in tegra210_hsic_phy_power_off()
1369 if (err < 0) { in tegra210_hsic_pad_probe()
1382 if (err < 0) in tegra210_hsic_pad_probe()
1422 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1423 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1424 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1425 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1426 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1427 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1428 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1449 if (err < 0) { in tegra210_pcie_lane_probe()
1493 if (err < 0) in tegra210_pcie_phy_power_on()
1517 return 0; in tegra210_pcie_phy_power_off()
1546 if (err < 0) { in tegra210_pcie_pad_probe()
1566 if (err < 0) in tegra210_pcie_pad_probe()
1599 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1620 if (err < 0) { in tegra210_sata_lane_probe()
1664 if (err < 0) in tegra210_sata_phy_power_on()
1688 return 0; in tegra210_sata_phy_power_off()
1717 if (err < 0) { in tegra210_sata_pad_probe()
1730 if (err < 0) in tegra210_sata_pad_probe()
1771 return 0; in tegra210_usb2_port_enable()
1792 return 0; in tegra210_hsic_port_enable()
1837 if (err < 0) in tegra210_usb3_port_enable()
1894 return 0; in tegra210_usb3_port_enable()
1930 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7); in tegra210_usb3_port_disable()
1935 { 0, "pcie", 6 },
1937 { 2, "pcie", 0 },
1941 { 0, NULL, 0 }
1964 if (err < 0) in tegra210_xusb_read_fuse_calibration()
1967 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { in tegra210_xusb_read_fuse_calibration()
1978 if (err < 0) in tegra210_xusb_read_fuse_calibration()
1985 return 0; in tegra210_xusb_read_fuse_calibration()
2003 if (err < 0) in tegra210_xusb_padctl_probe()