Lines Matching +full:1 +full:- +full:lane
33 ((x) ? (11 + ((x) - 1) * 6) : 0)
54 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
60 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
61 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
62 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
63 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
65 (1 << (1 + (x) * 3))
66 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
69 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
70 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
75 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
78 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)
79 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27)
80 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26)
89 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
90 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)
91 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11)
103 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26)
112 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18)
113 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17)
114 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16)
115 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15)
116 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14)
117 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13)
118 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9)
119 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8)
120 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7)
121 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6)
122 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5)
123 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
124 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3)
125 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
126 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1)
139 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19)
156 #define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15)
157 #define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)
158 #define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3)
159 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1
161 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
167 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
168 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1)
169 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
172 #define XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN (1 << 19)
173 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15)
178 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8)
188 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31)
189 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15)
190 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13)
191 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12)
251 /* must be called under padctl->lock */
254 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
259 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
260 pcie->enable++; in tegra210_pex_uphy_enable()
264 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
268 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
347 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
366 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
385 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
405 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
424 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
450 pcie->enable++; in tegra210_pex_uphy_enable()
455 reset_control_assert(pcie->rst); in tegra210_pex_uphy_enable()
457 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_enable()
463 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_disable()
465 mutex_lock(&padctl->lock); in tegra210_pex_uphy_disable()
467 if (WARN_ON(pcie->enable == 0)) in tegra210_pex_uphy_disable()
470 if (--pcie->enable > 0) in tegra210_pex_uphy_disable()
473 reset_control_assert(pcie->rst); in tegra210_pex_uphy_disable()
474 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_disable()
477 mutex_unlock(&padctl->lock); in tegra210_pex_uphy_disable()
480 /* must be called under padctl->lock */
483 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_enable()
488 if (sata->enable > 0) { in tegra210_sata_uphy_enable()
489 sata->enable++; in tegra210_sata_uphy_enable()
493 err = clk_prepare_enable(sata->pll); in tegra210_sata_uphy_enable()
497 err = reset_control_deassert(sata->rst); in tegra210_sata_uphy_enable()
589 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
608 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
627 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
647 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
666 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
692 sata->enable++; in tegra210_sata_uphy_enable()
697 reset_control_assert(sata->rst); in tegra210_sata_uphy_enable()
699 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_enable()
705 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_disable()
707 mutex_lock(&padctl->lock); in tegra210_sata_uphy_disable()
709 if (WARN_ON(sata->enable == 0)) in tegra210_sata_uphy_disable()
712 if (--sata->enable > 0) in tegra210_sata_uphy_disable()
715 reset_control_assert(sata->rst); in tegra210_sata_uphy_disable()
716 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_disable()
719 mutex_unlock(&padctl->lock); in tegra210_sata_uphy_disable()
726 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_enable()
728 if (padctl->enable++ > 0) in tegra210_xusb_padctl_enable()
748 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_enable()
756 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_disable()
758 if (WARN_ON(padctl->enable == 0)) in tegra210_xusb_padctl_disable()
761 if (--padctl->enable > 0) in tegra210_xusb_padctl_disable()
781 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_disable()
814 struct tegra_xusb_lane *lane; in tegra210_usb3_set_lfps_detect() local
819 return -ENODEV; in tegra210_usb3_set_lfps_detect()
821 lane = port->lane; in tegra210_usb3_set_lfps_detect()
823 if (lane->pad == padctl->pcie) in tegra210_usb3_set_lfps_detect()
824 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); in tegra210_usb3_set_lfps_detect()
864 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
865 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
866 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
867 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
879 return ERR_PTR(-ENOMEM); in tegra210_usb2_lane_probe()
881 INIT_LIST_HEAD(&usb2->base.list); in tegra210_usb2_lane_probe()
882 usb2->base.soc = &pad->soc->lanes[index]; in tegra210_usb2_lane_probe()
883 usb2->base.index = index; in tegra210_usb2_lane_probe()
884 usb2->base.pad = pad; in tegra210_usb2_lane_probe()
885 usb2->base.np = np; in tegra210_usb2_lane_probe()
887 err = tegra_xusb_lane_parse_dt(&usb2->base, np); in tegra210_usb2_lane_probe()
893 return &usb2->base; in tegra210_usb2_lane_probe()
896 static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra210_usb2_lane_remove() argument
898 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra210_usb2_lane_remove()
910 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_usb2_phy_init() local
911 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_init()
926 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_usb2_phy_exit() local
928 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_usb2_phy_exit()
933 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_usb2_phy_power_on() local
934 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra210_usb2_phy_power_on()
935 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_on()
936 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_on()
939 unsigned int index = lane->index; in tegra210_usb2_phy_power_on()
945 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index); in tegra210_usb2_phy_power_on()
946 return -ENODEV; in tegra210_usb2_phy_power_on()
977 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
978 usb2->hs_curr_level_offset) << in tegra210_usb2_phy_power_on()
990 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
992 (priv->fuse.rpd_ctrl << in tegra210_usb2_phy_power_on()
1004 err = regulator_enable(port->supply); in tegra210_usb2_phy_power_on()
1008 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_on()
1010 if (pad->enable > 0) { in tegra210_usb2_phy_power_on()
1011 pad->enable++; in tegra210_usb2_phy_power_on()
1012 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1016 err = clk_prepare_enable(pad->clk); in tegra210_usb2_phy_power_on()
1035 udelay(1); in tegra210_usb2_phy_power_on()
1043 clk_disable_unprepare(pad->clk); in tegra210_usb2_phy_power_on()
1045 pad->enable++; in tegra210_usb2_phy_power_on()
1046 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1051 regulator_disable(port->supply); in tegra210_usb2_phy_power_on()
1052 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1058 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_usb2_phy_power_off() local
1059 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_off()
1060 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_off()
1064 port = tegra_xusb_find_usb2_port(padctl, lane->index); in tegra210_usb2_phy_power_off()
1066 dev_err(&phy->dev, "no port found for USB2 lane %u\n", in tegra210_usb2_phy_power_off()
1067 lane->index); in tegra210_usb2_phy_power_off()
1068 return -ENODEV; in tegra210_usb2_phy_power_off()
1071 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_off()
1073 if (WARN_ON(pad->enable == 0)) in tegra210_usb2_phy_power_off()
1076 if (--pad->enable > 0) in tegra210_usb2_phy_power_off()
1084 regulator_disable(port->supply); in tegra210_usb2_phy_power_off()
1085 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_off()
1108 return ERR_PTR(-ENOMEM); in tegra210_usb2_pad_probe()
1110 pad = &usb2->base; in tegra210_usb2_pad_probe()
1111 pad->ops = &tegra210_usb2_lane_ops; in tegra210_usb2_pad_probe()
1112 pad->soc = soc; in tegra210_usb2_pad_probe()
1120 usb2->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_usb2_pad_probe()
1121 if (IS_ERR(usb2->clk)) { in tegra210_usb2_pad_probe()
1122 err = PTR_ERR(usb2->clk); in tegra210_usb2_pad_probe()
1123 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_usb2_pad_probe()
1131 dev_set_drvdata(&pad->dev, pad); in tegra210_usb2_pad_probe()
1136 device_unregister(&pad->dev); in tegra210_usb2_pad_probe()
1166 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1178 return ERR_PTR(-ENOMEM); in tegra210_hsic_lane_probe()
1180 INIT_LIST_HEAD(&hsic->base.list); in tegra210_hsic_lane_probe()
1181 hsic->base.soc = &pad->soc->lanes[index]; in tegra210_hsic_lane_probe()
1182 hsic->base.index = index; in tegra210_hsic_lane_probe()
1183 hsic->base.pad = pad; in tegra210_hsic_lane_probe()
1184 hsic->base.np = np; in tegra210_hsic_lane_probe()
1186 err = tegra_xusb_lane_parse_dt(&hsic->base, np); in tegra210_hsic_lane_probe()
1192 return &hsic->base; in tegra210_hsic_lane_probe()
1195 static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane) in tegra210_hsic_lane_remove() argument
1197 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); in tegra210_hsic_lane_remove()
1209 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_hsic_phy_init() local
1210 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_init()
1225 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_hsic_phy_exit() local
1227 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_hsic_phy_exit()
1232 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_hsic_phy_power_on() local
1233 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); in tegra210_hsic_phy_power_on()
1234 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_on()
1235 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_on()
1237 unsigned int index = lane->index; in tegra210_hsic_phy_power_on()
1243 err = regulator_enable(pad->supply); in tegra210_hsic_phy_power_on()
1247 padctl_writel(padctl, hsic->strobe_trim, in tegra210_hsic_phy_power_on()
1253 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
1262 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
1264 (hsic->rx_data_trim << in tegra210_hsic_phy_power_on()
1286 err = clk_prepare_enable(pad->clk); in tegra210_hsic_phy_power_on()
1301 udelay(1); in tegra210_hsic_phy_power_on()
1309 clk_disable_unprepare(pad->clk); in tegra210_hsic_phy_power_on()
1314 regulator_disable(pad->supply); in tegra210_hsic_phy_power_on()
1320 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_hsic_phy_power_off() local
1321 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_off()
1322 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_off()
1323 unsigned int index = lane->index; in tegra210_hsic_phy_power_off()
1338 regulator_disable(pad->supply); in tegra210_hsic_phy_power_off()
1362 return ERR_PTR(-ENOMEM); in tegra210_hsic_pad_probe()
1364 pad = &hsic->base; in tegra210_hsic_pad_probe()
1365 pad->ops = &tegra210_hsic_lane_ops; in tegra210_hsic_pad_probe()
1366 pad->soc = soc; in tegra210_hsic_pad_probe()
1374 hsic->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_hsic_pad_probe()
1375 if (IS_ERR(hsic->clk)) { in tegra210_hsic_pad_probe()
1376 err = PTR_ERR(hsic->clk); in tegra210_hsic_pad_probe()
1377 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_hsic_pad_probe()
1385 dev_set_drvdata(&pad->dev, pad); in tegra210_hsic_pad_probe()
1390 device_unregister(&pad->dev); in tegra210_hsic_pad_probe()
1415 "pcie-x1",
1416 "usb3-ss",
1418 "pcie-x4",
1422 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1423 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1424 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1425 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1426 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1427 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1428 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1440 return ERR_PTR(-ENOMEM); in tegra210_pcie_lane_probe()
1442 INIT_LIST_HEAD(&pcie->base.list); in tegra210_pcie_lane_probe()
1443 pcie->base.soc = &pad->soc->lanes[index]; in tegra210_pcie_lane_probe()
1444 pcie->base.index = index; in tegra210_pcie_lane_probe()
1445 pcie->base.pad = pad; in tegra210_pcie_lane_probe()
1446 pcie->base.np = np; in tegra210_pcie_lane_probe()
1448 err = tegra_xusb_lane_parse_dt(&pcie->base, np); in tegra210_pcie_lane_probe()
1454 return &pcie->base; in tegra210_pcie_lane_probe()
1457 static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane) in tegra210_pcie_lane_remove() argument
1459 struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane); in tegra210_pcie_lane_remove()
1471 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_pcie_phy_init() local
1473 return tegra210_xusb_padctl_enable(lane->pad->padctl); in tegra210_pcie_phy_init()
1478 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_pcie_phy_exit() local
1480 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_pcie_phy_exit()
1485 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_pcie_phy_power_on() local
1486 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_on()
1490 mutex_lock(&padctl->lock); in tegra210_pcie_phy_power_on()
1497 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_on()
1501 mutex_unlock(&padctl->lock); in tegra210_pcie_phy_power_on()
1507 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_pcie_phy_power_off() local
1508 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_off()
1512 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_off()
1539 return ERR_PTR(-ENOMEM); in tegra210_pcie_pad_probe()
1541 pad = &pcie->base; in tegra210_pcie_pad_probe()
1542 pad->ops = &tegra210_pcie_lane_ops; in tegra210_pcie_pad_probe()
1543 pad->soc = soc; in tegra210_pcie_pad_probe()
1551 pcie->pll = devm_clk_get(&pad->dev, "pll"); in tegra210_pcie_pad_probe()
1552 if (IS_ERR(pcie->pll)) { in tegra210_pcie_pad_probe()
1553 err = PTR_ERR(pcie->pll); in tegra210_pcie_pad_probe()
1554 dev_err(&pad->dev, "failed to get PLL: %d\n", err); in tegra210_pcie_pad_probe()
1558 pcie->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_pcie_pad_probe()
1559 if (IS_ERR(pcie->rst)) { in tegra210_pcie_pad_probe()
1560 err = PTR_ERR(pcie->rst); in tegra210_pcie_pad_probe()
1561 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err); in tegra210_pcie_pad_probe()
1569 dev_set_drvdata(&pad->dev, pad); in tegra210_pcie_pad_probe()
1574 device_unregister(&pad->dev); in tegra210_pcie_pad_probe()
1599 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1611 return ERR_PTR(-ENOMEM); in tegra210_sata_lane_probe()
1613 INIT_LIST_HEAD(&sata->base.list); in tegra210_sata_lane_probe()
1614 sata->base.soc = &pad->soc->lanes[index]; in tegra210_sata_lane_probe()
1615 sata->base.index = index; in tegra210_sata_lane_probe()
1616 sata->base.pad = pad; in tegra210_sata_lane_probe()
1617 sata->base.np = np; in tegra210_sata_lane_probe()
1619 err = tegra_xusb_lane_parse_dt(&sata->base, np); in tegra210_sata_lane_probe()
1625 return &sata->base; in tegra210_sata_lane_probe()
1628 static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane) in tegra210_sata_lane_remove() argument
1630 struct tegra_xusb_sata_lane *sata = to_sata_lane(lane); in tegra210_sata_lane_remove()
1642 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_sata_phy_init() local
1644 return tegra210_xusb_padctl_enable(lane->pad->padctl); in tegra210_sata_phy_init()
1649 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_sata_phy_exit() local
1651 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_sata_phy_exit()
1656 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_sata_phy_power_on() local
1657 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_on()
1661 mutex_lock(&padctl->lock); in tegra210_sata_phy_power_on()
1668 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_on()
1672 mutex_unlock(&padctl->lock); in tegra210_sata_phy_power_on()
1678 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_sata_phy_power_off() local
1679 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_off()
1683 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_off()
1686 tegra210_sata_uphy_disable(lane->pad->padctl); in tegra210_sata_phy_power_off()
1710 return ERR_PTR(-ENOMEM); in tegra210_sata_pad_probe()
1712 pad = &sata->base; in tegra210_sata_pad_probe()
1713 pad->ops = &tegra210_sata_lane_ops; in tegra210_sata_pad_probe()
1714 pad->soc = soc; in tegra210_sata_pad_probe()
1722 sata->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_sata_pad_probe()
1723 if (IS_ERR(sata->rst)) { in tegra210_sata_pad_probe()
1724 err = PTR_ERR(sata->rst); in tegra210_sata_pad_probe()
1725 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err); in tegra210_sata_pad_probe()
1733 dev_set_drvdata(&pad->dev, pad); in tegra210_sata_pad_probe()
1738 device_unregister(&pad->dev); in tegra210_sata_pad_probe()
1781 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); in tegra210_usb2_port_map()
1802 return tegra_xusb_find_lane(port->padctl, "hsic", port->index); in tegra210_hsic_port_map()
1814 struct tegra_xusb_padctl *padctl = port->padctl; in tegra210_usb3_port_enable()
1815 struct tegra_xusb_lane *lane = usb3->base.lane; in tegra210_usb3_port_enable() local
1816 unsigned int index = port->index; in tegra210_usb3_port_enable()
1822 if (!usb3->internal) in tegra210_usb3_port_enable()
1828 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_port_enable()
1832 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks in tegra210_usb3_port_enable()
1836 err = regulator_enable(usb3->supply); in tegra210_usb3_port_enable()
1867 if (lane->pad == padctl->sata) in tegra210_usb3_port_enable()
1873 dev_err(&port->dev, "%s: failed to enable UPHY: %d\n", in tegra210_usb3_port_enable()
1900 struct tegra_xusb_padctl *padctl = port->padctl; in tegra210_usb3_port_disable()
1901 struct tegra_xusb_lane *lane = port->lane; in tegra210_usb3_port_disable() local
1902 unsigned int index = port->index; in tegra210_usb3_port_disable()
1921 if (lane->pad == padctl->sata) in tegra210_usb3_port_disable()
1926 regulator_disable(usb3->supply); in tegra210_usb3_port_disable()
1936 { 1, "pcie", 5 },
1947 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss"); in tegra210_usb3_port_map()
1967 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { in tegra210_xusb_read_fuse_calibration()
1968 fuse->hs_curr_level[i] = in tegra210_xusb_read_fuse_calibration()
1973 fuse->hs_term_range_adj = in tegra210_xusb_read_fuse_calibration()
1981 fuse->rpd_ctrl = in tegra210_xusb_read_fuse_calibration()
1997 return ERR_PTR(-ENOMEM); in tegra210_xusb_padctl_probe()
1999 padctl->base.dev = dev; in tegra210_xusb_padctl_probe()
2000 padctl->base.soc = soc; in tegra210_xusb_padctl_probe()
2002 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse); in tegra210_xusb_padctl_probe()
2006 return &padctl->base; in tegra210_xusb_padctl_probe()
2030 .count = 1,