1166 	TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1173 	struct tegra_xusb_hsic_lane *hsic;  in tegra210_hsic_lane_probe()  local
1176 	hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);  in tegra210_hsic_lane_probe()
1177 	if (!hsic)  in tegra210_hsic_lane_probe()
1180 	INIT_LIST_HEAD(&hsic->base.list);  in tegra210_hsic_lane_probe()
1181 	hsic->base.soc = &pad->soc->lanes[index];  in tegra210_hsic_lane_probe()
1182 	hsic->base.index = index;  in tegra210_hsic_lane_probe()
1183 	hsic->base.pad = pad;  in tegra210_hsic_lane_probe()
1184 	hsic->base.np = np;  in tegra210_hsic_lane_probe()
1186 	err = tegra_xusb_lane_parse_dt(&hsic->base, np);  in tegra210_hsic_lane_probe()
1188 		kfree(hsic);  in tegra210_hsic_lane_probe()
1192 	return &hsic->base;  in tegra210_hsic_lane_probe()
1197 	struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);  in tegra210_hsic_lane_remove()  local
1199 	kfree(hsic);  in tegra210_hsic_lane_remove()
1233 	struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);  in tegra210_hsic_phy_power_on()  local
1247 	padctl_writel(padctl, hsic->strobe_trim,  in tegra210_hsic_phy_power_on()
1253 	value |= (hsic->tx_rtune_p <<  in tegra210_hsic_phy_power_on()
1262 	value |= (hsic->rx_strobe_trim <<  in tegra210_hsic_phy_power_on()
1264 		 (hsic->rx_data_trim <<  in tegra210_hsic_phy_power_on()
1356 	struct tegra_xusb_hsic_pad *hsic;  in tegra210_hsic_pad_probe()  local
1360 	hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);  in tegra210_hsic_pad_probe()
1361 	if (!hsic)  in tegra210_hsic_pad_probe()
1364 	pad = &hsic->base;  in tegra210_hsic_pad_probe()
1370 		kfree(hsic);  in tegra210_hsic_pad_probe()
1374 	hsic->clk = devm_clk_get(&pad->dev, "trk");  in tegra210_hsic_pad_probe()
1375 	if (IS_ERR(hsic->clk)) {  in tegra210_hsic_pad_probe()
1376 		err = PTR_ERR(hsic->clk);  in tegra210_hsic_pad_probe()
1397 	struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad);  in tegra210_hsic_pad_remove()  local
1399 	kfree(hsic);  in tegra210_hsic_pad_remove()
1408 	.name = "hsic",
1802 	return tegra_xusb_find_lane(port->padctl, "hsic", port->index);  in tegra210_hsic_port_map()
2028 		.hsic = {