Lines Matching full:value
256 u32 value; in tegra210_pex_uphy_enable() local
272 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
273 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
275 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
277 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
279 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
280 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
282 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
284 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
287 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_pex_uphy_enable()
288 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
290 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
291 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_pex_uphy_enable()
292 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
294 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
295 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_pex_uphy_enable()
296 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
298 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
299 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << in tegra210_pex_uphy_enable()
303 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << in tegra210_pex_uphy_enable()
306 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
308 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
309 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_pex_uphy_enable()
313 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << in tegra210_pex_uphy_enable()
315 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
317 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
318 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; in tegra210_pex_uphy_enable()
319 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
321 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
322 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << in tegra210_pex_uphy_enable()
324 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
328 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
329 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; in tegra210_pex_uphy_enable()
330 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
332 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
333 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_pex_uphy_enable()
334 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
339 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
340 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) in tegra210_pex_uphy_enable()
351 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
352 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_pex_uphy_enable()
353 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
358 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
359 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) in tegra210_pex_uphy_enable()
370 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
371 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; in tegra210_pex_uphy_enable()
372 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
377 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
378 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) in tegra210_pex_uphy_enable()
389 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
390 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | in tegra210_pex_uphy_enable()
392 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
397 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
398 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) in tegra210_pex_uphy_enable()
409 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
410 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; in tegra210_pex_uphy_enable()
411 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
416 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
417 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) in tegra210_pex_uphy_enable()
428 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
429 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; in tegra210_pex_uphy_enable()
430 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
434 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
435 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_pex_uphy_enable()
436 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
438 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
439 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_pex_uphy_enable()
440 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
442 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
443 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_pex_uphy_enable()
444 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
485 u32 value; in tegra210_sata_uphy_enable() local
501 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
502 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_sata_uphy_enable()
504 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_sata_uphy_enable()
506 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
508 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
509 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_sata_uphy_enable()
511 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_sata_uphy_enable()
513 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
515 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
516 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_sata_uphy_enable()
517 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
519 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
520 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_sata_uphy_enable()
521 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
523 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
524 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_sata_uphy_enable()
525 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
527 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
528 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << in tegra210_sata_uphy_enable()
532 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN; in tegra210_sata_uphy_enable()
535 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << in tegra210_sata_uphy_enable()
538 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL << in tegra210_sata_uphy_enable()
541 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN; in tegra210_sata_uphy_enable()
542 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
544 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
545 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_sata_uphy_enable()
551 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << in tegra210_sata_uphy_enable()
554 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL << in tegra210_sata_uphy_enable()
557 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
559 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
560 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; in tegra210_sata_uphy_enable()
561 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
563 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
564 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << in tegra210_sata_uphy_enable()
566 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
570 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
571 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; in tegra210_sata_uphy_enable()
572 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
574 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
575 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_sata_uphy_enable()
576 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
581 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
582 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) in tegra210_sata_uphy_enable()
593 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
594 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_sata_uphy_enable()
595 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
600 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
601 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) in tegra210_sata_uphy_enable()
612 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
613 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; in tegra210_sata_uphy_enable()
614 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
619 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
620 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) in tegra210_sata_uphy_enable()
631 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
632 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | in tegra210_sata_uphy_enable()
634 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
639 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
640 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) in tegra210_sata_uphy_enable()
651 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
652 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; in tegra210_sata_uphy_enable()
653 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
658 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
659 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) in tegra210_sata_uphy_enable()
670 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
671 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; in tegra210_sata_uphy_enable()
672 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
676 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
677 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_sata_uphy_enable()
678 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
680 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
681 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_sata_uphy_enable()
682 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
684 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
685 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_sata_uphy_enable()
686 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
724 u32 value; in tegra210_xusb_padctl_enable() local
731 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
732 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in tegra210_xusb_padctl_enable()
733 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
737 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
738 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra210_xusb_padctl_enable()
739 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
743 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
744 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in tegra210_xusb_padctl_enable()
745 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
754 u32 value; in tegra210_xusb_padctl_disable() local
764 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
765 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in tegra210_xusb_padctl_disable()
766 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
770 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
771 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra210_xusb_padctl_disable()
772 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
776 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
777 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in tegra210_xusb_padctl_disable()
778 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
788 u32 value; in tegra210_hsic_set_idle() local
790 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
792 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | in tegra210_hsic_set_idle()
797 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_set_idle()
801 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_set_idle()
805 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
815 u32 value, offset; in tegra210_usb3_set_lfps_detect() local
828 value = padctl_readl(padctl, offset); in tegra210_usb3_set_lfps_detect()
830 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK << in tegra210_usb3_set_lfps_detect()
836 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL << in tegra210_usb3_set_lfps_detect()
842 padctl_writel(padctl, value, offset); in tegra210_usb3_set_lfps_detect()
912 u32 value; in tegra210_usb2_phy_init() local
914 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
915 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK << in tegra210_usb2_phy_init()
917 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB << in tegra210_usb2_phy_init()
919 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
940 u32 value; in tegra210_usb2_phy_power_on() local
951 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
952 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK << in tegra210_usb2_phy_power_on()
956 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL << in tegra210_usb2_phy_power_on()
960 value |= in tegra210_usb2_phy_power_on()
964 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
966 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
967 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index); in tegra210_usb2_phy_power_on()
968 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index); in tegra210_usb2_phy_power_on()
969 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
971 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
972 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK << in tegra210_usb2_phy_power_on()
977 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
980 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
982 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
983 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK << in tegra210_usb2_phy_power_on()
990 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
994 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
996 value = padctl_readl(padctl, in tegra210_usb2_phy_power_on()
998 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK << in tegra210_usb2_phy_power_on()
1000 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; in tegra210_usb2_phy_power_on()
1001 padctl_writel(padctl, value, in tegra210_usb2_phy_power_on()
1020 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1021 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK << in tegra210_usb2_phy_power_on()
1025 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL << in tegra210_usb2_phy_power_on()
1029 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1031 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1032 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; in tegra210_usb2_phy_power_on()
1033 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1037 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1038 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK; in tegra210_usb2_phy_power_on()
1039 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1062 u32 value; in tegra210_usb2_phy_power_off() local
1079 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1080 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; in tegra210_usb2_phy_power_off()
1081 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1211 u32 value; in tegra210_hsic_phy_init() local
1213 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1214 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK << in tegra210_hsic_phy_init()
1216 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB << in tegra210_hsic_phy_init()
1218 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1238 u32 value; in tegra210_hsic_phy_power_on() local
1250 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1251 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK << in tegra210_hsic_phy_power_on()
1253 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
1255 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1257 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1258 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK << in tegra210_hsic_phy_power_on()
1262 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
1266 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1268 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1269 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | in tegra210_hsic_phy_power_on()
1281 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_phy_power_on()
1284 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1290 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1291 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK << in tegra210_hsic_phy_power_on()
1295 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL << in tegra210_hsic_phy_power_on()
1299 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1303 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1304 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK; in tegra210_hsic_phy_power_on()
1305 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1324 u32 value; in tegra210_hsic_phy_power_off() local
1326 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_off()
1327 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 | in tegra210_hsic_phy_power_off()
1336 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_off()
1487 u32 value; in tegra210_pcie_phy_power_on() local
1496 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1497 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_on()
1498 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1509 u32 value; in tegra210_pcie_phy_power_off() local
1511 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1512 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_off()
1513 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1658 u32 value; in tegra210_sata_phy_power_on() local
1667 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1668 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_on()
1669 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1680 u32 value; in tegra210_sata_phy_power_off() local
1682 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1683 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_off()
1684 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1817 u32 value; in tegra210_usb3_port_enable() local
1820 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
1823 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); in tegra210_usb3_port_enable()
1825 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); in tegra210_usb3_port_enable()
1827 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); in tegra210_usb3_port_enable()
1828 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_port_enable()
1829 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
1840 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
1841 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK << in tegra210_usb3_port_enable()
1843 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL << in tegra210_usb3_port_enable()
1845 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
1847 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
1848 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK << in tegra210_usb3_port_enable()
1850 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL << in tegra210_usb3_port_enable()
1852 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
1857 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
1858 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK << in tegra210_usb3_port_enable()
1860 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL << in tegra210_usb3_port_enable()
1862 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
1878 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1879 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); in tegra210_usb3_port_enable()
1880 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1884 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1885 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra210_usb3_port_enable()
1886 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1890 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1891 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); in tegra210_usb3_port_enable()
1892 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1903 u32 value; in tegra210_usb3_port_disable() local
1905 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1906 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra210_usb3_port_disable()
1907 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1911 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1912 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); in tegra210_usb3_port_disable()
1913 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1917 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1918 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); in tegra210_usb3_port_disable()
1919 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1928 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
1929 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); in tegra210_usb3_port_disable()
1930 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7); in tegra210_usb3_port_disable()
1931 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
1960 u32 value; in tegra210_xusb_read_fuse_calibration() local
1963 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); in tegra210_xusb_read_fuse_calibration()
1969 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) & in tegra210_xusb_read_fuse_calibration()
1974 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) & in tegra210_xusb_read_fuse_calibration()
1977 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); in tegra210_xusb_read_fuse_calibration()
1982 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) & in tegra210_xusb_read_fuse_calibration()