Lines Matching +full:xusb +full:- +full:padctl
30 #include "xusb.h"
33 ((x) ? (11 + ((x) - 1) * 6) : 0)
246 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra210_xusb_padctl() argument
248 return container_of(padctl, struct tegra210_xusb_padctl, base); in to_tegra210_xusb_padctl()
251 /* must be called under padctl->lock */
252 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl) in tegra210_pex_uphy_enable() argument
254 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
259 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
260 pcie->enable++; in tegra210_pex_uphy_enable()
264 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
268 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
272 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
277 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
279 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
284 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
288 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
290 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
292 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
294 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
296 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
298 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
306 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
308 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
315 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
317 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
319 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
321 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
324 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
328 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
330 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
332 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
334 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
339 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
347 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
351 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
353 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
358 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
366 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
370 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
372 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
377 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
385 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
389 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
392 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
397 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
405 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
409 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
411 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
416 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
424 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
428 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
430 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
434 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
436 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
438 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
440 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
442 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
444 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
450 pcie->enable++; in tegra210_pex_uphy_enable()
455 reset_control_assert(pcie->rst); in tegra210_pex_uphy_enable()
457 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_enable()
461 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl) in tegra210_pex_uphy_disable() argument
463 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_disable()
465 mutex_lock(&padctl->lock); in tegra210_pex_uphy_disable()
467 if (WARN_ON(pcie->enable == 0)) in tegra210_pex_uphy_disable()
470 if (--pcie->enable > 0) in tegra210_pex_uphy_disable()
473 reset_control_assert(pcie->rst); in tegra210_pex_uphy_disable()
474 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_disable()
477 mutex_unlock(&padctl->lock); in tegra210_pex_uphy_disable()
480 /* must be called under padctl->lock */
481 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb) in tegra210_sata_uphy_enable() argument
483 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_enable()
488 if (sata->enable > 0) { in tegra210_sata_uphy_enable()
489 sata->enable++; in tegra210_sata_uphy_enable()
493 err = clk_prepare_enable(sata->pll); in tegra210_sata_uphy_enable()
497 err = reset_control_deassert(sata->rst); in tegra210_sata_uphy_enable()
501 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
506 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
508 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
513 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
515 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
517 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
519 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
521 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
523 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
525 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
527 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
542 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
544 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
557 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
559 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
561 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
563 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
566 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
570 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
572 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
574 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
576 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
581 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
589 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
593 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
595 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
600 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
608 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
612 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
614 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
619 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
627 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
631 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
634 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
639 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
647 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
651 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
653 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
658 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
666 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
670 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
672 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
676 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
678 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
680 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
682 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
684 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
686 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
692 sata->enable++; in tegra210_sata_uphy_enable()
697 reset_control_assert(sata->rst); in tegra210_sata_uphy_enable()
699 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_enable()
703 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl) in tegra210_sata_uphy_disable() argument
705 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_disable()
707 mutex_lock(&padctl->lock); in tegra210_sata_uphy_disable()
709 if (WARN_ON(sata->enable == 0)) in tegra210_sata_uphy_disable()
712 if (--sata->enable > 0) in tegra210_sata_uphy_disable()
715 reset_control_assert(sata->rst); in tegra210_sata_uphy_disable()
716 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_disable()
719 mutex_unlock(&padctl->lock); in tegra210_sata_uphy_disable()
722 static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_enable() argument
726 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_enable()
728 if (padctl->enable++ > 0) in tegra210_xusb_padctl_enable()
731 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
733 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
737 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
739 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
743 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
745 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
748 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_enable()
752 static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_disable() argument
756 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_disable()
758 if (WARN_ON(padctl->enable == 0)) in tegra210_xusb_padctl_disable()
761 if (--padctl->enable > 0) in tegra210_xusb_padctl_disable()
764 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
766 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
770 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
772 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
776 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
778 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
781 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_disable()
785 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl, in tegra210_hsic_set_idle() argument
790 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
805 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
810 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl, in tegra210_usb3_set_lfps_detect() argument
817 port = tegra_xusb_find_port(padctl, "usb3", index); in tegra210_usb3_set_lfps_detect()
819 return -ENODEV; in tegra210_usb3_set_lfps_detect()
821 lane = port->lane; in tegra210_usb3_set_lfps_detect()
823 if (lane->pad == padctl->pcie) in tegra210_usb3_set_lfps_detect()
824 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); in tegra210_usb3_set_lfps_detect()
828 value = padctl_readl(padctl, offset); in tegra210_usb3_set_lfps_detect()
842 padctl_writel(padctl, value, offset); in tegra210_usb3_set_lfps_detect()
859 "xusb",
864 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
865 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
866 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
867 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
879 return ERR_PTR(-ENOMEM); in tegra210_usb2_lane_probe()
881 INIT_LIST_HEAD(&usb2->base.list); in tegra210_usb2_lane_probe()
882 usb2->base.soc = &pad->soc->lanes[index]; in tegra210_usb2_lane_probe()
883 usb2->base.index = index; in tegra210_usb2_lane_probe()
884 usb2->base.pad = pad; in tegra210_usb2_lane_probe()
885 usb2->base.np = np; in tegra210_usb2_lane_probe()
887 err = tegra_xusb_lane_parse_dt(&usb2->base, np); in tegra210_usb2_lane_probe()
893 return &usb2->base; in tegra210_usb2_lane_probe()
911 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_init() local
914 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
919 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
921 return tegra210_xusb_padctl_enable(padctl); in tegra210_usb2_phy_init()
928 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_usb2_phy_exit()
935 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_on()
936 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_on() local
939 unsigned int index = lane->index; in tegra210_usb2_phy_power_on()
943 port = tegra_xusb_find_usb2_port(padctl, index); in tegra210_usb2_phy_power_on()
945 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index); in tegra210_usb2_phy_power_on()
946 return -ENODEV; in tegra210_usb2_phy_power_on()
949 priv = to_tegra210_xusb_padctl(padctl); in tegra210_usb2_phy_power_on()
951 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
964 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
966 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
969 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
971 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
977 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
978 usb2->hs_curr_level_offset) << in tegra210_usb2_phy_power_on()
980 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
982 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
990 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
992 (priv->fuse.rpd_ctrl << in tegra210_usb2_phy_power_on()
994 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
996 value = padctl_readl(padctl, in tegra210_usb2_phy_power_on()
1001 padctl_writel(padctl, value, in tegra210_usb2_phy_power_on()
1004 err = regulator_enable(port->supply); in tegra210_usb2_phy_power_on()
1008 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_on()
1010 if (pad->enable > 0) { in tegra210_usb2_phy_power_on()
1011 pad->enable++; in tegra210_usb2_phy_power_on()
1012 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1016 err = clk_prepare_enable(pad->clk); in tegra210_usb2_phy_power_on()
1020 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1029 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1031 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1033 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1037 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1039 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1043 clk_disable_unprepare(pad->clk); in tegra210_usb2_phy_power_on()
1045 pad->enable++; in tegra210_usb2_phy_power_on()
1046 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1051 regulator_disable(port->supply); in tegra210_usb2_phy_power_on()
1052 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1059 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_off()
1060 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_off() local
1064 port = tegra_xusb_find_usb2_port(padctl, lane->index); in tegra210_usb2_phy_power_off()
1066 dev_err(&phy->dev, "no port found for USB2 lane %u\n", in tegra210_usb2_phy_power_off()
1067 lane->index); in tegra210_usb2_phy_power_off()
1068 return -ENODEV; in tegra210_usb2_phy_power_off()
1071 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_off()
1073 if (WARN_ON(pad->enable == 0)) in tegra210_usb2_phy_power_off()
1076 if (--pad->enable > 0) in tegra210_usb2_phy_power_off()
1079 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1081 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1084 regulator_disable(port->supply); in tegra210_usb2_phy_power_off()
1085 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_off()
1098 tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_usb2_pad_probe() argument
1108 return ERR_PTR(-ENOMEM); in tegra210_usb2_pad_probe()
1110 pad = &usb2->base; in tegra210_usb2_pad_probe()
1111 pad->ops = &tegra210_usb2_lane_ops; in tegra210_usb2_pad_probe()
1112 pad->soc = soc; in tegra210_usb2_pad_probe()
1114 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_usb2_pad_probe()
1120 usb2->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_usb2_pad_probe()
1121 if (IS_ERR(usb2->clk)) { in tegra210_usb2_pad_probe()
1122 err = PTR_ERR(usb2->clk); in tegra210_usb2_pad_probe()
1123 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_usb2_pad_probe()
1131 dev_set_drvdata(&pad->dev, pad); in tegra210_usb2_pad_probe()
1136 device_unregister(&pad->dev); in tegra210_usb2_pad_probe()
1162 "xusb",
1166 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1178 return ERR_PTR(-ENOMEM); in tegra210_hsic_lane_probe()
1180 INIT_LIST_HEAD(&hsic->base.list); in tegra210_hsic_lane_probe()
1181 hsic->base.soc = &pad->soc->lanes[index]; in tegra210_hsic_lane_probe()
1182 hsic->base.index = index; in tegra210_hsic_lane_probe()
1183 hsic->base.pad = pad; in tegra210_hsic_lane_probe()
1184 hsic->base.np = np; in tegra210_hsic_lane_probe()
1186 err = tegra_xusb_lane_parse_dt(&hsic->base, np); in tegra210_hsic_lane_probe()
1192 return &hsic->base; in tegra210_hsic_lane_probe()
1210 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_init() local
1213 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1218 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1220 return tegra210_xusb_padctl_enable(padctl); in tegra210_hsic_phy_init()
1227 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_hsic_phy_exit()
1234 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_on()
1235 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_on() local
1237 unsigned int index = lane->index; in tegra210_hsic_phy_power_on()
1241 priv = to_tegra210_xusb_padctl(padctl); in tegra210_hsic_phy_power_on()
1243 err = regulator_enable(pad->supply); in tegra210_hsic_phy_power_on()
1247 padctl_writel(padctl, hsic->strobe_trim, in tegra210_hsic_phy_power_on()
1250 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1253 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
1255 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1257 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1262 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
1264 (hsic->rx_data_trim << in tegra210_hsic_phy_power_on()
1266 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1268 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1284 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1286 err = clk_prepare_enable(pad->clk); in tegra210_hsic_phy_power_on()
1290 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1299 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1303 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1305 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1309 clk_disable_unprepare(pad->clk); in tegra210_hsic_phy_power_on()
1314 regulator_disable(pad->supply); in tegra210_hsic_phy_power_on()
1321 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_off()
1322 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_off() local
1323 unsigned int index = lane->index; in tegra210_hsic_phy_power_off()
1326 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_off()
1336 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_off()
1338 regulator_disable(pad->supply); in tegra210_hsic_phy_power_off()
1352 tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_hsic_pad_probe() argument
1362 return ERR_PTR(-ENOMEM); in tegra210_hsic_pad_probe()
1364 pad = &hsic->base; in tegra210_hsic_pad_probe()
1365 pad->ops = &tegra210_hsic_lane_ops; in tegra210_hsic_pad_probe()
1366 pad->soc = soc; in tegra210_hsic_pad_probe()
1368 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_hsic_pad_probe()
1374 hsic->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_hsic_pad_probe()
1375 if (IS_ERR(hsic->clk)) { in tegra210_hsic_pad_probe()
1376 err = PTR_ERR(hsic->clk); in tegra210_hsic_pad_probe()
1377 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_hsic_pad_probe()
1385 dev_set_drvdata(&pad->dev, pad); in tegra210_hsic_pad_probe()
1390 device_unregister(&pad->dev); in tegra210_hsic_pad_probe()
1415 "pcie-x1",
1416 "usb3-ss",
1418 "pcie-x4",
1422 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1423 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1424 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1425 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1426 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1427 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1428 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1440 return ERR_PTR(-ENOMEM); in tegra210_pcie_lane_probe()
1442 INIT_LIST_HEAD(&pcie->base.list); in tegra210_pcie_lane_probe()
1443 pcie->base.soc = &pad->soc->lanes[index]; in tegra210_pcie_lane_probe()
1444 pcie->base.index = index; in tegra210_pcie_lane_probe()
1445 pcie->base.pad = pad; in tegra210_pcie_lane_probe()
1446 pcie->base.np = np; in tegra210_pcie_lane_probe()
1448 err = tegra_xusb_lane_parse_dt(&pcie->base, np); in tegra210_pcie_lane_probe()
1454 return &pcie->base; in tegra210_pcie_lane_probe()
1473 return tegra210_xusb_padctl_enable(lane->pad->padctl); in tegra210_pcie_phy_init()
1480 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_pcie_phy_exit()
1486 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_on() local
1490 mutex_lock(&padctl->lock); in tegra210_pcie_phy_power_on()
1492 err = tegra210_pex_uphy_enable(padctl); in tegra210_pcie_phy_power_on()
1496 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1497 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_on()
1498 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1501 mutex_unlock(&padctl->lock); in tegra210_pcie_phy_power_on()
1508 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_off() local
1511 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1512 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_off()
1513 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1515 tegra210_pex_uphy_disable(padctl); in tegra210_pcie_phy_power_off()
1529 tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_pcie_pad_probe() argument
1539 return ERR_PTR(-ENOMEM); in tegra210_pcie_pad_probe()
1541 pad = &pcie->base; in tegra210_pcie_pad_probe()
1542 pad->ops = &tegra210_pcie_lane_ops; in tegra210_pcie_pad_probe()
1543 pad->soc = soc; in tegra210_pcie_pad_probe()
1545 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_pcie_pad_probe()
1551 pcie->pll = devm_clk_get(&pad->dev, "pll"); in tegra210_pcie_pad_probe()
1552 if (IS_ERR(pcie->pll)) { in tegra210_pcie_pad_probe()
1553 err = PTR_ERR(pcie->pll); in tegra210_pcie_pad_probe()
1554 dev_err(&pad->dev, "failed to get PLL: %d\n", err); in tegra210_pcie_pad_probe()
1558 pcie->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_pcie_pad_probe()
1559 if (IS_ERR(pcie->rst)) { in tegra210_pcie_pad_probe()
1560 err = PTR_ERR(pcie->rst); in tegra210_pcie_pad_probe()
1561 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err); in tegra210_pcie_pad_probe()
1569 dev_set_drvdata(&pad->dev, pad); in tegra210_pcie_pad_probe()
1574 device_unregister(&pad->dev); in tegra210_pcie_pad_probe()
1599 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1611 return ERR_PTR(-ENOMEM); in tegra210_sata_lane_probe()
1613 INIT_LIST_HEAD(&sata->base.list); in tegra210_sata_lane_probe()
1614 sata->base.soc = &pad->soc->lanes[index]; in tegra210_sata_lane_probe()
1615 sata->base.index = index; in tegra210_sata_lane_probe()
1616 sata->base.pad = pad; in tegra210_sata_lane_probe()
1617 sata->base.np = np; in tegra210_sata_lane_probe()
1619 err = tegra_xusb_lane_parse_dt(&sata->base, np); in tegra210_sata_lane_probe()
1625 return &sata->base; in tegra210_sata_lane_probe()
1644 return tegra210_xusb_padctl_enable(lane->pad->padctl); in tegra210_sata_phy_init()
1651 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_sata_phy_exit()
1657 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_on() local
1661 mutex_lock(&padctl->lock); in tegra210_sata_phy_power_on()
1663 err = tegra210_sata_uphy_enable(padctl, false); in tegra210_sata_phy_power_on()
1667 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1668 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_on()
1669 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1672 mutex_unlock(&padctl->lock); in tegra210_sata_phy_power_on()
1679 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_off() local
1682 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1683 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_off()
1684 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1686 tegra210_sata_uphy_disable(lane->pad->padctl); in tegra210_sata_phy_power_off()
1700 tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_sata_pad_probe() argument
1710 return ERR_PTR(-ENOMEM); in tegra210_sata_pad_probe()
1712 pad = &sata->base; in tegra210_sata_pad_probe()
1713 pad->ops = &tegra210_sata_lane_ops; in tegra210_sata_pad_probe()
1714 pad->soc = soc; in tegra210_sata_pad_probe()
1716 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_sata_pad_probe()
1722 sata->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_sata_pad_probe()
1723 if (IS_ERR(sata->rst)) { in tegra210_sata_pad_probe()
1724 err = PTR_ERR(sata->rst); in tegra210_sata_pad_probe()
1725 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err); in tegra210_sata_pad_probe()
1733 dev_set_drvdata(&pad->dev, pad); in tegra210_sata_pad_probe()
1738 device_unregister(&pad->dev); in tegra210_sata_pad_probe()
1781 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); in tegra210_usb2_port_map()
1802 return tegra_xusb_find_lane(port->padctl, "hsic", port->index); in tegra210_hsic_port_map()
1814 struct tegra_xusb_padctl *padctl = port->padctl; in tegra210_usb3_port_enable() local
1815 struct tegra_xusb_lane *lane = usb3->base.lane; in tegra210_usb3_port_enable()
1816 unsigned int index = port->index; in tegra210_usb3_port_enable()
1820 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
1822 if (!usb3->internal) in tegra210_usb3_port_enable()
1828 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_port_enable()
1829 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
1832 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks in tegra210_usb3_port_enable()
1836 err = regulator_enable(usb3->supply); in tegra210_usb3_port_enable()
1840 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
1845 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
1847 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
1852 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
1854 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL, in tegra210_usb3_port_enable()
1857 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
1862 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
1864 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL, in tegra210_usb3_port_enable()
1867 if (lane->pad == padctl->sata) in tegra210_usb3_port_enable()
1868 err = tegra210_sata_uphy_enable(padctl, true); in tegra210_usb3_port_enable()
1870 err = tegra210_pex_uphy_enable(padctl); in tegra210_usb3_port_enable()
1873 dev_err(&port->dev, "%s: failed to enable UPHY: %d\n", in tegra210_usb3_port_enable()
1878 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1880 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1884 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1886 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1890 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1892 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1900 struct tegra_xusb_padctl *padctl = port->padctl; in tegra210_usb3_port_disable() local
1901 struct tegra_xusb_lane *lane = port->lane; in tegra210_usb3_port_disable()
1902 unsigned int index = port->index; in tegra210_usb3_port_disable()
1905 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1907 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1911 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1913 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1917 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1919 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1921 if (lane->pad == padctl->sata) in tegra210_usb3_port_disable()
1922 tegra210_sata_uphy_disable(padctl); in tegra210_usb3_port_disable()
1924 tegra210_pex_uphy_disable(padctl); in tegra210_usb3_port_disable()
1926 regulator_disable(usb3->supply); in tegra210_usb3_port_disable()
1928 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
1931 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
1947 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss"); in tegra210_usb3_port_map()
1967 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { in tegra210_xusb_read_fuse_calibration()
1968 fuse->hs_curr_level[i] = in tegra210_xusb_read_fuse_calibration()
1973 fuse->hs_term_range_adj = in tegra210_xusb_read_fuse_calibration()
1981 fuse->rpd_ctrl = in tegra210_xusb_read_fuse_calibration()
1992 struct tegra210_xusb_padctl *padctl; in tegra210_xusb_padctl_probe() local
1995 padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL); in tegra210_xusb_padctl_probe()
1996 if (!padctl) in tegra210_xusb_padctl_probe()
1997 return ERR_PTR(-ENOMEM); in tegra210_xusb_padctl_probe()
1999 padctl->base.dev = dev; in tegra210_xusb_padctl_probe()
2000 padctl->base.soc = soc; in tegra210_xusb_padctl_probe()
2002 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse); in tegra210_xusb_padctl_probe()
2006 return &padctl->base; in tegra210_xusb_padctl_probe()
2009 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_remove() argument
2042 MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");