Lines Matching +full:irqs +full:- +full:map +full:- +full:range
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
100 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
114 * struct pcs_data - wrapper for data needed by pinctrl framework
128 * struct pcs_soc_data - SoC specific settings
133 * @rearm: optional SoC specific wake-up rearm function
144 * struct pcs_device - pinctrl device instance
166 * @irqs: list of interrupt registers
199 struct list_head irqs; member
207 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
208 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
209 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
281 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_dbg_show()
283 val = pcs->read(pcs->base + offset); in pcs_pin_dbg_show()
284 pa = pcs->res->start + offset; in pcs_pin_dbg_show()
290 struct pinctrl_map *map, unsigned num_maps) in pcs_dt_free_map() argument
295 devm_kfree(pcs->dev, map); in pcs_dt_free_map()
300 struct pinctrl_map **map, unsigned *num_maps);
321 setting = pdesc->mux_setting; in pcs_get_function()
323 return -ENOTSUPP; in pcs_get_function()
324 fselector = setting->func; in pcs_get_function()
326 *func = function->data; in pcs_get_function()
328 dev_err(pcs->dev, "%s could not find function%i\n", in pcs_get_function()
330 return -ENOTSUPP; in pcs_get_function()
345 if (!pcs->fmask) in pcs_set_mux()
348 func = function->data; in pcs_set_mux()
350 return -EINVAL; in pcs_set_mux()
352 dev_dbg(pcs->dev, "enabling %s function%i\n", in pcs_set_mux()
353 func->name, fselector); in pcs_set_mux()
355 for (i = 0; i < func->nvals; i++) { in pcs_set_mux()
360 vals = &func->vals[i]; in pcs_set_mux()
361 raw_spin_lock_irqsave(&pcs->lock, flags); in pcs_set_mux()
362 val = pcs->read(vals->reg); in pcs_set_mux()
364 if (pcs->bits_per_mux) in pcs_set_mux()
365 mask = vals->mask; in pcs_set_mux()
367 mask = pcs->fmask; in pcs_set_mux()
370 val |= (vals->val & mask); in pcs_set_mux()
371 pcs->write(val, vals->reg); in pcs_set_mux()
372 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pcs_set_mux()
379 struct pinctrl_gpio_range *range, unsigned pin) in pcs_request_gpio() argument
388 if (!pcs->fmask) in pcs_request_gpio()
389 return -ENOTSUPP; in pcs_request_gpio()
391 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { in pcs_request_gpio()
393 if (pin >= frange->offset + frange->npins in pcs_request_gpio()
394 || pin < frange->offset) in pcs_request_gpio()
396 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_request_gpio()
398 if (pcs->bits_per_mux) { in pcs_request_gpio()
401 byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_request_gpio()
403 pin_shift = pin % (pcs->width / pcs->bits_per_pin) * in pcs_request_gpio()
404 pcs->bits_per_pin; in pcs_request_gpio()
406 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
407 data &= ~(pcs->fmask << pin_shift); in pcs_request_gpio()
408 data |= frange->gpiofunc << pin_shift; in pcs_request_gpio()
409 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
411 data = pcs->read(pcs->base + pin * mux_bytes); in pcs_request_gpio()
412 data &= ~pcs->fmask; in pcs_request_gpio()
413 data |= frange->gpiofunc; in pcs_request_gpio()
414 pcs->write(data, pcs->base + pin * mux_bytes); in pcs_request_gpio()
471 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_get()
478 return -ENOTSUPP; in pcs_pinconf_get()
480 } else if (param != func->conf[i].param) { in pcs_pinconf_get()
484 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_get()
485 data = pcs->read(pcs->base + offset) & func->conf[i].mask; in pcs_pinconf_get()
486 switch (func->conf[i].param) { in pcs_pinconf_get()
491 if ((data != func->conf[i].enable) || in pcs_pinconf_get()
492 (data == func->conf[i].disable)) in pcs_pinconf_get()
493 return -ENOTSUPP; in pcs_pinconf_get()
498 for (j = 0; j < func->nconfs; j++) { in pcs_pinconf_get()
499 switch (func->conf[j].param) { in pcs_pinconf_get()
501 if (data != func->conf[j].enable) in pcs_pinconf_get()
502 return -ENOTSUPP; in pcs_pinconf_get()
519 return -ENOTSUPP; in pcs_pinconf_get()
537 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_set()
539 != func->conf[i].param) in pcs_pinconf_set()
542 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_set()
543 data = pcs->read(pcs->base + offset); in pcs_pinconf_set()
545 switch (func->conf[i].param) { in pcs_pinconf_set()
551 shift = ffs(func->conf[i].mask) - 1; in pcs_pinconf_set()
552 data &= ~func->conf[i].mask; in pcs_pinconf_set()
553 data |= (arg << shift) & func->conf[i].mask; in pcs_pinconf_set()
565 data &= ~func->conf[i].mask; in pcs_pinconf_set()
567 data |= func->conf[i].enable; in pcs_pinconf_set()
569 data |= func->conf[i].disable; in pcs_pinconf_set()
572 return -ENOTSUPP; in pcs_pinconf_set()
574 pcs->write(data, pcs->base + offset); in pcs_pinconf_set()
578 if (i >= func->nconfs) in pcs_pinconf_set()
579 return -ENOTSUPP; in pcs_pinconf_set()
597 return -ENOTSUPP; in pcs_pinconf_group_get()
600 return -ENOTSUPP; in pcs_pinconf_group_get()
619 return -ENOTSUPP; in pcs_pinconf_group_set()
653 * pcs_add_pin() - add a pin to the static per controller pin array
660 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_add_pin()
664 i = pcs->pins.cur; in pcs_add_pin()
665 if (i >= pcs->desc.npins) { in pcs_add_pin()
666 dev_err(pcs->dev, "too many pins, max %i\n", in pcs_add_pin()
667 pcs->desc.npins); in pcs_add_pin()
668 return -ENOMEM; in pcs_add_pin()
671 if (pcs_soc->irq_enable_mask) { in pcs_add_pin()
674 val = pcs->read(pcs->base + offset); in pcs_add_pin()
675 if (val & pcs_soc->irq_enable_mask) { in pcs_add_pin()
676 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", in pcs_add_pin()
677 (unsigned long)pcs->res->start + offset, val); in pcs_add_pin()
678 val &= ~pcs_soc->irq_enable_mask; in pcs_add_pin()
679 pcs->write(val, pcs->base + offset); in pcs_add_pin()
683 pin = &pcs->pins.pa[i]; in pcs_add_pin()
684 pin->number = i; in pcs_add_pin()
685 pcs->pins.cur++; in pcs_add_pin()
691 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
704 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_allocate_pin_table()
706 if (pcs->bits_per_mux) { in pcs_allocate_pin_table()
707 pcs->bits_per_pin = fls(pcs->fmask); in pcs_allocate_pin_table()
708 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_allocate_pin_table()
709 num_pins_in_register = pcs->width / pcs->bits_per_pin; in pcs_allocate_pin_table()
711 nr_pins = pcs->size / mux_bytes; in pcs_allocate_pin_table()
714 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); in pcs_allocate_pin_table()
715 pcs->pins.pa = devm_kcalloc(pcs->dev, in pcs_allocate_pin_table()
716 nr_pins, sizeof(*pcs->pins.pa), in pcs_allocate_pin_table()
718 if (!pcs->pins.pa) in pcs_allocate_pin_table()
719 return -ENOMEM; in pcs_allocate_pin_table()
721 pcs->desc.pins = pcs->pins.pa; in pcs_allocate_pin_table()
722 pcs->desc.npins = nr_pins; in pcs_allocate_pin_table()
724 for (i = 0; i < pcs->desc.npins; i++) { in pcs_allocate_pin_table()
730 if (pcs->bits_per_mux) { in pcs_allocate_pin_table()
731 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; in pcs_allocate_pin_table()
739 dev_err(pcs->dev, "error adding pins: %i\n", res); in pcs_allocate_pin_table()
748 * pcs_add_function() - adds a new function to the function list
770 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); in pcs_add_function()
772 return -ENOMEM; in pcs_add_function()
774 function->vals = vals; in pcs_add_function()
775 function->nvals = nvals; in pcs_add_function()
777 selector = pinmux_generic_add_function(pcs->pctl, name, in pcs_add_function()
781 devm_kfree(pcs->dev, function); in pcs_add_function()
791 * pcs_get_pin_by_offset() - get a pin index based on the register offset
801 if (offset >= pcs->size) { in pcs_get_pin_by_offset()
802 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", in pcs_get_pin_by_offset()
803 offset, pcs->size); in pcs_get_pin_by_offset()
804 return -EINVAL; in pcs_get_pin_by_offset()
807 if (pcs->bits_per_mux) in pcs_get_pin_by_offset()
808 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_get_pin_by_offset()
810 index = offset / (pcs->width / BITS_PER_BYTE); in pcs_get_pin_by_offset()
822 int ret = -EINVAL; in pcs_config_match()
835 (*conf)->param = param; in add_config()
836 (*conf)->val = value; in add_config()
837 (*conf)->enable = enable; in add_config()
838 (*conf)->disable = disable; in add_config()
839 (*conf)->mask = mask; in add_config()
863 shift = ffs(value[1]) - 1; in pcs_add_conf2()
882 dev_err(pcs->dev, "mask field of the property can't be 0\n"); in pcs_add_conf4()
890 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); in pcs_add_conf4()
897 struct pinctrl_map **map) in pcs_parse_pinconf() argument
900 struct pinctrl_map *m = *map; in pcs_parse_pinconf()
905 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, in pcs_parse_pinconf()
906 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, in pcs_parse_pinconf()
907 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, in pcs_parse_pinconf()
908 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, in pcs_parse_pinconf()
911 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, in pcs_parse_pinconf()
912 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, in pcs_parse_pinconf()
913 { "pinctrl-single,input-schmitt-enable", in pcs_parse_pinconf()
919 return -ENOTSUPP; in pcs_parse_pinconf()
931 return -ENOTSUPP; in pcs_parse_pinconf()
933 func->conf = devm_kcalloc(pcs->dev, in pcs_parse_pinconf()
936 if (!func->conf) in pcs_parse_pinconf()
937 return -ENOMEM; in pcs_parse_pinconf()
938 func->nconfs = nconfs; in pcs_parse_pinconf()
939 conf = &(func->conf[0]); in pcs_parse_pinconf()
941 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), in pcs_parse_pinconf()
944 return -ENOMEM; in pcs_parse_pinconf()
953 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; in pcs_parse_pinconf()
954 m->data.configs.group_or_pin = np->name; in pcs_parse_pinconf()
955 m->data.configs.configs = settings; in pcs_parse_pinconf()
956 m->data.configs.num_configs = nconfs; in pcs_parse_pinconf()
961 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
965 * @map: map entry
966 * @num_maps: number of map
982 struct pinctrl_map **map, in pcs_parse_one_pinctrl_entry() argument
986 const char *name = "pinctrl-single,pins"; in pcs_parse_one_pinctrl_entry()
988 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; in pcs_parse_one_pinctrl_entry()
993 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_one_pinctrl_entry()
994 return -EINVAL; in pcs_parse_one_pinctrl_entry()
997 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
999 return -ENOMEM; in pcs_parse_one_pinctrl_entry()
1001 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1015 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_one_pinctrl_entry()
1022 vals[found].reg = pcs->base + offset; in pcs_parse_one_pinctrl_entry()
1025 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n", in pcs_parse_one_pinctrl_entry()
1026 pinctrl_spec.np->name, offset, pinctrl_spec.args[1]); in pcs_parse_one_pinctrl_entry()
1030 dev_err(pcs->dev, in pcs_parse_one_pinctrl_entry()
1032 np->name, offset); in pcs_parse_one_pinctrl_entry()
1038 pgnames[0] = np->name; in pcs_parse_one_pinctrl_entry()
1039 mutex_lock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1040 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_one_pinctrl_entry()
1047 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_one_pinctrl_entry()
1053 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_one_pinctrl_entry()
1054 (*map)->data.mux.group = np->name; in pcs_parse_one_pinctrl_entry()
1055 (*map)->data.mux.function = np->name; in pcs_parse_one_pinctrl_entry()
1058 res = pcs_parse_pinconf(pcs, np, function, map); in pcs_parse_one_pinctrl_entry()
1061 else if (res == -ENOTSUPP) in pcs_parse_one_pinctrl_entry()
1068 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1073 pinctrl_generic_remove_group(pcs->pctl, gsel); in pcs_parse_one_pinctrl_entry()
1076 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_one_pinctrl_entry()
1078 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1079 devm_kfree(pcs->dev, pins); in pcs_parse_one_pinctrl_entry()
1082 devm_kfree(pcs->dev, vals); in pcs_parse_one_pinctrl_entry()
1089 struct pinctrl_map **map, in pcs_parse_bits_in_pinctrl_entry() argument
1093 const char *name = "pinctrl-single,bits"; in pcs_parse_bits_in_pinctrl_entry()
1095 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; in pcs_parse_bits_in_pinctrl_entry()
1101 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_bits_in_pinctrl_entry()
1102 return -EINVAL; in pcs_parse_bits_in_pinctrl_entry()
1105 npins_in_row = pcs->width / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1107 vals = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1111 return -ENOMEM; in pcs_parse_bits_in_pinctrl_entry()
1113 pins = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1131 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_bits_in_pinctrl_entry()
1141 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n", in pcs_parse_bits_in_pinctrl_entry()
1142 pinctrl_spec.np->name, offset, val, mask); in pcs_parse_bits_in_pinctrl_entry()
1147 pin_num_from_lsb = bit_pos / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1148 mask_pos = ((pcs->fmask) << bit_pos); in pcs_parse_bits_in_pinctrl_entry()
1153 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1155 np->name, offset); in pcs_parse_bits_in_pinctrl_entry()
1162 dev_warn(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1164 submask, np->name, offset); in pcs_parse_bits_in_pinctrl_entry()
1169 vals[found].reg = pcs->base + offset; in pcs_parse_bits_in_pinctrl_entry()
1174 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1176 np->name, offset); in pcs_parse_bits_in_pinctrl_entry()
1183 pgnames[0] = np->name; in pcs_parse_bits_in_pinctrl_entry()
1184 mutex_lock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1185 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_bits_in_pinctrl_entry()
1192 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_bits_in_pinctrl_entry()
1198 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_bits_in_pinctrl_entry()
1199 (*map)->data.mux.group = np->name; in pcs_parse_bits_in_pinctrl_entry()
1200 (*map)->data.mux.function = np->name; in pcs_parse_bits_in_pinctrl_entry()
1203 dev_err(pcs->dev, "pinconf not supported\n"); in pcs_parse_bits_in_pinctrl_entry()
1208 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1213 pinctrl_generic_remove_group(pcs->pctl, gsel); in pcs_parse_bits_in_pinctrl_entry()
1216 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_bits_in_pinctrl_entry()
1218 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1219 devm_kfree(pcs->dev, pins); in pcs_parse_bits_in_pinctrl_entry()
1222 devm_kfree(pcs->dev, vals); in pcs_parse_bits_in_pinctrl_entry()
1227 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1230 * @map: array of map entries
1235 struct pinctrl_map **map, unsigned *num_maps) in pcs_dt_node_to_map() argument
1244 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); in pcs_dt_node_to_map()
1245 if (!*map) in pcs_dt_node_to_map()
1246 return -ENOMEM; in pcs_dt_node_to_map()
1250 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); in pcs_dt_node_to_map()
1252 ret = -ENOMEM; in pcs_dt_node_to_map()
1256 if (pcs->bits_per_mux) { in pcs_dt_node_to_map()
1257 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, in pcs_dt_node_to_map()
1260 dev_err(pcs->dev, "no pins entries for %s\n", in pcs_dt_node_to_map()
1261 np_config->name); in pcs_dt_node_to_map()
1265 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, in pcs_dt_node_to_map()
1268 dev_err(pcs->dev, "no pins entries for %s\n", in pcs_dt_node_to_map()
1269 np_config->name); in pcs_dt_node_to_map()
1277 devm_kfree(pcs->dev, pgnames); in pcs_dt_node_to_map()
1279 devm_kfree(pcs->dev, *map); in pcs_dt_node_to_map()
1285 * pcs_irq_free() - free interrupt
1290 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_free()
1292 if (pcs_soc->irq < 0) in pcs_irq_free()
1295 if (pcs->domain) in pcs_irq_free()
1296 irq_domain_remove(pcs->domain); in pcs_irq_free()
1299 free_irq(pcs_soc->irq, pcs_soc); in pcs_irq_free()
1301 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_free()
1305 * pcs_free_resources() - free memory used by this driver
1311 pinctrl_unregister(pcs->pctl); in pcs_free_resources()
1314 if (pcs->missing_nr_pinctrl_cells) in pcs_free_resources()
1315 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); in pcs_free_resources()
1321 const char *propname = "pinctrl-single,gpio-range"; in pcs_add_gpio_func()
1322 const char *cellname = "#pinctrl-single,gpio-range-cells"; in pcs_add_gpio_func()
1324 struct pcs_gpiofunc_range *range; in pcs_add_gpio_func() local
1335 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); in pcs_add_gpio_func()
1336 if (!range) { in pcs_add_gpio_func()
1337 ret = -ENOMEM; in pcs_add_gpio_func()
1340 range->offset = gpiospec.args[0]; in pcs_add_gpio_func()
1341 range->npins = gpiospec.args[1]; in pcs_add_gpio_func()
1342 range->gpiofunc = gpiospec.args[2]; in pcs_add_gpio_func()
1343 mutex_lock(&pcs->mutex); in pcs_add_gpio_func()
1344 list_add_tail(&range->node, &pcs->gpiofuncs); in pcs_add_gpio_func()
1345 mutex_unlock(&pcs->mutex); in pcs_add_gpio_func()
1363 * pcs_irq_set() - enables or disables an interrupt
1366 * register that is typically used for wake-up events.
1376 list_for_each(pos, &pcs->irqs) { in pcs_irq_set()
1381 if (irq != pcswi->irq) in pcs_irq_set()
1384 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1385 raw_spin_lock(&pcs->lock); in pcs_irq_set()
1386 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1391 pcs->write(mask, pcswi->reg); in pcs_irq_set()
1394 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1395 raw_spin_unlock(&pcs->lock); in pcs_irq_set()
1398 if (pcs_soc->rearm) in pcs_irq_set()
1399 pcs_soc->rearm(); in pcs_irq_set()
1403 * pcs_irq_mask() - mask pinctrl interrupt
1410 pcs_irq_set(pcs_soc, d->irq, false); in pcs_irq_mask()
1414 * pcs_irq_unmask() - unmask pinctrl interrupt
1421 pcs_irq_set(pcs_soc, d->irq, true); in pcs_irq_unmask()
1425 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1427 * @state: wake-up state
1430 * For runtime PM, the wake-up events should be enabled by default.
1443 * pcs_irq_handle() - common interrupt handler
1447 * mux register. This interrupt is typically used for wake-up events.
1457 list_for_each(pos, &pcs->irqs) { in pcs_irq_handle()
1462 raw_spin_lock(&pcs->lock); in pcs_irq_handle()
1463 mask = pcs->read(pcswi->reg); in pcs_irq_handle()
1464 raw_spin_unlock(&pcs->lock); in pcs_irq_handle()
1465 if (mask & pcs_soc->irq_status_mask) { in pcs_irq_handle()
1466 generic_handle_irq(irq_find_mapping(pcs->domain, in pcs_irq_handle()
1467 pcswi->hwirq)); in pcs_irq_handle()
1476 * pcs_irq_handler() - handler for the shared interrupt case
1481 * pinctrl-single share a single interrupt like on omaps.
1491 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1496 * pinctrl-single instance.
1513 struct pcs_soc_data *pcs_soc = d->host_data; in pcs_irqdomain_map()
1518 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); in pcs_irqdomain_map()
1520 return -ENOMEM; in pcs_irqdomain_map()
1522 pcswi->reg = pcs->base + hwirq; in pcs_irqdomain_map()
1523 pcswi->hwirq = hwirq; in pcs_irqdomain_map()
1524 pcswi->irq = irq; in pcs_irqdomain_map()
1526 mutex_lock(&pcs->mutex); in pcs_irqdomain_map()
1527 list_add_tail(&pcswi->node, &pcs->irqs); in pcs_irqdomain_map()
1528 mutex_unlock(&pcs->mutex); in pcs_irqdomain_map()
1531 irq_set_chip_and_handler(irq, &pcs->chip, in pcs_irqdomain_map()
1540 .map = pcs_irqdomain_map,
1545 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1552 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_init_chained_handler()
1556 if (!pcs_soc->irq_enable_mask || in pcs_irq_init_chained_handler()
1557 !pcs_soc->irq_status_mask) { in pcs_irq_init_chained_handler()
1558 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1559 return -EINVAL; in pcs_irq_init_chained_handler()
1562 INIT_LIST_HEAD(&pcs->irqs); in pcs_irq_init_chained_handler()
1563 pcs->chip.name = name; in pcs_irq_init_chained_handler()
1564 pcs->chip.irq_ack = pcs_irq_mask; in pcs_irq_init_chained_handler()
1565 pcs->chip.irq_mask = pcs_irq_mask; in pcs_irq_init_chained_handler()
1566 pcs->chip.irq_unmask = pcs_irq_unmask; in pcs_irq_init_chained_handler()
1567 pcs->chip.irq_set_wake = pcs_irq_set_wake; in pcs_irq_init_chained_handler()
1572 res = request_irq(pcs_soc->irq, pcs_irq_handler, in pcs_irq_init_chained_handler()
1577 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1581 irq_set_chained_handler_and_data(pcs_soc->irq, in pcs_irq_init_chained_handler()
1592 num_irqs = pcs->size; in pcs_irq_init_chained_handler()
1594 pcs->domain = irq_domain_add_simple(np, num_irqs, 0, in pcs_irq_init_chained_handler()
1597 if (!pcs->domain) { in pcs_irq_init_chained_handler()
1598 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_init_chained_handler()
1599 return -EINVAL; in pcs_irq_init_chained_handler()
1613 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_save_context()
1615 if (!pcs->saved_vals) { in pcs_save_context()
1616 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); in pcs_save_context()
1617 if (!pcs->saved_vals) in pcs_save_context()
1618 return -ENOMEM; in pcs_save_context()
1621 switch (pcs->width) { in pcs_save_context()
1623 regsl = pcs->saved_vals; in pcs_save_context()
1624 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1625 *regsl++ = pcs->read(pcs->base + i); in pcs_save_context()
1628 regsw = pcs->saved_vals; in pcs_save_context()
1629 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1630 *regsw++ = pcs->read(pcs->base + i); in pcs_save_context()
1633 regshw = pcs->saved_vals; in pcs_save_context()
1634 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1635 *regshw++ = pcs->read(pcs->base + i); in pcs_save_context()
1649 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_restore_context()
1651 switch (pcs->width) { in pcs_restore_context()
1653 regsl = pcs->saved_vals; in pcs_restore_context()
1654 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1655 pcs->write(*regsl++, pcs->base + i); in pcs_restore_context()
1658 regsw = pcs->saved_vals; in pcs_restore_context()
1659 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1660 pcs->write(*regsw++, pcs->base + i); in pcs_restore_context()
1663 regshw = pcs->saved_vals; in pcs_restore_context()
1664 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1665 pcs->write(*regshw++, pcs->base + i); in pcs_restore_context()
1677 return -EINVAL; in pinctrl_single_suspend()
1679 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { in pinctrl_single_suspend()
1687 return pinctrl_force_sleep(pcs->pctl); in pinctrl_single_suspend()
1696 return -EINVAL; in pinctrl_single_resume()
1698 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) in pinctrl_single_resume()
1701 return pinctrl_force_default(pcs->pctl); in pinctrl_single_resume()
1706 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1711 * Handle legacy binding with no #pinctrl-cells. This should be
1712 * always two pinctrl-single,bit-per-mux and one for others.
1720 const char *name = "#pinctrl-cells"; in pcs_quirk_missing_pinctrl_cells()
1728 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", in pcs_quirk_missing_pinctrl_cells()
1731 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1733 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1735 p->length = sizeof(__be32); in pcs_quirk_missing_pinctrl_cells()
1736 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1737 if (!p->value) in pcs_quirk_missing_pinctrl_cells()
1738 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1739 *(__be32 *)p->value = cpu_to_be32(cells); in pcs_quirk_missing_pinctrl_cells()
1741 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1742 if (!p->name) in pcs_quirk_missing_pinctrl_cells()
1743 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1745 pcs->missing_nr_pinctrl_cells = p; in pcs_quirk_missing_pinctrl_cells()
1748 error = of_add_property(np, pcs->missing_nr_pinctrl_cells); in pcs_quirk_missing_pinctrl_cells()
1756 struct device_node *np = pdev->dev.of_node; in pcs_probe()
1763 soc = of_device_get_match_data(&pdev->dev); in pcs_probe()
1765 return -EINVAL; in pcs_probe()
1767 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); in pcs_probe()
1769 return -ENOMEM; in pcs_probe()
1771 pcs->dev = &pdev->dev; in pcs_probe()
1772 pcs->np = np; in pcs_probe()
1773 raw_spin_lock_init(&pcs->lock); in pcs_probe()
1774 mutex_init(&pcs->mutex); in pcs_probe()
1775 INIT_LIST_HEAD(&pcs->gpiofuncs); in pcs_probe()
1776 pcs->flags = soc->flags; in pcs_probe()
1777 memcpy(&pcs->socdata, soc, sizeof(*soc)); in pcs_probe()
1779 ret = of_property_read_u32(np, "pinctrl-single,register-width", in pcs_probe()
1780 &pcs->width); in pcs_probe()
1782 dev_err(pcs->dev, "register width not specified\n"); in pcs_probe()
1787 ret = of_property_read_u32(np, "pinctrl-single,function-mask", in pcs_probe()
1788 &pcs->fmask); in pcs_probe()
1790 pcs->fshift = __ffs(pcs->fmask); in pcs_probe()
1791 pcs->fmax = pcs->fmask >> pcs->fshift; in pcs_probe()
1794 pcs->fmask = 0; in pcs_probe()
1795 pcs->fshift = 0; in pcs_probe()
1796 pcs->fmax = 0; in pcs_probe()
1799 ret = of_property_read_u32(np, "pinctrl-single,function-off", in pcs_probe()
1800 &pcs->foff); in pcs_probe()
1802 pcs->foff = PCS_OFF_DISABLED; in pcs_probe()
1804 pcs->bits_per_mux = of_property_read_bool(np, in pcs_probe()
1805 "pinctrl-single,bit-per-mux"); in pcs_probe()
1807 pcs->bits_per_mux ? 2 : 1); in pcs_probe()
1809 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); in pcs_probe()
1816 dev_err(pcs->dev, "could not get resource\n"); in pcs_probe()
1817 return -ENODEV; in pcs_probe()
1820 pcs->res = devm_request_mem_region(pcs->dev, res->start, in pcs_probe()
1822 if (!pcs->res) { in pcs_probe()
1823 dev_err(pcs->dev, "could not get mem_region\n"); in pcs_probe()
1824 return -EBUSY; in pcs_probe()
1827 pcs->size = resource_size(pcs->res); in pcs_probe()
1828 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); in pcs_probe()
1829 if (!pcs->base) { in pcs_probe()
1830 dev_err(pcs->dev, "could not ioremap\n"); in pcs_probe()
1831 return -ENODEV; in pcs_probe()
1836 switch (pcs->width) { in pcs_probe()
1838 pcs->read = pcs_readb; in pcs_probe()
1839 pcs->write = pcs_writeb; in pcs_probe()
1842 pcs->read = pcs_readw; in pcs_probe()
1843 pcs->write = pcs_writew; in pcs_probe()
1846 pcs->read = pcs_readl; in pcs_probe()
1847 pcs->write = pcs_writel; in pcs_probe()
1853 pcs->desc.name = DRIVER_NAME; in pcs_probe()
1854 pcs->desc.pctlops = &pcs_pinctrl_ops; in pcs_probe()
1855 pcs->desc.pmxops = &pcs_pinmux_ops; in pcs_probe()
1857 pcs->desc.confops = &pcs_pinconf_ops; in pcs_probe()
1858 pcs->desc.owner = THIS_MODULE; in pcs_probe()
1864 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); in pcs_probe()
1866 dev_err(pcs->dev, "could not register single pinctrl driver\n"); in pcs_probe()
1874 pcs->socdata.irq = irq_of_parse_and_map(np, 0); in pcs_probe()
1875 if (pcs->socdata.irq) in pcs_probe()
1876 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1879 pdata = dev_get_platdata(&pdev->dev); in pcs_probe()
1881 if (pdata->rearm) in pcs_probe()
1882 pcs->socdata.rearm = pdata->rearm; in pcs_probe()
1883 if (pdata->irq) { in pcs_probe()
1884 pcs->socdata.irq = pdata->irq; in pcs_probe()
1885 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1892 dev_warn(pcs->dev, "initialized with no interrupts\n"); in pcs_probe()
1895 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); in pcs_probe()
1897 return pinctrl_enable(pcs->pctl); in pcs_probe()
1942 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1943 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1944 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1945 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1946 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1947 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1948 { .compatible = "pinconf-single", .data = &pinconf_single },
1969 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");