Lines Matching +full:bank +full:- +full:name
62 * There are two registers cfg0 and cfg1 in this style for each bank.
63 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
98 * (direction, retime-type, retime-clk, retime-delay)
100 * +----------------+
101 *[31:28]| reserved-3 |
102 * +----------------+-------------
104 * +----------------+ v
106 * +----------------+ ^
108 * +----------------+-------------
109 *[24] | reserved-2 |
110 * +----------------+-------------
112 * +----------------+ |
113 *[22] | retime-invclk | |
114 * +----------------+ v
115 *[21] |retime-clknotdat| [Retime-type ]
116 * +----------------+ ^
117 *[20] | retime-de | |
118 * +----------------+-------------
119 *[19:18]| retime-clk |------>[Retime-Clk ]
120 * +----------------+
121 *[17:16]| reserved-1 |
122 * +----------------+
123 *[15..0]| retime-delay |------>[Retime Delay]
124 * +----------------+
251 const char *name; member
257 const char *name; member
263 const char *name; member
273 * of each gpio pin in a GPIO bank.
275 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
276 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
279 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
280 * --------------------------------------------------------
281 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
282 * --------------------------------------------------------
286 * ------- ----------------------------
287 * [0-3] - Description
288 * ------- ----------------------------
289 * 0000 - No edge IRQ.
290 * 0001 - Falling edge IRQ.
291 * 0010 - Rising edge IRQ.
292 * 0011 - Rising and Falling edge IRQ.
293 * ------- ----------------------------
358 .oe = -1, /* Not Available */
359 .pu = -1, /* Not Available */
369 struct st_gpio_bank *bank = gpio_range_to_bank(range); in st_get_pio_control() local
371 return &bank->pc; in st_get_pio_control()
388 struct regmap_field *output_enable = pc->oe; in st_pinconf_set_config()
389 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
390 struct regmap_field *open_drain = pc->od; in st_pinconf_set_config()
422 struct regmap_field *alt = pc->alt; in st_pctl_set_function()
438 struct regmap_field *alt = pc->alt; in st_pctl_get_pin_function()
454 int num_delay_times, i, closest_index = -1; in st_pinconf_delay_to_bit()
458 delay_times = data->output_delays; in st_pinconf_delay_to_bit()
459 num_delay_times = data->noutput_delays; in st_pinconf_delay_to_bit()
461 delay_times = data->input_delays; in st_pinconf_delay_to_bit()
462 num_delay_times = data->ninput_delays; in st_pinconf_delay_to_bit()
466 unsigned int divergence = abs(delay - delay_times[i]); in st_pinconf_delay_to_bit()
490 delay_times = data->output_delays; in st_pinconf_bit_to_delay()
491 num_delay_times = data->noutput_delays; in st_pinconf_bit_to_delay()
493 delay_times = data->input_delays; in st_pinconf_bit_to_delay()
494 num_delay_times = data->ninput_delays; in st_pinconf_bit_to_delay()
521 const struct st_pctl_data *data = info->data; in st_pinconf_set_retime_packed()
522 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_set_retime_packed()
525 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, in st_pinconf_set_retime_packed()
528 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, in st_pinconf_set_retime_packed()
531 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, in st_pinconf_set_retime_packed()
534 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, in st_pinconf_set_retime_packed()
537 st_regmap_field_bit_set_clear_pin(rt_p->retime, in st_pinconf_set_retime_packed()
543 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); in st_pinconf_set_retime_packed()
545 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); in st_pinconf_set_retime_packed()
561 info->data, config); in st_pinconf_set_retime_dedicated()
562 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_set_retime_dedicated()
573 regmap_field_write(rt_d->rt[pin], retime_config); in st_pinconf_set_retime_dedicated()
581 if (pc->oe) { in st_pinconf_get_direction()
582 regmap_field_read(pc->oe, &oe_value); in st_pinconf_get_direction()
587 if (pc->pu) { in st_pinconf_get_direction()
588 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
593 if (pc->od) { in st_pinconf_get_direction()
594 regmap_field_read(pc->od, &od_value); in st_pinconf_get_direction()
603 const struct st_pctl_data *data = info->data; in st_pinconf_get_retime_packed()
604 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_get_retime_packed()
608 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
611 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
614 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
617 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
620 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
623 regmap_field_read(rt_p->delay_0, &delay0); in st_pinconf_get_retime_packed()
624 regmap_field_read(rt_p->delay_1, &delay1); in st_pinconf_get_retime_packed()
639 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_get_retime_dedicated()
641 regmap_field_read(rt_d->rt[pin], &value); in st_pinconf_get_retime_dedicated()
647 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); in st_pinconf_get_retime_dedicated()
667 static inline void __st_gpio_set(struct st_gpio_bank *bank, in __st_gpio_set() argument
671 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); in __st_gpio_set()
673 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); in __st_gpio_set()
676 static void st_gpio_direction(struct st_gpio_bank *bank, in st_gpio_direction() argument
690 * 0 0 0 [Input Weak pull-up] in st_gpio_direction()
700 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); in st_gpio_direction()
702 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); in st_gpio_direction()
708 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_get() local
710 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); in st_gpio_get()
715 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_set() local
716 __st_gpio_set(bank, offset, value); in st_gpio_set()
721 pinctrl_gpio_direction_input(chip->base + offset); in st_gpio_direction_input()
729 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_direction_output() local
731 __st_gpio_set(bank, offset, value); in st_gpio_direction_output()
732 pinctrl_gpio_direction_output(chip->base + offset); in st_gpio_direction_output()
739 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_get_direction() local
740 struct st_pio_control pc = bank->pc; in st_gpio_get_direction()
756 * - See st_gpio_direction() above for an explanation in st_gpio_get_direction()
759 value = readl(bank->base + REG_PIO_PC(i)); in st_gpio_get_direction()
771 return info->ngroups; in st_pctl_get_groups_count()
779 return info->groups[selector].name; in st_pctl_get_group_name()
787 if (selector >= info->ngroups) in st_pctl_get_group_pins()
788 return -EINVAL; in st_pctl_get_group_pins()
790 *pins = info->groups[selector].pins; in st_pctl_get_group_pins()
791 *npins = info->groups[selector].npins; in st_pctl_get_group_pins()
797 const struct st_pinctrl *info, const char *name) in st_pctl_find_group_by_name() argument
801 for (i = 0; i < info->ngroups; i++) { in st_pctl_find_group_by_name()
802 if (!strcmp(info->groups[i].name, name)) in st_pctl_find_group_by_name()
803 return &info->groups[i]; in st_pctl_find_group_by_name()
818 grp = st_pctl_find_group_by_name(info, np->name); in st_pctl_dt_node_to_map()
820 dev_err(info->dev, "unable to find group for node %s\n", in st_pctl_dt_node_to_map()
821 np->name); in st_pctl_dt_node_to_map()
822 return -EINVAL; in st_pctl_dt_node_to_map()
825 map_num = grp->npins + 1; in st_pctl_dt_node_to_map()
826 new_map = devm_kcalloc(pctldev->dev, in st_pctl_dt_node_to_map()
829 return -ENOMEM; in st_pctl_dt_node_to_map()
833 devm_kfree(pctldev->dev, new_map); in st_pctl_dt_node_to_map()
834 return -EINVAL; in st_pctl_dt_node_to_map()
840 new_map[0].data.mux.function = parent->name; in st_pctl_dt_node_to_map()
841 new_map[0].data.mux.group = np->name; in st_pctl_dt_node_to_map()
846 for (i = 0; i < grp->npins; i++) { in st_pctl_dt_node_to_map()
849 pin_get_name(pctldev, grp->pins[i]); in st_pctl_dt_node_to_map()
850 new_map[i].data.configs.configs = &grp->pin_conf[i].config; in st_pctl_dt_node_to_map()
853 dev_info(pctldev->dev, "maps: function %s group %s num %d\n", in st_pctl_dt_node_to_map()
854 (*map)->data.mux.function, grp->name, map_num); in st_pctl_dt_node_to_map()
877 return info->nfunctions; in st_pmx_get_funcs_count()
885 return info->functions[selector].name; in st_pmx_get_fname()
892 *grps = info->functions[selector].groups; in st_pmx_get_groups()
893 *ngrps = info->functions[selector].ngroups; in st_pmx_get_groups()
902 struct st_pinconf *conf = info->groups[group].pin_conf; in st_pmx_set_mux()
906 for (i = 0; i < info->groups[group].npins; i++) { in st_pmx_set_mux()
918 struct st_gpio_bank *bank = gpio_range_to_bank(range); in st_pmx_set_gpio_direction() local
920 * When a PIO bank is used in its primary function mode (altfunc = 0) in st_pmx_set_gpio_direction()
924 st_pctl_set_function(&bank->pc, gpio, 0); in st_pmx_set_gpio_direction()
925 st_gpio_direction(bank, gpio, input ? in st_pmx_set_gpio_direction()
944 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_get_retime()
946 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_get_retime()
947 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_get_retime()
955 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_set_retime()
957 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_set_retime()
958 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_set_retime()
1002 mutex_unlock(&pctldev->mutex); in st_pinconf_dbg_show()
1005 mutex_lock(&pctldev->mutex); in st_pinconf_dbg_show()
1015 "de:%ld,rt-clk:%ld,rt-delay:%ld]", in st_pinconf_dbg_show()
1016 !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset), in st_pinconf_dbg_show()
1039 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_dt_child_count()
1040 info->nbanks++; in st_pctl_dt_child_count()
1042 info->nfunctions++; in st_pctl_dt_child_count()
1043 info->ngroups += of_get_child_count(child); in st_pctl_dt_child_count()
1049 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime_packed() argument
1051 struct device *dev = info->dev; in st_pctl_dt_setup_retime_packed()
1052 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_packed()
1053 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_packed()
1054 /* 2 registers per bank */ in st_pctl_dt_setup_retime_packed()
1055 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_packed()
1056 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pctl_dt_setup_retime_packed()
1067 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); in st_pctl_dt_setup_retime_packed()
1068 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); in st_pctl_dt_setup_retime_packed()
1069 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); in st_pctl_dt_setup_retime_packed()
1070 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); in st_pctl_dt_setup_retime_packed()
1071 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); in st_pctl_dt_setup_retime_packed()
1072 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); in st_pctl_dt_setup_retime_packed()
1073 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); in st_pctl_dt_setup_retime_packed()
1075 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || in st_pctl_dt_setup_retime_packed()
1076 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || in st_pctl_dt_setup_retime_packed()
1077 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || in st_pctl_dt_setup_retime_packed()
1078 IS_ERR(rt_p->double_edge)) in st_pctl_dt_setup_retime_packed()
1079 return -EINVAL; in st_pctl_dt_setup_retime_packed()
1085 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime_dedicated() argument
1087 struct device *dev = info->dev; in st_pctl_dt_setup_retime_dedicated()
1088 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_dedicated()
1089 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_dedicated()
1090 /* 8 registers per bank */ in st_pctl_dt_setup_retime_dedicated()
1091 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_dedicated()
1092 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pctl_dt_setup_retime_dedicated()
1094 u32 pin_mask = pc->rt_pin_mask; in st_pctl_dt_setup_retime_dedicated()
1099 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); in st_pctl_dt_setup_retime_dedicated()
1100 if (IS_ERR(rt_d->rt[j])) in st_pctl_dt_setup_retime_dedicated()
1101 return -EINVAL; in st_pctl_dt_setup_retime_dedicated()
1109 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime() argument
1111 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime()
1112 if (data->rt_style == st_retime_style_packed) in st_pctl_dt_setup_retime()
1113 return st_pctl_dt_setup_retime_packed(info, bank, pc); in st_pctl_dt_setup_retime()
1114 else if (data->rt_style == st_retime_style_dedicated) in st_pctl_dt_setup_retime()
1115 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); in st_pctl_dt_setup_retime()
1117 return -EINVAL; in st_pctl_dt_setup_retime()
1122 struct regmap *regmap, int bank, in st_pc_get_value() argument
1125 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); in st_pc_get_value()
1133 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, in st_parse_syscfgs() argument
1136 const struct st_pctl_data *data = info->data; in st_parse_syscfgs()
1138 * For a given shared register like OE/PU/OD, there are 8 bits per bank in st_parse_syscfgs()
1142 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; in st_parse_syscfgs()
1143 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; in st_parse_syscfgs()
1144 struct st_pio_control *pc = &info->banks[bank].pc; in st_parse_syscfgs()
1145 struct device *dev = info->dev; in st_parse_syscfgs()
1146 struct regmap *regmap = info->regmap; in st_parse_syscfgs()
1148 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); in st_parse_syscfgs()
1149 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); in st_parse_syscfgs()
1150 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); in st_parse_syscfgs()
1151 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); in st_parse_syscfgs()
1154 pc->rt_pin_mask = 0xff; in st_parse_syscfgs()
1155 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); in st_parse_syscfgs()
1156 st_pctl_dt_setup_retime(info, bank, pc); in st_parse_syscfgs()
1163 * <bank offset mux direction rt_type rt_delay rt_clk>
1168 /* bank pad direction val altfunction */ in st_pctl_dt_parse_groups()
1177 return -ENODATA; in st_pctl_dt_parse_groups()
1181 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1184 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { in st_pctl_dt_parse_groups()
1187 pr_warn("Invalid st,pins in %s node\n", np->name); in st_pctl_dt_parse_groups()
1188 return -EINVAL; in st_pctl_dt_parse_groups()
1192 grp->npins = npins; in st_pctl_dt_parse_groups()
1193 grp->name = np->name; in st_pctl_dt_parse_groups()
1194 grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL); in st_pctl_dt_parse_groups()
1195 grp->pin_conf = devm_kcalloc(info->dev, in st_pctl_dt_parse_groups()
1198 if (!grp->pins || !grp->pin_conf) in st_pctl_dt_parse_groups()
1199 return -ENOMEM; in st_pctl_dt_parse_groups()
1201 /* <bank offset mux direction rt_type rt_delay rt_clk> */ in st_pctl_dt_parse_groups()
1203 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1205 nr_props = pp->length/sizeof(u32); in st_pctl_dt_parse_groups()
1206 list = pp->value; in st_pctl_dt_parse_groups()
1207 conf = &grp->pin_conf[i]; in st_pctl_dt_parse_groups()
1209 /* bank & offset */ in st_pctl_dt_parse_groups()
1212 conf->pin = of_get_named_gpio(pins, pp->name, 0); in st_pctl_dt_parse_groups()
1213 conf->name = pp->name; in st_pctl_dt_parse_groups()
1214 grp->pins[i] = conf->pin; in st_pctl_dt_parse_groups()
1216 conf->altfunc = be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1217 conf->config = 0; in st_pctl_dt_parse_groups()
1219 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1223 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1225 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1228 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1245 func = &info->functions[index]; in st_pctl_parse_functions()
1246 func->name = np->name; in st_pctl_parse_functions()
1247 func->ngroups = of_get_child_count(np); in st_pctl_parse_functions()
1248 if (func->ngroups == 0) { in st_pctl_parse_functions()
1249 dev_err(info->dev, "No groups defined\n"); in st_pctl_parse_functions()
1250 return -EINVAL; in st_pctl_parse_functions()
1252 func->groups = devm_kcalloc(info->dev, in st_pctl_parse_functions()
1253 func->ngroups, sizeof(char *), GFP_KERNEL); in st_pctl_parse_functions()
1254 if (!func->groups) in st_pctl_parse_functions()
1255 return -ENOMEM; in st_pctl_parse_functions()
1259 func->groups[i] = child->name; in st_pctl_parse_functions()
1260 grp = &info->groups[*grp_index]; in st_pctl_parse_functions()
1266 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", in st_pctl_parse_functions()
1267 index, func->name, func->ngroups); in st_pctl_parse_functions()
1275 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_mask() local
1277 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); in st_gpio_irq_mask()
1283 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_unmask() local
1285 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); in st_gpio_irq_unmask()
1292 st_gpio_direction_input(gc, d->hwirq); in st_gpio_irq_request_resources()
1294 return gpiochip_lock_as_irq(gc, d->hwirq); in st_gpio_irq_request_resources()
1301 gpiochip_unlock_as_irq(gc, d->hwirq); in st_gpio_irq_release_resources()
1307 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_set_type() local
1309 int comp, pin = d->hwirq; in st_gpio_irq_set_type()
1329 comp = st_gpio_get(&bank->gpio_chip, pin); in st_gpio_irq_set_type()
1333 return -EINVAL; in st_gpio_irq_set_type()
1336 spin_lock_irqsave(&bank->lock, flags); in st_gpio_irq_set_type()
1337 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( in st_gpio_irq_set_type()
1339 bank->irq_edge_conf |= pin_edge_conf; in st_gpio_irq_set_type()
1340 spin_unlock_irqrestore(&bank->lock, flags); in st_gpio_irq_set_type()
1342 val = readl(bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1345 writel(val, bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1358 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1362 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1366 * step-1 ________ __________
1367 * | | step - 3
1369 * step -2 |_____|
1374 static void __gpio_irq_handler(struct st_gpio_bank *bank) in __gpio_irq_handler() argument
1380 spin_lock_irqsave(&bank->lock, flags); in __gpio_irq_handler()
1381 bank_edge_mask = bank->irq_edge_conf; in __gpio_irq_handler()
1382 spin_unlock_irqrestore(&bank->lock, flags); in __gpio_irq_handler()
1385 port_in = readl(bank->base + REG_PIO_PIN); in __gpio_irq_handler()
1386 port_comp = readl(bank->base + REG_PIO_PCOMP); in __gpio_irq_handler()
1387 port_mask = readl(bank->base + REG_PIO_PMASK); in __gpio_irq_handler()
1400 val = st_gpio_get(&bank->gpio_chip, n); in __gpio_irq_handler()
1403 val ? bank->base + REG_PIO_SET_PCOMP : in __gpio_irq_handler()
1404 bank->base + REG_PIO_CLR_PCOMP); in __gpio_irq_handler()
1411 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n)); in __gpio_irq_handler()
1418 /* interrupt dedicated per bank */ in st_gpio_irq_handler()
1421 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_handler() local
1424 __gpio_irq_handler(bank); in st_gpio_irq_handler()
1437 status = readl(info->irqmux_base); in st_gpio_irqmux_handler()
1439 for_each_set_bit(n, &status, info->nbanks) in st_gpio_irqmux_handler()
1440 __gpio_irq_handler(&info->banks[n]); in st_gpio_irqmux_handler()
1457 .name = "GPIO",
1470 struct st_gpio_bank *bank = &info->banks[bank_nr]; in st_gpiolib_register_bank() local
1471 struct pinctrl_gpio_range *range = &bank->range; in st_gpiolib_register_bank()
1472 struct device *dev = info->dev; in st_gpiolib_register_bank()
1478 return -ENODEV; in st_gpiolib_register_bank()
1480 bank->base = devm_ioremap_resource(dev, &res); in st_gpiolib_register_bank()
1481 if (IS_ERR(bank->base)) in st_gpiolib_register_bank()
1482 return PTR_ERR(bank->base); in st_gpiolib_register_bank()
1484 bank->gpio_chip = st_gpio_template; in st_gpiolib_register_bank()
1485 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1486 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1487 bank->gpio_chip.of_node = np; in st_gpiolib_register_bank()
1488 bank->gpio_chip.parent = dev; in st_gpiolib_register_bank()
1489 spin_lock_init(&bank->lock); in st_gpiolib_register_bank()
1491 of_property_read_string(np, "st,bank-name", &range->name); in st_gpiolib_register_bank()
1492 bank->gpio_chip.label = range->name; in st_gpiolib_register_bank()
1494 range->id = bank_num; in st_gpiolib_register_bank()
1495 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1496 range->npins = bank->gpio_chip.ngpio; in st_gpiolib_register_bank()
1497 range->gc = &bank->gpio_chip; in st_gpiolib_register_bank()
1498 err = gpiochip_add_data(&bank->gpio_chip, bank); in st_gpiolib_register_bank()
1503 dev_info(dev, "%s bank added.\n", range->name); in st_gpiolib_register_bank()
1506 * GPIO bank can have one of the two possible types of in st_gpiolib_register_bank()
1507 * interrupt-wirings. in st_gpiolib_register_bank()
1513 * | |----> [gpio-bank (n) ] in st_gpiolib_register_bank()
1514 * | |----> [gpio-bank (n + 1)] in st_gpiolib_register_bank()
1515 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] in st_gpiolib_register_bank()
1516 * | |----> [gpio-bank (... )] in st_gpiolib_register_bank()
1517 * |_________|----> [gpio-bank (n + 7)] in st_gpiolib_register_bank()
1519 * Second type has a dedicated interrupt per each gpio bank. in st_gpiolib_register_bank()
1521 * [irqN]----> [gpio-bank (n)] in st_gpiolib_register_bank()
1526 gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, in st_gpiolib_register_bank()
1530 if (info->irqmux_base || gpio_irq > 0) { in st_gpiolib_register_bank()
1531 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, in st_gpiolib_register_bank()
1535 gpiochip_remove(&bank->gpio_chip); in st_gpiolib_register_bank()
1540 dev_info(dev, "No IRQ support for %pOF bank\n", np); in st_gpiolib_register_bank()
1547 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1548 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1549 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1550 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1558 int i = 0, j = 0, k = 0, bank; in st_pctl_probe_dt() local
1560 struct device_node *np = pdev->dev.of_node; in st_pctl_probe_dt()
1567 if (!info->nbanks) { in st_pctl_probe_dt()
1568 dev_err(&pdev->dev, "you need atleast one gpio bank\n"); in st_pctl_probe_dt()
1569 return -EINVAL; in st_pctl_probe_dt()
1572 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); in st_pctl_probe_dt()
1573 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in st_pctl_probe_dt()
1574 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); in st_pctl_probe_dt()
1576 info->functions = devm_kcalloc(&pdev->dev, in st_pctl_probe_dt()
1577 info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in st_pctl_probe_dt()
1579 info->groups = devm_kcalloc(&pdev->dev, in st_pctl_probe_dt()
1580 info->ngroups, sizeof(*info->groups), in st_pctl_probe_dt()
1583 info->banks = devm_kcalloc(&pdev->dev, in st_pctl_probe_dt()
1584 info->nbanks, sizeof(*info->banks), GFP_KERNEL); in st_pctl_probe_dt()
1586 if (!info->functions || !info->groups || !info->banks) in st_pctl_probe_dt()
1587 return -ENOMEM; in st_pctl_probe_dt()
1589 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in st_pctl_probe_dt()
1590 if (IS_ERR(info->regmap)) { in st_pctl_probe_dt()
1591 dev_err(info->dev, "No syscfg phandle specified\n"); in st_pctl_probe_dt()
1592 return PTR_ERR(info->regmap); in st_pctl_probe_dt()
1594 info->data = of_match_node(st_pctl_of_match, np)->data; in st_pctl_probe_dt()
1601 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); in st_pctl_probe_dt()
1603 if (IS_ERR(info->irqmux_base)) in st_pctl_probe_dt()
1604 return PTR_ERR(info->irqmux_base); in st_pctl_probe_dt()
1611 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; in st_pctl_probe_dt()
1612 pdesc = devm_kcalloc(&pdev->dev, in st_pctl_probe_dt()
1613 pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); in st_pctl_probe_dt()
1615 return -ENOMEM; in st_pctl_probe_dt()
1617 pctl_desc->pins = pdesc; in st_pctl_probe_dt()
1619 bank = 0; in st_pctl_probe_dt()
1621 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_probe_dt()
1623 ret = st_gpiolib_register_bank(info, bank, child); in st_pctl_probe_dt()
1627 k = info->banks[bank].range.pin_base; in st_pctl_probe_dt()
1628 bank_name = info->banks[bank].range.name; in st_pctl_probe_dt()
1630 pdesc->number = k; in st_pctl_probe_dt()
1631 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", in st_pctl_probe_dt()
1635 st_parse_syscfgs(info, bank, child); in st_pctl_probe_dt()
1636 bank++; in st_pctl_probe_dt()
1641 dev_err(&pdev->dev, "No functions found.\n"); in st_pctl_probe_dt()
1656 if (!pdev->dev.of_node) { in st_pctl_probe()
1657 dev_err(&pdev->dev, "device node not found.\n"); in st_pctl_probe()
1658 return -EINVAL; in st_pctl_probe()
1661 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); in st_pctl_probe()
1663 return -ENOMEM; in st_pctl_probe()
1665 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); in st_pctl_probe()
1667 return -ENOMEM; in st_pctl_probe()
1669 info->dev = &pdev->dev; in st_pctl_probe()
1675 pctl_desc->owner = THIS_MODULE; in st_pctl_probe()
1676 pctl_desc->pctlops = &st_pctlops; in st_pctl_probe()
1677 pctl_desc->pmxops = &st_pmxops; in st_pctl_probe()
1678 pctl_desc->confops = &st_confops; in st_pctl_probe()
1679 pctl_desc->name = dev_name(&pdev->dev); in st_pctl_probe()
1681 info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info); in st_pctl_probe()
1682 if (IS_ERR(info->pctl)) { in st_pctl_probe()
1683 dev_err(&pdev->dev, "Failed pinctrl registration\n"); in st_pctl_probe()
1684 return PTR_ERR(info->pctl); in st_pctl_probe()
1687 for (i = 0; i < info->nbanks; i++) in st_pctl_probe()
1688 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); in st_pctl_probe()
1695 .name = "st-pinctrl",