Lines Matching +full:spi +full:- +full:nand
2 * linux/drivers/pinctrl/pinmux-xway.c
3 * based on linux/drivers/pinctrl/pinmux-pxa910.c
24 #include "pinctrl-lantiq.h"
113 /* --------- DEPRECATED: xr9 related code --------- */
114 /* ---------- use xrx100/xrx200 instead ---------- */
128 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
129 MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
130 MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI),
132 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
134 MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE),
135 MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG),
136 MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG),
137 MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG),
141 MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE),
252 GRP_MUX("nand ale", EBU, pins_nand_ale),
253 GRP_MUX("nand cs1", EBU, pins_nand_cs1),
254 GRP_MUX("nand cle", EBU, pins_nand_cle),
255 GRP_MUX("spi", SPI, pins_spi),
256 GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
257 GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
258 GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
259 GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
260 GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
261 GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
280 GRP_MUX("nand rdy", EBU, pins_nand_rdy),
281 GRP_MUX("nand rd", EBU, pins_nand_rd),
299 static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
308 "nand ale", "nand cs1",
309 "nand cle"};
325 "nand ale", "nand cs1",
326 "nand cle", "nand rdy",
327 "nand rd"};
336 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
350 /* --------- ase related code --------- */
362 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
363 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
364 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
365 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
369 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
370 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
426 GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
427 GRP_MUX("spi_di", SPI, ase_pins_spi_di),
428 GRP_MUX("spi_do", SPI, ase_pins_spi_do),
429 GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
430 GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
431 GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
432 GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
460 static const char * const ase_spi_grps[] = {"spi", /* DEPRECATED */
466 {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
478 /* --------- danube related code --------- */
492 MFP_XWAY(GPIO9, GPIO, ASC, SPI, MII),
493 MFP_XWAY(GPIO10, GPIO, ASC, SPI, MII),
494 MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
496 MFP_XWAY(GPIO13, GPIO, EBU, SPI, MII),
498 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, JTAG),
499 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, JTAG),
500 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, JTAG),
501 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, JTAG),
505 MFP_XWAY(GPIO22, GPIO, SPI, MCD, MII),
581 GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
582 GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
583 GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
584 GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
585 GRP_MUX("spi_di", SPI, danube_pins_spi_di),
586 GRP_MUX("spi_do", SPI, danube_pins_spi_do),
587 GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
588 GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
589 GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
590 GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
591 GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
592 GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
593 GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
618 static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
629 "nand ale", "nand cs1",
630 "nand cle"};
640 {"spi", ARRAY_AND_SIZE(danube_spi_grps)},
653 /* --------- xrx100 related code --------- */
667 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
668 MFP_XWAY(GPIO10, GPIO, ASC, SPI, EXIN),
669 MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
671 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
673 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
674 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
675 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
676 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
680 MFP_XWAY(GPIO22, GPIO, SPI, NONE, EBU),
788 GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
789 GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
790 GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
791 GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
792 GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
793 GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
794 GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
795 GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
796 GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
797 GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
798 GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
799 GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
800 GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
801 GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
840 "nand ale", "nand cs1",
841 "nand cle", "nand rdy",
842 "nand rd"};
853 {"spi", ARRAY_AND_SIZE(xrx100_spi_grps)},
866 /* --------- xrx200 related code --------- */
880 MFP_XWAY(GPIO9, GPIO, USIF, SPI, EXIN),
881 MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
882 MFP_XWAY(GPIO11, GPIO, USIF, CBUS, SPI),
884 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
886 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
887 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
888 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
889 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
893 MFP_XWAY(GPIO22, GPIO, SPI, CGU, EBU),
1016 GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
1017 GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
1018 GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
1019 GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
1020 GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
1021 GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
1022 GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
1023 GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
1024 GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
1025 GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
1026 GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
1027 GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
1028 GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
1029 GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
1086 "nand ale", "nand cs1",
1087 "nand cle", "nand rdy",
1088 "nand rd"};
1108 {"spi", ARRAY_AND_SIZE(xrx200_spi_grps)},
1122 /* --------- xrx300 related code --------- */
1137 MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
1138 MFP_XWAY(GPIO11, GPIO, USIF, WIFI, SPI),
1142 MFP_XWAY(GPIO15, GPIO, SPI, NONE, MCD),
1143 MFP_XWAY(GPIO16, GPIO, SPI, EXIN, NONE),
1144 MFP_XWAY(GPIO17, GPIO, SPI, NONE, NONE),
1145 MFP_XWAY(GPIO18, GPIO, SPI, NONE, NONE),
1259 GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
1260 GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
1261 GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
1262 GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
1263 GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
1264 GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
1265 GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
1266 GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
1267 GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
1268 GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
1269 GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
1270 GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
1271 GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
1272 GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
1273 GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
1274 GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
1275 GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
1276 GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
1277 GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
1278 GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
1279 GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
1280 GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
1281 GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
1303 static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
1304 "nand cle", "nand rdy",
1305 "nand rd", "nand d1",
1306 "nand d0", "nand d2",
1307 "nand d7", "nand d6",
1308 "nand d5", "nand d4",
1309 "nand d3", "nand cs0",
1310 "nand wr", "nand wp",
1311 "nand se"};
1324 {"spi", ARRAY_AND_SIZE(xrx300_spi_grps)},
1335 /* --------- pinconf related code --------- */
1352 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
1360 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { in xway_pinconf_get()
1369 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) in xway_pinconf_get()
1378 gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
1381 dev_err(pctldev->dev, "Invalid config param %04x\n", param); in xway_pinconf_get()
1382 return -ENOTSUPP; in xway_pinconf_get()
1410 gpio_setbit(info->membase[0], in xway_pinconf_set()
1414 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1425 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1430 gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); in xway_pinconf_set()
1437 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1441 gpio_setbit(info->membase[0], in xway_pinconf_set()
1445 dev_err(pctldev->dev, in xway_pinconf_set()
1452 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1456 gpio_setbit(info->membase[0], in xway_pinconf_set()
1462 dev_err(pctldev->dev, in xway_pinconf_set()
1464 return -ENOTSUPP; in xway_pinconf_set()
1479 for (i = 0; i < info->grps[selector].npins && !ret; i++) in xway_pinconf_group_set()
1481 info->grps[selector].pins[i], in xway_pinconf_group_set()
1510 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); in xway_mux_apply()
1512 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); in xway_mux_apply()
1515 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); in xway_mux_apply()
1517 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); in xway_mux_apply()
1524 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
1535 /* --------- gpio_chip related code --------- */
1538 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_set()
1541 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); in xway_gpio_set()
1543 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); in xway_gpio_set()
1548 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_get()
1550 return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); in xway_gpio_get()
1555 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_dir_in()
1557 gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); in xway_gpio_dir_in()
1564 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_dir_out()
1567 gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin)); in xway_gpio_dir_out()
1569 gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin)); in xway_gpio_dir_out()
1570 gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); in xway_gpio_dir_out()
1582 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_to_irq()
1585 for (i = 0; i < info->num_exin; i++) in xway_gpio_to_irq()
1586 if (info->exin[i] == offset) in xway_gpio_to_irq()
1589 return -1; in xway_gpio_to_irq()
1593 .label = "gpio-xway",
1601 .base = -1,
1605 /* --------- register the pinctrl layer --------- */
1695 { .compatible = "lantiq,pinctrl-xway", .data = &danube_pinctrl}, /*DEPRECATED*/
1696 { .compatible = "lantiq,pinctrl-xr9", .data = &xr9_pinctrl}, /*DEPRECATED*/
1697 { .compatible = "lantiq,pinctrl-ase", .data = &ase_pinctrl}, /*DEPRECATED*/
1698 { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
1699 { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
1700 { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
1701 { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
1702 { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
1716 xway_info.membase[0] = devm_ioremap_resource(&pdev->dev, res); in pinmux_xway_probe()
1720 match = of_match_device(xway_match, &pdev->dev); in pinmux_xway_probe()
1722 xway_soc = (const struct pinctrl_xway_soc *) match->data; in pinmux_xway_probe()
1727 xway_chip.ngpio = xway_soc->pin_count; in pinmux_xway_probe()
1730 xway_info.pads = devm_kcalloc(&pdev->dev, in pinmux_xway_probe()
1734 return -ENOMEM; in pinmux_xway_probe()
1738 char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); in pinmux_xway_probe()
1741 return -ENOMEM; in pinmux_xway_probe()
1750 xway_pctrl_desc.name = dev_name(&pdev->dev); in pinmux_xway_probe()
1755 xway_info.mfp = xway_soc->mfp; in pinmux_xway_probe()
1756 xway_info.grps = xway_soc->grps; in pinmux_xway_probe()
1757 xway_info.num_grps = xway_soc->num_grps; in pinmux_xway_probe()
1758 xway_info.funcs = xway_soc->funcs; in pinmux_xway_probe()
1759 xway_info.num_funcs = xway_soc->num_funcs; in pinmux_xway_probe()
1760 xway_info.exin = xway_soc->exin; in pinmux_xway_probe()
1761 xway_info.num_exin = xway_soc->num_exin; in pinmux_xway_probe()
1766 dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); in pinmux_xway_probe()
1771 xway_chip.parent = &pdev->dev; in pinmux_xway_probe()
1773 xway_chip.of_node = pdev->dev.of_node; in pinmux_xway_probe()
1774 ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL); in pinmux_xway_probe()
1776 dev_err(&pdev->dev, "Failed to register gpio chip\n"); in pinmux_xway_probe()
1781 * For DeviceTree-supported systems, the gpio core checks the in pinmux_xway_probe()
1782 * pinctrl's device node for the "gpio-ranges" property. in pinmux_xway_probe()
1787 * files which don't set the "gpio-ranges" property or systems that in pinmux_xway_probe()
1790 if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) { in pinmux_xway_probe()
1797 dev_info(&pdev->dev, "Init done\n"); in pinmux_xway_probe()
1804 .name = "pinctrl-xway",