Lines Matching full:g
151 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
156 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
157 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
159 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
160 if (g->funcs[i] == function) in msm_pinmux_set_mux()
164 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
169 val = readl(pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
171 val |= i << g->mux_bit; in msm_pinmux_set_mux()
172 writel(val, pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
188 const struct msm_pingroup *g, in msm_config_reg() argument
198 *bit = g->pull_bit; in msm_config_reg()
202 *bit = g->drv_bit; in msm_config_reg()
207 *bit = g->oe_bit; in msm_config_reg()
232 const struct msm_pingroup *g; in msm_config_group_get() local
241 g = &pctrl->soc->groups[group]; in msm_config_group_get()
243 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
247 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_get()
286 val = readl(pctrl->regs + g->io_reg); in msm_config_group_get()
287 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
309 const struct msm_pingroup *g; in msm_config_group_set() local
320 g = &pctrl->soc->groups[group]; in msm_config_group_set()
326 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
360 val = readl(pctrl->regs + g->io_reg); in msm_config_group_set()
362 val |= BIT(g->out_bit); in msm_config_group_set()
364 val &= ~BIT(g->out_bit); in msm_config_group_set()
365 writel(val, pctrl->regs + g->io_reg); in msm_config_group_set()
388 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_set()
391 writel(val, pctrl->regs + g->ctl_reg); in msm_config_group_set()
406 const struct msm_pingroup *g; in msm_gpio_direction_input() local
411 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
415 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
416 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
417 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
426 const struct msm_pingroup *g; in msm_gpio_direction_output() local
431 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
435 val = readl(pctrl->regs + g->io_reg); in msm_gpio_direction_output()
437 val |= BIT(g->out_bit); in msm_gpio_direction_output()
439 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
440 writel(val, pctrl->regs + g->io_reg); in msm_gpio_direction_output()
442 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
443 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
444 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
454 const struct msm_pingroup *g; in msm_gpio_get_direction() local
457 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
459 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_get_direction()
462 return val & BIT(g->oe_bit) ? 0 : 1; in msm_gpio_get_direction()
467 const struct msm_pingroup *g; in msm_gpio_get() local
471 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
473 val = readl(pctrl->regs + g->io_reg); in msm_gpio_get()
474 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
479 const struct msm_pingroup *g; in msm_gpio_set() local
484 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
488 val = readl(pctrl->regs + g->io_reg); in msm_gpio_set()
490 val |= BIT(g->out_bit); in msm_gpio_set()
492 val &= ~BIT(g->out_bit); in msm_gpio_set()
493 writel(val, pctrl->regs + g->io_reg); in msm_gpio_set()
507 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
532 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
533 ctl_reg = readl(pctrl->regs + g->ctl_reg); in msm_gpio_dbg_show_one()
534 io_reg = readl(pctrl->regs + g->io_reg); in msm_gpio_dbg_show_one()
536 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
537 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
538 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
539 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
542 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
544 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
546 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
601 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
609 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
611 pol = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_update_dual_edge_pos()
612 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
613 writel(pol, pctrl->regs + g->intr_cfg_reg); in msm_gpio_update_dual_edge_pos()
615 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
616 intstat = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_update_dual_edge_pos()
628 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
632 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
636 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_mask()
658 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
660 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
661 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_mask()
672 const struct msm_pingroup *g; in msm_gpio_irq_unmask() local
676 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
680 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_unmask()
681 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
682 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
683 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_unmask()
694 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
698 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
702 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_ack()
703 if (g->intr_ack_high) in msm_gpio_irq_ack()
704 val |= BIT(g->intr_status_bit); in msm_gpio_irq_ack()
706 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_ack()
707 writel(val, pctrl->regs + g->intr_status_reg); in msm_gpio_irq_ack()
710 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
719 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
723 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
730 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
736 val = readl(pctrl->regs + g->intr_target_reg); in msm_gpio_irq_set_type()
737 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
738 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
739 writel(val, pctrl->regs + g->intr_target_reg); in msm_gpio_irq_set_type()
746 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_set_type()
747 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
748 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
749 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
750 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
753 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
754 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
757 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
758 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
761 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
762 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
767 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
770 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
771 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
772 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
775 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
776 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
779 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
782 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
783 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
788 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
794 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_set_type()
797 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
827 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
842 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
843 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_handler()
844 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()