Lines Matching +full:gpio +full:- +full:out +full:- +full:pol
25 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/gpio.h>
36 #include "pinctrl-msm.h"
37 #include "../pinctrl-utils.h"
43 * struct msm_pinctrl - state for a pinctrl-msm device
80 return pctrl->soc->ngroups; in msm_get_groups_count()
88 return pctrl->soc->groups[group].name; in msm_get_group_name()
98 *pins = pctrl->soc->groups[group].pins; in msm_get_group_pins()
99 *num_pins = pctrl->soc->groups[group].npins; in msm_get_group_pins()
114 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
116 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
123 return pctrl->soc->nfunctions; in msm_get_functions_count()
131 return pctrl->soc->functions[function].name; in msm_get_function_name()
141 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
142 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
156 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
157 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
159 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
160 if (g->funcs[i] == function) in msm_pinmux_set_mux()
164 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
165 return -EINVAL; in msm_pinmux_set_mux()
167 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
169 val = readl(pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
171 val |= i << g->mux_bit; in msm_pinmux_set_mux()
172 writel(val, pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
174 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
198 *bit = g->pull_bit; in msm_config_reg()
202 *bit = g->drv_bit; in msm_config_reg()
207 *bit = g->oe_bit; in msm_config_reg()
211 return -ENOTSUPP; in msm_config_reg()
241 g = &pctrl->soc->groups[group]; in msm_config_group_get()
247 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_get()
254 return -EINVAL; in msm_config_group_get()
259 return -EINVAL; in msm_config_group_get()
263 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
264 return -ENOTSUPP; in msm_config_group_get()
267 return -EINVAL; in msm_config_group_get()
271 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
276 return -EINVAL; in msm_config_group_get()
284 return -EINVAL; in msm_config_group_get()
286 val = readl(pctrl->regs + g->io_reg); in msm_config_group_get()
287 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
292 return -EINVAL; in msm_config_group_get()
296 return -ENOTSUPP; in msm_config_group_get()
320 g = &pctrl->soc->groups[group]; in msm_config_group_set()
339 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
340 return -ENOTSUPP; in msm_config_group_set()
345 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
353 arg = -1; in msm_config_group_set()
355 arg = (arg / 2) - 1; in msm_config_group_set()
359 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
360 val = readl(pctrl->regs + g->io_reg); in msm_config_group_set()
362 val |= BIT(g->out_bit); in msm_config_group_set()
364 val &= ~BIT(g->out_bit); in msm_config_group_set()
365 writel(val, pctrl->regs + g->io_reg); in msm_config_group_set()
366 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
376 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
378 return -EINVAL; in msm_config_group_set()
381 /* Range-check user-supplied value */ in msm_config_group_set()
383 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
384 return -EINVAL; in msm_config_group_set()
387 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
388 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_set()
391 writel(val, pctrl->regs + g->ctl_reg); in msm_config_group_set()
392 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
411 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
413 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
415 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
416 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
417 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
419 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
431 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
433 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
435 val = readl(pctrl->regs + g->io_reg); in msm_gpio_direction_output()
437 val |= BIT(g->out_bit); in msm_gpio_direction_output()
439 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
440 writel(val, pctrl->regs + g->io_reg); in msm_gpio_direction_output()
442 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
443 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
444 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
446 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
457 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
459 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_get_direction()
462 return val & BIT(g->oe_bit) ? 0 : 1; in msm_gpio_get_direction()
471 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
473 val = readl(pctrl->regs + g->io_reg); in msm_gpio_get()
474 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
484 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
486 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
488 val = readl(pctrl->regs + g->io_reg); in msm_gpio_set()
490 val |= BIT(g->out_bit); in msm_gpio_set()
492 val &= ~BIT(g->out_bit); in msm_gpio_set()
493 writel(val, pctrl->regs + g->io_reg); in msm_gpio_set()
495 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
505 unsigned gpio) in msm_gpio_dbg_show_one() argument
532 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
533 ctl_reg = readl(pctrl->regs + g->ctl_reg); in msm_gpio_dbg_show_one()
534 io_reg = readl(pctrl->regs + g->io_reg); in msm_gpio_dbg_show_one()
536 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
537 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
538 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
539 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
542 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
544 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
546 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
547 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); in msm_gpio_dbg_show_one()
549 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
558 unsigned gpio = chip->base; in msm_gpio_dbg_show() local
561 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
562 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); in msm_gpio_dbg_show()
580 /* For dual-edge interrupts in software, since some hardware has no
584 * settings of both-edge irq lines to try and catch the next edge.
587 * - the status bit goes high, indicating that an edge was caught, or
588 * - the input value of the gpio doesn't change during the attempt.
593 * The do-loop tries to sledge-hammer closed the timing hole between
594 * the initial value-read and the polarity-write - if the line value changes
606 unsigned pol; in msm_gpio_update_dual_edge_pos() local
609 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
611 pol = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_update_dual_edge_pos()
612 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
613 writel(pol, pctrl->regs + g->intr_cfg_reg); in msm_gpio_update_dual_edge_pos()
615 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
616 intstat = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_update_dual_edge_pos()
619 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
620 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
632 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
634 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
636 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_mask()
642 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
651 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
658 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
660 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
661 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_mask()
663 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
665 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
676 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
678 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
680 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_unmask()
681 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
682 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
683 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_unmask()
685 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
687 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
698 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
700 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
702 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_ack()
703 if (g->intr_ack_high) in msm_gpio_irq_ack()
704 val |= BIT(g->intr_status_bit); in msm_gpio_irq_ack()
706 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_ack()
707 writel(val, pctrl->regs + g->intr_status_reg); in msm_gpio_irq_ack()
709 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
712 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
723 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
725 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
730 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
731 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
733 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
736 val = readl(pctrl->regs + g->intr_target_reg); in msm_gpio_irq_set_type()
737 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
738 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
739 writel(val, pctrl->regs + g->intr_target_reg); in msm_gpio_irq_set_type()
741 /* Update configuration for gpio. in msm_gpio_irq_set_type()
742 * RAW_STATUS_EN is left on for all gpio irqs. Due to the in msm_gpio_irq_set_type()
746 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_set_type()
747 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
748 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
749 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
750 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
753 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
754 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
757 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
758 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
761 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
762 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
767 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
770 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
771 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
772 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
775 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
776 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
779 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
782 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
783 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
788 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
794 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_set_type()
796 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
799 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
815 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_wake()
817 irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
819 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_wake()
841 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
842 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
843 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_handler()
844 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
845 irq_pin = irq_find_mapping(gc->irq.domain, i); in msm_gpio_irq_handler()
863 unsigned int max_gpios = pctrl->soc->ngpios; in msm_gpio_init_valid_mask()
867 len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0); in msm_gpio_init_valid_mask()
872 return -EINVAL; in msm_gpio_init_valid_mask()
876 return -ENOMEM; in msm_gpio_init_valid_mask()
878 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
880 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
881 goto out; in msm_gpio_init_valid_mask()
884 bitmap_zero(chip->valid_mask, max_gpios); in msm_gpio_init_valid_mask()
886 set_bit(tmp[i], chip->valid_mask); in msm_gpio_init_valid_mask()
888 out: in msm_gpio_init_valid_mask()
895 return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; in msm_gpio_needs_valid_mask()
902 unsigned ngpio = pctrl->soc->ngpios; in msm_gpio_init()
905 return -EINVAL; in msm_gpio_init()
907 chip = &pctrl->chip; in msm_gpio_init()
908 chip->base = -1; in msm_gpio_init()
909 chip->ngpio = ngpio; in msm_gpio_init()
910 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
911 chip->parent = pctrl->dev; in msm_gpio_init()
912 chip->owner = THIS_MODULE; in msm_gpio_init()
913 chip->of_node = pctrl->dev->of_node; in msm_gpio_init()
914 chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl); in msm_gpio_init()
916 pctrl->irq_chip.name = "msmgpio"; in msm_gpio_init()
917 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; in msm_gpio_init()
918 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; in msm_gpio_init()
919 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; in msm_gpio_init()
920 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; in msm_gpio_init()
921 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; in msm_gpio_init()
923 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
925 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
931 dev_err(pctrl->dev, "Failed to setup irq valid bits\n"); in msm_gpio_init()
932 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
937 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
938 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
943 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
946 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
947 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
948 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
950 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
951 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
957 &pctrl->irq_chip, in msm_gpio_init()
962 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); in msm_gpio_init()
963 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
964 return -ENOSYS; in msm_gpio_init()
967 gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, in msm_gpio_init()
978 writel(0, pctrl->regs + PS_HOLD_OFFSET); in msm_ps_hold_restart()
987 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); in msm_ps_hold_poweroff()
993 const struct msm_function *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
995 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
997 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
998 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
999 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1000 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1015 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1017 return -ENOMEM; in msm_pinctrl_probe()
1019 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1020 pctrl->soc = soc_data; in msm_pinctrl_probe()
1021 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1023 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1026 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1027 if (IS_ERR(pctrl->regs)) in msm_pinctrl_probe()
1028 return PTR_ERR(pctrl->regs); in msm_pinctrl_probe()
1032 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1033 if (pctrl->irq < 0) { in msm_pinctrl_probe()
1034 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); in msm_pinctrl_probe()
1035 return pctrl->irq; in msm_pinctrl_probe()
1038 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1039 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1040 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1041 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1042 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1043 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1044 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1046 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1047 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1048 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1049 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1058 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()
1068 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1070 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()