Lines Matching +full:irq +full:- +full:push +full:- +full:pull
20 #include <linux/pinctrl/pinconf-generic.h>
28 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
31 #include "../pinctrl-utils.h"
63 * struct pm8xxx_pin_data - dynamic configuration for a pin
65 * @irq: IRQ from the PMIC interrupt controller
69 * @open_drain: output buffer configured as open-drain (vs push-pull)
72 * @pull_up_strength: placeholder for selected pull up strength
73 * only used to configure bias when pull up is selected
74 * @output_strength: selector of output-strength
81 int irq; member
105 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0},
106 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0},
111 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
112 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true),
139 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_read_bank()
141 dev_err(pctrl->dev, "failed to select bank %d\n", bank); in pm8xxx_read_bank()
145 ret = regmap_read(pctrl->regmap, pin->reg, &val); in pm8xxx_read_bank()
147 dev_err(pctrl->dev, "failed to read register %d\n", bank); in pm8xxx_read_bank()
164 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_write_bank()
166 dev_err(pctrl->dev, "failed to write register\n"); in pm8xxx_write_bank()
175 return pctrl->npins; in pm8xxx_get_groups_count()
192 *pins = &pctrl->desc.pins[group].number; in pm8xxx_get_group_pins()
225 *num_groups = pctrl->npins; in pm8xxx_get_function_groups()
234 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; in pm8xxx_pinmux_set_mux()
237 pin->function = function; in pm8xxx_pinmux_set_mux()
238 val = pin->function << 1; in pm8xxx_pinmux_set_mux()
257 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_get()
263 if (pin->bias != PM8XXX_GPIO_BIAS_NP) in pm8xxx_pin_config_get()
264 return -EINVAL; in pm8xxx_pin_config_get()
268 if (pin->bias != PM8XXX_GPIO_BIAS_PD) in pm8xxx_pin_config_get()
269 return -EINVAL; in pm8xxx_pin_config_get()
273 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30) in pm8xxx_pin_config_get()
274 return -EINVAL; in pm8xxx_pin_config_get()
278 arg = pin->pull_up_strength; in pm8xxx_pin_config_get()
281 if (!pin->disable) in pm8xxx_pin_config_get()
282 return -EINVAL; in pm8xxx_pin_config_get()
286 if (pin->mode != PM8XXX_GPIO_MODE_INPUT) in pm8xxx_pin_config_get()
287 return -EINVAL; in pm8xxx_pin_config_get()
291 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) in pm8xxx_pin_config_get()
292 arg = pin->output_value; in pm8xxx_pin_config_get()
297 arg = pin->power_source; in pm8xxx_pin_config_get()
300 arg = pin->output_strength; in pm8xxx_pin_config_get()
303 if (pin->open_drain) in pm8xxx_pin_config_get()
304 return -EINVAL; in pm8xxx_pin_config_get()
308 if (!pin->open_drain) in pm8xxx_pin_config_get()
309 return -EINVAL; in pm8xxx_pin_config_get()
313 return -EINVAL; in pm8xxx_pin_config_get()
327 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_set()
340 pin->bias = PM8XXX_GPIO_BIAS_NP; in pm8xxx_pin_config_set()
342 pin->disable = 0; in pm8xxx_pin_config_set()
346 pin->bias = PM8XXX_GPIO_BIAS_PD; in pm8xxx_pin_config_set()
348 pin->disable = 0; in pm8xxx_pin_config_set()
353 dev_err(pctrl->dev, "invalid pull-up strength\n"); in pm8xxx_pin_config_set()
354 return -EINVAL; in pm8xxx_pin_config_set()
356 pin->pull_up_strength = arg; in pm8xxx_pin_config_set()
359 pin->bias = pin->pull_up_strength; in pm8xxx_pin_config_set()
361 pin->disable = 0; in pm8xxx_pin_config_set()
365 pin->disable = 1; in pm8xxx_pin_config_set()
369 pin->mode = PM8XXX_GPIO_MODE_INPUT; in pm8xxx_pin_config_set()
373 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; in pm8xxx_pin_config_set()
374 pin->output_value = !!arg; in pm8xxx_pin_config_set()
378 pin->power_source = arg; in pm8xxx_pin_config_set()
383 dev_err(pctrl->dev, "invalid drive strength\n"); in pm8xxx_pin_config_set()
384 return -EINVAL; in pm8xxx_pin_config_set()
386 pin->output_strength = arg; in pm8xxx_pin_config_set()
390 pin->open_drain = 0; in pm8xxx_pin_config_set()
394 pin->open_drain = 1; in pm8xxx_pin_config_set()
398 dev_err(pctrl->dev, in pm8xxx_pin_config_set()
401 return -EINVAL; in pm8xxx_pin_config_set()
406 val = pin->power_source << 1; in pm8xxx_pin_config_set()
412 val = pin->mode << 2; in pm8xxx_pin_config_set()
413 val |= pin->open_drain << 1; in pm8xxx_pin_config_set()
414 val |= pin->output_value; in pm8xxx_pin_config_set()
419 val = pin->bias << 1; in pm8xxx_pin_config_set()
424 val = pin->output_strength << 2; in pm8xxx_pin_config_set()
425 val |= pin->disable; in pm8xxx_pin_config_set()
430 val = pin->function << 1; in pm8xxx_pin_config_set()
436 if (!pin->inverted) in pm8xxx_pin_config_set()
462 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_direction_input()
465 pin->mode = PM8XXX_GPIO_MODE_INPUT; in pm8xxx_gpio_direction_input()
466 val = pin->mode << 2; in pm8xxx_gpio_direction_input()
478 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_direction_output()
481 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; in pm8xxx_gpio_direction_output()
482 pin->output_value = !!value; in pm8xxx_gpio_direction_output()
484 val = pin->mode << 2; in pm8xxx_gpio_direction_output()
485 val |= pin->open_drain << 1; in pm8xxx_gpio_direction_output()
486 val |= pin->output_value; in pm8xxx_gpio_direction_output()
496 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_get()
500 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) { in pm8xxx_gpio_get()
501 ret = pin->output_value; in pm8xxx_gpio_get()
503 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); in pm8xxx_gpio_get()
514 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_set()
517 pin->output_value = !!value; in pm8xxx_gpio_set()
519 val = pin->mode << 2; in pm8xxx_gpio_set()
520 val |= pin->open_drain << 1; in pm8xxx_gpio_set()
521 val |= pin->output_value; in pm8xxx_gpio_set()
530 if (chip->of_gpio_n_cells < 2) in pm8xxx_gpio_of_xlate()
531 return -EINVAL; in pm8xxx_gpio_of_xlate()
534 *flags = gpio_desc->args[1]; in pm8xxx_gpio_of_xlate()
536 return gpio_desc->args[0] - 1; in pm8xxx_gpio_of_xlate()
543 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_to_irq()
545 return pin->irq; in pm8xxx_gpio_to_irq()
558 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_dbg_show_one()
564 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", in pm8xxx_gpio_dbg_show_one()
565 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" in pm8xxx_gpio_dbg_show_one()
568 "push-pull", "open-drain" in pm8xxx_gpio_dbg_show_one()
574 seq_printf(s, " gpio%-2d:", offset + 1); in pm8xxx_gpio_dbg_show_one()
575 if (pin->disable) { in pm8xxx_gpio_dbg_show_one()
576 seq_puts(s, " ---"); in pm8xxx_gpio_dbg_show_one()
578 seq_printf(s, " %-4s", modes[pin->mode]); in pm8xxx_gpio_dbg_show_one()
579 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); in pm8xxx_gpio_dbg_show_one()
580 seq_printf(s, " VIN%d", pin->power_source); in pm8xxx_gpio_dbg_show_one()
581 seq_printf(s, " %-27s", biases[pin->bias]); in pm8xxx_gpio_dbg_show_one()
582 seq_printf(s, " %-10s", buffer_types[pin->open_drain]); in pm8xxx_gpio_dbg_show_one()
583 seq_printf(s, " %-4s", pin->output_value ? "high" : "low"); in pm8xxx_gpio_dbg_show_one()
584 seq_printf(s, " %-7s", strengths[pin->output_strength]); in pm8xxx_gpio_dbg_show_one()
585 if (pin->inverted) in pm8xxx_gpio_dbg_show_one()
592 unsigned gpio = chip->base; in pm8xxx_gpio_dbg_show()
595 for (i = 0; i < chip->ngpio; i++, gpio++) { in pm8xxx_gpio_dbg_show()
625 pin->power_source = (val >> 1) & 0x7; in pm8xxx_pin_populate()
631 pin->mode = (val >> 2) & 0x3; in pm8xxx_pin_populate()
632 pin->open_drain = !!(val & BIT(1)); in pm8xxx_pin_populate()
633 pin->output_value = val & BIT(0); in pm8xxx_pin_populate()
639 pin->bias = (val >> 1) & 0x7; in pm8xxx_pin_populate()
640 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) in pm8xxx_pin_populate()
641 pin->pull_up_strength = pin->bias; in pm8xxx_pin_populate()
643 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; in pm8xxx_pin_populate()
649 pin->output_strength = (val >> 2) & 0x3; in pm8xxx_pin_populate()
650 pin->disable = val & BIT(0); in pm8xxx_pin_populate()
656 pin->function = (val >> 1) & 0x7; in pm8xxx_pin_populate()
662 pin->inverted = !(val & BIT(3)); in pm8xxx_pin_populate()
668 { .compatible = "qcom,pm8018-gpio" },
669 { .compatible = "qcom,pm8038-gpio" },
670 { .compatible = "qcom,pm8058-gpio" },
671 { .compatible = "qcom,pm8917-gpio" },
672 { .compatible = "qcom,pm8921-gpio" },
673 { .compatible = "qcom,ssbi-gpio" },
686 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in pm8xxx_gpio_probe()
688 return -ENOMEM; in pm8xxx_gpio_probe()
690 pctrl->dev = &pdev->dev; in pm8xxx_gpio_probe()
693 return -EINVAL; in pm8xxx_gpio_probe()
696 pctrl->npins = npins; in pm8xxx_gpio_probe()
698 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); in pm8xxx_gpio_probe()
699 if (!pctrl->regmap) { in pm8xxx_gpio_probe()
700 dev_err(&pdev->dev, "parent regmap unavailable\n"); in pm8xxx_gpio_probe()
701 return -ENXIO; in pm8xxx_gpio_probe()
704 pctrl->desc = pm8xxx_pinctrl_desc; in pm8xxx_gpio_probe()
705 pctrl->desc.npins = pctrl->npins; in pm8xxx_gpio_probe()
707 pins = devm_kcalloc(&pdev->dev, in pm8xxx_gpio_probe()
708 pctrl->desc.npins, in pm8xxx_gpio_probe()
712 return -ENOMEM; in pm8xxx_gpio_probe()
714 pin_data = devm_kcalloc(&pdev->dev, in pm8xxx_gpio_probe()
715 pctrl->desc.npins, in pm8xxx_gpio_probe()
719 return -ENOMEM; in pm8xxx_gpio_probe()
721 for (i = 0; i < pctrl->desc.npins; i++) { in pm8xxx_gpio_probe()
723 pin_data[i].irq = platform_get_irq(pdev, i); in pm8xxx_gpio_probe()
724 if (pin_data[i].irq < 0) { in pm8xxx_gpio_probe()
725 dev_err(&pdev->dev, in pm8xxx_gpio_probe()
727 return pin_data[i].irq; in pm8xxx_gpio_probe()
738 pctrl->desc.pins = pins; in pm8xxx_gpio_probe()
740 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings); in pm8xxx_gpio_probe()
741 pctrl->desc.custom_params = pm8xxx_gpio_bindings; in pm8xxx_gpio_probe()
743 pctrl->desc.custom_conf_items = pm8xxx_conf_items; in pm8xxx_gpio_probe()
746 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in pm8xxx_gpio_probe()
747 if (IS_ERR(pctrl->pctrl)) { in pm8xxx_gpio_probe()
748 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); in pm8xxx_gpio_probe()
749 return PTR_ERR(pctrl->pctrl); in pm8xxx_gpio_probe()
752 pctrl->chip = pm8xxx_gpio_template; in pm8xxx_gpio_probe()
753 pctrl->chip.base = -1; in pm8xxx_gpio_probe()
754 pctrl->chip.parent = &pdev->dev; in pm8xxx_gpio_probe()
755 pctrl->chip.of_node = pdev->dev.of_node; in pm8xxx_gpio_probe()
756 pctrl->chip.of_gpio_n_cells = 2; in pm8xxx_gpio_probe()
757 pctrl->chip.label = dev_name(pctrl->dev); in pm8xxx_gpio_probe()
758 pctrl->chip.ngpio = pctrl->npins; in pm8xxx_gpio_probe()
759 ret = gpiochip_add_data(&pctrl->chip, pctrl); in pm8xxx_gpio_probe()
761 dev_err(&pdev->dev, "failed register gpiochip\n"); in pm8xxx_gpio_probe()
766 * For DeviceTree-supported systems, the gpio core checks the in pm8xxx_gpio_probe()
767 * pinctrl's device node for the "gpio-ranges" property. in pm8xxx_gpio_probe()
772 * files which don't set the "gpio-ranges" property or systems that in pm8xxx_gpio_probe()
775 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in pm8xxx_gpio_probe()
776 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), in pm8xxx_gpio_probe()
777 0, 0, pctrl->chip.ngpio); in pm8xxx_gpio_probe()
779 dev_err(pctrl->dev, "failed to add pin range\n"); in pm8xxx_gpio_probe()
786 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n"); in pm8xxx_gpio_probe()
791 gpiochip_remove(&pctrl->chip); in pm8xxx_gpio_probe()
800 gpiochip_remove(&pctrl->chip); in pm8xxx_gpio_remove()
807 .name = "qcom-ssbi-gpio",