Lines Matching +full:range +full:- +full:gpios
5 * Copyright (C) 2009 - 2012 Paul Mundt
44 return chip->pfc; in gpio_to_pfc()
51 int idx = sh_pfc_get_pin_index(chip->pfc, offset); in gpio_get_data_reg()
52 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; in gpio_get_data_reg()
54 *reg = &chip->regs[gpio_pin->dreg]; in gpio_get_data_reg()
55 *bit = gpio_pin->dbit; in gpio_get_data_reg()
61 phys_addr_t address = dreg->reg; in gpio_read_data_reg()
62 void __iomem *mem = address - chip->mem->phys + chip->mem->virt; in gpio_read_data_reg()
64 return sh_pfc_read_raw_reg(mem, dreg->reg_width); in gpio_read_data_reg()
70 phys_addr_t address = dreg->reg; in gpio_write_data_reg()
71 void __iomem *mem = address - chip->mem->phys + chip->mem->virt; in gpio_write_data_reg()
73 sh_pfc_write_raw_reg(mem, dreg->reg_width, value); in gpio_write_data_reg()
78 struct sh_pfc *pfc = chip->pfc; in gpio_setup_data_reg()
79 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; in gpio_setup_data_reg()
80 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; in gpio_setup_data_reg()
85 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { in gpio_setup_data_reg()
86 for (bit = 0; bit < dreg->reg_width; bit++) { in gpio_setup_data_reg()
87 if (dreg->enum_ids[bit] == pin->enum_id) { in gpio_setup_data_reg()
88 gpio_pin->dreg = i; in gpio_setup_data_reg()
89 gpio_pin->dbit = bit; in gpio_setup_data_reg()
100 struct sh_pfc *pfc = chip->pfc; in gpio_setup_data_regs()
107 for (i = 0; pfc->info->data_regs[i].reg_width; ++i) in gpio_setup_data_regs()
110 chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs), in gpio_setup_data_regs()
112 if (chip->regs == NULL) in gpio_setup_data_regs()
113 return -ENOMEM; in gpio_setup_data_regs()
115 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { in gpio_setup_data_regs()
116 chip->regs[i].info = dreg; in gpio_setup_data_regs()
117 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg); in gpio_setup_data_regs()
120 for (i = 0; i < pfc->info->nr_pins; i++) { in gpio_setup_data_regs()
121 if (pfc->info->pins[i].enum_id == 0) in gpio_setup_data_regs()
130 /* -----------------------------------------------------------------------------
131 * Pin GPIOs
139 if (idx < 0 || pfc->info->pins[idx].enum_id == 0) in gpio_pin_request()
140 return -EINVAL; in gpio_pin_request()
159 pos = reg->info->reg_width - (bit + 1); in gpio_pin_set_value()
162 reg->shadow |= BIT(pos); in gpio_pin_set_value()
164 reg->shadow &= ~BIT(pos); in gpio_pin_set_value()
166 gpio_write_data_reg(chip, reg->info, reg->shadow); in gpio_pin_set_value()
191 pos = reg->info->reg_width - (bit + 1); in gpio_pin_get()
193 return (gpio_read_data_reg(chip, reg->info) >> pos) & 1; in gpio_pin_get()
206 for (i = 0; i < pfc->info->gpio_irq_size; i++) { in gpio_pin_to_irq()
207 const short *gpios = pfc->info->gpio_irq[i].gpios; in gpio_pin_to_irq() local
209 for (k = 0; gpios[k] >= 0; k++) { in gpio_pin_to_irq()
210 if (gpios[k] == offset) in gpio_pin_to_irq()
218 return pfc->irqs[i]; in gpio_pin_to_irq()
223 struct sh_pfc *pfc = chip->pfc; in gpio_pin_setup()
224 struct gpio_chip *gc = &chip->gpio_chip; in gpio_pin_setup()
227 chip->pins = devm_kcalloc(pfc->dev, in gpio_pin_setup()
228 pfc->info->nr_pins, sizeof(*chip->pins), in gpio_pin_setup()
230 if (chip->pins == NULL) in gpio_pin_setup()
231 return -ENOMEM; in gpio_pin_setup()
237 gc->request = gpio_pin_request; in gpio_pin_setup()
238 gc->free = gpio_pin_free; in gpio_pin_setup()
239 gc->direction_input = gpio_pin_direction_input; in gpio_pin_setup()
240 gc->get = gpio_pin_get; in gpio_pin_setup()
241 gc->direction_output = gpio_pin_direction_output; in gpio_pin_setup()
242 gc->set = gpio_pin_set; in gpio_pin_setup()
243 gc->to_irq = gpio_pin_to_irq; in gpio_pin_setup()
245 gc->label = pfc->info->name; in gpio_pin_setup()
246 gc->parent = pfc->dev; in gpio_pin_setup()
247 gc->owner = THIS_MODULE; in gpio_pin_setup()
248 gc->base = 0; in gpio_pin_setup()
249 gc->ngpio = pfc->nr_gpio_pins; in gpio_pin_setup()
254 /* -----------------------------------------------------------------------------
255 * Function GPIOs
263 unsigned int mark = pfc->info->func_gpios[offset].enum_id; in gpio_function_request()
268 dev_notice(pfc->dev, in gpio_function_request()
275 return -EINVAL; in gpio_function_request()
277 spin_lock_irqsave(&pfc->lock, flags); in gpio_function_request()
279 spin_unlock_irqrestore(&pfc->lock, flags); in gpio_function_request()
286 struct sh_pfc *pfc = chip->pfc; in gpio_function_setup()
287 struct gpio_chip *gc = &chip->gpio_chip; in gpio_function_setup()
289 gc->request = gpio_function_request; in gpio_function_setup()
291 gc->label = pfc->info->name; in gpio_function_setup()
292 gc->owner = THIS_MODULE; in gpio_function_setup()
293 gc->base = pfc->nr_gpio_pins; in gpio_function_setup()
294 gc->ngpio = pfc->info->nr_func_gpios; in gpio_function_setup()
300 /* -----------------------------------------------------------------------------
311 chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); in sh_pfc_add_gpiochip()
313 return ERR_PTR(-ENOMEM); in sh_pfc_add_gpiochip()
315 chip->mem = mem; in sh_pfc_add_gpiochip()
316 chip->pfc = pfc; in sh_pfc_add_gpiochip()
322 ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip); in sh_pfc_add_gpiochip()
326 dev_info(pfc->dev, "%s handling gpio %u -> %u\n", in sh_pfc_add_gpiochip()
327 chip->gpio_chip.label, chip->gpio_chip.base, in sh_pfc_add_gpiochip()
328 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); in sh_pfc_add_gpiochip()
339 if (pfc->info->data_regs == NULL) in sh_pfc_register_gpiochip()
345 * GPIOs. in sh_pfc_register_gpiochip()
347 address = pfc->info->data_regs[0].reg; in sh_pfc_register_gpiochip()
348 for (i = 0; i < pfc->num_windows; ++i) { in sh_pfc_register_gpiochip()
349 struct sh_pfc_window *window = &pfc->windows[i]; in sh_pfc_register_gpiochip()
351 if (address >= window->phys && in sh_pfc_register_gpiochip()
352 address < window->phys + window->size) in sh_pfc_register_gpiochip()
356 if (i == pfc->num_windows) in sh_pfc_register_gpiochip()
360 if (pfc->num_irqs != pfc->info->gpio_irq_size) { in sh_pfc_register_gpiochip()
361 dev_err(pfc->dev, "invalid number of IRQ resources\n"); in sh_pfc_register_gpiochip()
362 return -EINVAL; in sh_pfc_register_gpiochip()
365 /* Register the real GPIOs chip. */ in sh_pfc_register_gpiochip()
366 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]); in sh_pfc_register_gpiochip()
370 pfc->gpio = chip; in sh_pfc_register_gpiochip()
372 if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node) in sh_pfc_register_gpiochip()
379 * ports by stopping at the first range that contains such a in sh_pfc_register_gpiochip()
382 for (i = 0; i < pfc->nr_ranges; ++i) { in sh_pfc_register_gpiochip()
383 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; in sh_pfc_register_gpiochip() local
386 if (range->start >= pfc->nr_gpio_pins) in sh_pfc_register_gpiochip()
389 ret = gpiochip_add_pin_range(&chip->gpio_chip, in sh_pfc_register_gpiochip()
390 dev_name(pfc->dev), range->start, range->start, in sh_pfc_register_gpiochip()
391 range->end - range->start + 1); in sh_pfc_register_gpiochip()
396 /* Register the function GPIOs chip. */ in sh_pfc_register_gpiochip()
397 if (pfc->info->nr_func_gpios == 0) in sh_pfc_register_gpiochip()