Lines Matching +full:lock +full:- +full:offset
9 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
33 #include "pinctrl-sirf.h"
35 #define DRIVER_NAME "pinmux-sirf"
40 spinlock_t lock; member
46 spinlock_t lock; member
74 struct seq_file *s, unsigned offset) in sirfsoc_pin_dbg_show() argument
107 dev_err(spmx->dev, "No child nodes passed via DT\n"); in sirfsoc_dt_node_to_map()
108 return -ENODEV; in sirfsoc_dt_node_to_map()
113 return -ENOMEM; in sirfsoc_dt_node_to_map()
154 const struct sirfsoc_muxmask *mask = mux->muxmask; in sirfsoc_pinmux_endisable()
156 for (i = 0; i < mux->muxmask_counts; i++) { in sirfsoc_pinmux_endisable()
158 muxval = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_endisable()
164 writel(muxval, spmx->gpio_virtbase + in sirfsoc_pinmux_endisable()
168 if (mux->funcmask && enable) { in sirfsoc_pinmux_endisable()
172 readl(spmx->rsc_virtbase + mux->ctrlreg); in sirfsoc_pinmux_endisable()
174 (func_en_val & ~mux->funcmask) | (mux->funcval); in sirfsoc_pinmux_endisable()
175 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); in sirfsoc_pinmux_endisable()
213 struct pinctrl_gpio_range *range, unsigned offset) in sirfsoc_pinmux_request_gpio() argument
217 int group = range->id; in sirfsoc_pinmux_request_gpio()
223 muxval = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_request_gpio()
225 muxval = muxval | (1 << (offset - range->pin_base)); in sirfsoc_pinmux_request_gpio()
226 writel(muxval, spmx->gpio_virtbase + in sirfsoc_pinmux_request_gpio()
250 { .compatible = "sirf,prima2-rsc" }, in sirfsoc_rsc_of_iomap()
266 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) in sirfsoc_gpio_of_xlate()
267 return -EINVAL; in sirfsoc_gpio_of_xlate()
270 *flags = gpiospec->args[1]; in sirfsoc_gpio_of_xlate()
272 return gpiospec->args[0]; in sirfsoc_gpio_of_xlate()
276 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
277 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
285 struct device_node *np = pdev->dev.of_node; in sirfsoc_pinmux_probe()
289 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); in sirfsoc_pinmux_probe()
291 return -ENOMEM; in sirfsoc_pinmux_probe()
293 spmx->dev = &pdev->dev; in sirfsoc_pinmux_probe()
297 spmx->gpio_virtbase = of_iomap(np, 0); in sirfsoc_pinmux_probe()
298 if (!spmx->gpio_virtbase) { in sirfsoc_pinmux_probe()
299 dev_err(&pdev->dev, "can't map gpio registers\n"); in sirfsoc_pinmux_probe()
300 return -ENOMEM; in sirfsoc_pinmux_probe()
303 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); in sirfsoc_pinmux_probe()
304 if (!spmx->rsc_virtbase) { in sirfsoc_pinmux_probe()
305 ret = -ENOMEM; in sirfsoc_pinmux_probe()
306 dev_err(&pdev->dev, "can't map rsc registers\n"); in sirfsoc_pinmux_probe()
310 pdata = of_match_node(pinmux_ids, np)->data; in sirfsoc_pinmux_probe()
311 sirfsoc_pin_groups = pdata->grps; in sirfsoc_pinmux_probe()
312 sirfsoc_pingrp_cnt = pdata->grps_cnt; in sirfsoc_pinmux_probe()
313 sirfsoc_pmx_functions = pdata->funcs; in sirfsoc_pinmux_probe()
314 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; in sirfsoc_pinmux_probe()
315 sirfsoc_pinmux_desc.pins = pdata->pads; in sirfsoc_pinmux_probe()
316 sirfsoc_pinmux_desc.npins = pdata->pads_cnt; in sirfsoc_pinmux_probe()
320 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); in sirfsoc_pinmux_probe()
321 if (IS_ERR(spmx->pmx)) { in sirfsoc_pinmux_probe()
322 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); in sirfsoc_pinmux_probe()
323 ret = PTR_ERR(spmx->pmx); in sirfsoc_pinmux_probe()
327 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); in sirfsoc_pinmux_probe()
332 iounmap(spmx->rsc_virtbase); in sirfsoc_pinmux_probe()
334 iounmap(spmx->gpio_virtbase); in sirfsoc_pinmux_probe()
346 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_suspend_noirq()
349 spmx->ints_regs[i] = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_suspend_noirq()
351 spmx->paden_regs[i] = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_suspend_noirq()
354 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); in sirfsoc_pinmux_suspend_noirq()
357 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); in sirfsoc_pinmux_suspend_noirq()
369 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + in sirfsoc_pinmux_resume_noirq()
372 writel(spmx->ints_regs[i], spmx->gpio_virtbase + in sirfsoc_pinmux_resume_noirq()
374 writel(spmx->paden_regs[i], spmx->gpio_virtbase + in sirfsoc_pinmux_resume_noirq()
377 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); in sirfsoc_pinmux_resume_noirq()
380 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); in sirfsoc_pinmux_resume_noirq()
411 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) in sirfsoc_gpio_to_bank() argument
413 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE]; in sirfsoc_gpio_to_bank()
416 static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) in sirfsoc_gpio_to_bankoff() argument
418 return offset % SIRFSOC_GPIO_BANK_SIZE; in sirfsoc_gpio_to_bankoff()
425 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); in sirfsoc_gpio_irq_ack()
426 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); in sirfsoc_gpio_irq_ack()
427 u32 val, offset; in sirfsoc_gpio_irq_ack() local
430 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in sirfsoc_gpio_irq_ack()
432 spin_lock_irqsave(&sgpio->lock, flags); in sirfsoc_gpio_irq_ack()
434 val = readl(sgpio->chip.regs + offset); in sirfsoc_gpio_irq_ack()
436 writel(val, sgpio->chip.regs + offset); in sirfsoc_gpio_irq_ack()
438 spin_unlock_irqrestore(&sgpio->lock, flags); in sirfsoc_gpio_irq_ack()
445 u32 val, offset; in __sirfsoc_gpio_irq_mask() local
448 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in __sirfsoc_gpio_irq_mask()
450 spin_lock_irqsave(&sgpio->lock, flags); in __sirfsoc_gpio_irq_mask()
452 val = readl(sgpio->chip.regs + offset); in __sirfsoc_gpio_irq_mask()
455 writel(val, sgpio->chip.regs + offset); in __sirfsoc_gpio_irq_mask()
457 spin_unlock_irqrestore(&sgpio->lock, flags); in __sirfsoc_gpio_irq_mask()
464 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); in sirfsoc_gpio_irq_mask()
466 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); in sirfsoc_gpio_irq_mask()
473 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); in sirfsoc_gpio_irq_unmask()
474 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); in sirfsoc_gpio_irq_unmask()
475 u32 val, offset; in sirfsoc_gpio_irq_unmask() local
478 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in sirfsoc_gpio_irq_unmask()
480 spin_lock_irqsave(&sgpio->lock, flags); in sirfsoc_gpio_irq_unmask()
482 val = readl(sgpio->chip.regs + offset); in sirfsoc_gpio_irq_unmask()
485 writel(val, sgpio->chip.regs + offset); in sirfsoc_gpio_irq_unmask()
487 spin_unlock_irqrestore(&sgpio->lock, flags); in sirfsoc_gpio_irq_unmask()
494 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); in sirfsoc_gpio_irq_type()
495 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); in sirfsoc_gpio_irq_type()
496 u32 val, offset; in sirfsoc_gpio_irq_type() local
499 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in sirfsoc_gpio_irq_type()
501 spin_lock_irqsave(&sgpio->lock, flags); in sirfsoc_gpio_irq_type()
503 val = readl(sgpio->chip.regs + offset); in sirfsoc_gpio_irq_type()
536 writel(val, sgpio->chip.regs + offset); in sirfsoc_gpio_irq_type()
538 spin_unlock_irqrestore(&sgpio->lock, flags); in sirfsoc_gpio_irq_type()
544 .name = "sirf-gpio-irq",
563 bank = &sgpio->sgpio_bank[i]; in sirfsoc_gpio_handle_irq()
564 if (bank->parent_irq == irq) in sirfsoc_gpio_handle_irq()
571 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); in sirfsoc_gpio_handle_irq()
575 __func__, bank->id, status); in sirfsoc_gpio_handle_irq()
581 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); in sirfsoc_gpio_handle_irq()
589 __func__, bank->id, idx); in sirfsoc_gpio_handle_irq()
590 generic_handle_irq(irq_find_mapping(gc->irq.domain, idx + in sirfsoc_gpio_handle_irq()
591 bank->id * SIRFSOC_GPIO_BANK_SIZE)); in sirfsoc_gpio_handle_irq()
606 val = readl(sgpio->chip.regs + ctrl_offset); in sirfsoc_gpio_set_input()
608 writel(val, sgpio->chip.regs + ctrl_offset); in sirfsoc_gpio_set_input()
611 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) in sirfsoc_gpio_request() argument
614 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); in sirfsoc_gpio_request()
617 if (pinctrl_gpio_request(chip->base + offset)) in sirfsoc_gpio_request()
618 return -ENODEV; in sirfsoc_gpio_request()
620 spin_lock_irqsave(&bank->lock, flags); in sirfsoc_gpio_request()
626 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); in sirfsoc_gpio_request()
627 __sirfsoc_gpio_irq_mask(sgpio, bank, offset); in sirfsoc_gpio_request()
629 spin_unlock_irqrestore(&bank->lock, flags); in sirfsoc_gpio_request()
634 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) in sirfsoc_gpio_free() argument
637 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); in sirfsoc_gpio_free()
640 spin_lock_irqsave(&bank->lock, flags); in sirfsoc_gpio_free()
642 __sirfsoc_gpio_irq_mask(sgpio, bank, offset); in sirfsoc_gpio_free()
643 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); in sirfsoc_gpio_free()
645 spin_unlock_irqrestore(&bank->lock, flags); in sirfsoc_gpio_free()
647 pinctrl_gpio_free(chip->base + offset); in sirfsoc_gpio_free()
656 unsigned offset; in sirfsoc_gpio_direction_input() local
658 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in sirfsoc_gpio_direction_input()
660 spin_lock_irqsave(&bank->lock, flags); in sirfsoc_gpio_direction_input()
662 sirfsoc_gpio_set_input(sgpio, offset); in sirfsoc_gpio_direction_input()
664 spin_unlock_irqrestore(&bank->lock, flags); in sirfsoc_gpio_direction_input()
671 unsigned offset, in sirfsoc_gpio_set_output() argument
677 spin_lock_irqsave(&bank->lock, flags); in sirfsoc_gpio_set_output()
679 out_ctrl = readl(sgpio->chip.regs + offset); in sirfsoc_gpio_set_output()
687 writel(out_ctrl, sgpio->chip.regs + offset); in sirfsoc_gpio_set_output()
689 spin_unlock_irqrestore(&bank->lock, flags); in sirfsoc_gpio_set_output()
698 u32 offset; in sirfsoc_gpio_direction_output() local
701 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); in sirfsoc_gpio_direction_output()
703 spin_lock_irqsave(&sgpio->lock, flags); in sirfsoc_gpio_direction_output()
705 sirfsoc_gpio_set_output(sgpio, bank, offset, value); in sirfsoc_gpio_direction_output()
707 spin_unlock_irqrestore(&sgpio->lock, flags); in sirfsoc_gpio_direction_output()
712 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) in sirfsoc_gpio_get_value() argument
715 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); in sirfsoc_gpio_get_value()
719 spin_lock_irqsave(&bank->lock, flags); in sirfsoc_gpio_get_value()
721 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); in sirfsoc_gpio_get_value()
723 spin_unlock_irqrestore(&bank->lock, flags); in sirfsoc_gpio_get_value()
728 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, in sirfsoc_gpio_set_value() argument
732 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); in sirfsoc_gpio_set_value()
736 spin_lock_irqsave(&bank->lock, flags); in sirfsoc_gpio_set_value()
738 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); in sirfsoc_gpio_set_value()
743 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); in sirfsoc_gpio_set_value()
745 spin_unlock_irqrestore(&bank->lock, flags); in sirfsoc_gpio_set_value()
756 u32 offset = SIRFSOC_GPIO_CTRL(i, n); in sirfsoc_gpio_set_pullup() local
757 u32 val = readl(sgpio->chip.regs + offset); in sirfsoc_gpio_set_pullup()
760 writel(val, sgpio->chip.regs + offset); in sirfsoc_gpio_set_pullup()
773 u32 offset = SIRFSOC_GPIO_CTRL(i, n); in sirfsoc_gpio_set_pulldown() local
774 u32 val = readl(sgpio->chip.regs + offset); in sirfsoc_gpio_set_pulldown()
777 writel(val, sgpio->chip.regs + offset); in sirfsoc_gpio_set_pulldown()
794 return -ENODEV; in sirfsoc_gpio_probe()
796 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); in sirfsoc_gpio_probe()
798 return -ENOMEM; in sirfsoc_gpio_probe()
799 spin_lock_init(&sgpio->lock); in sirfsoc_gpio_probe()
803 return -ENOMEM; in sirfsoc_gpio_probe()
805 sgpio->chip.gc.request = sirfsoc_gpio_request; in sirfsoc_gpio_probe()
806 sgpio->chip.gc.free = sirfsoc_gpio_free; in sirfsoc_gpio_probe()
807 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; in sirfsoc_gpio_probe()
808 sgpio->chip.gc.get = sirfsoc_gpio_get_value; in sirfsoc_gpio_probe()
809 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; in sirfsoc_gpio_probe()
810 sgpio->chip.gc.set = sirfsoc_gpio_set_value; in sirfsoc_gpio_probe()
811 sgpio->chip.gc.base = 0; in sirfsoc_gpio_probe()
812 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; in sirfsoc_gpio_probe()
813 sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np); in sirfsoc_gpio_probe()
814 sgpio->chip.gc.of_node = np; in sirfsoc_gpio_probe()
815 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; in sirfsoc_gpio_probe()
816 sgpio->chip.gc.of_gpio_n_cells = 2; in sirfsoc_gpio_probe()
817 sgpio->chip.gc.parent = &pdev->dev; in sirfsoc_gpio_probe()
818 sgpio->chip.regs = regs; in sirfsoc_gpio_probe()
820 err = gpiochip_add_data(&sgpio->chip.gc, sgpio); in sirfsoc_gpio_probe()
822 dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n", in sirfsoc_gpio_probe()
827 err = gpiochip_irqchip_add(&sgpio->chip.gc, in sirfsoc_gpio_probe()
832 dev_err(&pdev->dev, in sirfsoc_gpio_probe()
838 bank = &sgpio->sgpio_bank[i]; in sirfsoc_gpio_probe()
839 spin_lock_init(&bank->lock); in sirfsoc_gpio_probe()
840 bank->parent_irq = platform_get_irq(pdev, i); in sirfsoc_gpio_probe()
841 if (bank->parent_irq < 0) { in sirfsoc_gpio_probe()
842 err = bank->parent_irq; in sirfsoc_gpio_probe()
846 gpiochip_set_chained_irqchip(&sgpio->chip.gc, in sirfsoc_gpio_probe()
848 bank->parent_irq, in sirfsoc_gpio_probe()
852 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), in sirfsoc_gpio_probe()
855 dev_err(&pdev->dev, in sirfsoc_gpio_probe()
872 gpiochip_remove(&sgpio->chip.gc); in sirfsoc_gpio_probe()
886 return -ENODEV; in sirfsoc_gpio_init()