Lines Matching full:bank
131 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, in __stm32_gpio_set() argument
137 clk_enable(bank->clk); in __stm32_gpio_set()
139 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
141 clk_disable(bank->clk); in __stm32_gpio_set()
146 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_request() local
147 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
149 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
167 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get() local
170 clk_enable(bank->clk); in stm32_gpio_get()
172 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
174 clk_disable(bank->clk); in stm32_gpio_get()
181 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_set() local
183 __stm32_gpio_set(bank, offset, value); in stm32_gpio_set()
194 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_direction_output() local
196 __stm32_gpio_set(bank, offset, value); in stm32_gpio_direction_output()
205 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_to_irq() local
208 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
218 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get_direction() local
223 stm32_pmx_get_mode(bank, pin, &mode, &alt); in stm32_gpio_get_direction()
247 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources() local
248 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources()
251 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
255 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
267 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources() local
269 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
301 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate() local
302 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate()
304 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
312 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc() local
324 bank); in stm32_gpio_domain_alloc()
582 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, in stm32_pmx_set_mode() argument
590 clk_enable(bank->clk); in stm32_pmx_set_mode()
591 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
593 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
596 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
598 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
601 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
603 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
604 clk_disable(bank->clk); in stm32_pmx_set_mode()
607 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, in stm32_pmx_get_mode() argument
615 clk_enable(bank->clk); in stm32_pmx_get_mode()
616 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
618 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
622 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
626 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
627 clk_disable(bank->clk); in stm32_pmx_get_mode()
638 struct stm32_gpio_bank *bank; in stm32_pmx_set_mux() local
655 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
661 stm32_pmx_set_mode(bank, pin, mode, alt); in stm32_pmx_set_mux()
670 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction() local
673 stm32_pmx_set_mode(bank, pin, !input, 0); in stm32_pmx_gpio_set_direction()
689 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, in stm32_pconf_set_driving() argument
695 clk_enable(bank->clk); in stm32_pconf_set_driving()
696 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
698 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
701 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
703 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
704 clk_disable(bank->clk); in stm32_pconf_set_driving()
707 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, in stm32_pconf_get_driving() argument
713 clk_enable(bank->clk); in stm32_pconf_get_driving()
714 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
716 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
719 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
720 clk_disable(bank->clk); in stm32_pconf_get_driving()
725 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, in stm32_pconf_set_speed() argument
731 clk_enable(bank->clk); in stm32_pconf_set_speed()
732 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
734 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
737 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
739 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
740 clk_disable(bank->clk); in stm32_pconf_set_speed()
743 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, in stm32_pconf_get_speed() argument
749 clk_enable(bank->clk); in stm32_pconf_get_speed()
750 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
752 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
755 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
756 clk_disable(bank->clk); in stm32_pconf_get_speed()
761 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, in stm32_pconf_set_bias() argument
767 clk_enable(bank->clk); in stm32_pconf_set_bias()
768 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
770 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
773 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
775 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
776 clk_disable(bank->clk); in stm32_pconf_set_bias()
779 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, in stm32_pconf_get_bias() argument
785 clk_enable(bank->clk); in stm32_pconf_get_bias()
786 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
788 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
791 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
792 clk_disable(bank->clk); in stm32_pconf_get_bias()
797 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, in stm32_pconf_get() argument
803 clk_enable(bank->clk); in stm32_pconf_get()
804 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
807 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
810 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
813 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
814 clk_disable(bank->clk); in stm32_pconf_get()
825 struct stm32_gpio_bank *bank; in stm32_pconf_parse_conf() local
834 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
839 stm32_pconf_set_driving(bank, offset, 0); in stm32_pconf_parse_conf()
842 stm32_pconf_set_driving(bank, offset, 1); in stm32_pconf_parse_conf()
845 stm32_pconf_set_speed(bank, offset, arg); in stm32_pconf_parse_conf()
848 stm32_pconf_set_bias(bank, offset, 0); in stm32_pconf_parse_conf()
851 stm32_pconf_set_bias(bank, offset, 1); in stm32_pconf_parse_conf()
854 stm32_pconf_set_bias(bank, offset, 2); in stm32_pconf_parse_conf()
857 __stm32_gpio_set(bank, offset, arg); in stm32_pconf_parse_conf()
903 struct stm32_gpio_bank *bank; in stm32_pconf_dbg_show() local
918 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
921 stm32_pmx_get_mode(bank, offset, &mode, &alt); in stm32_pconf_dbg_show()
922 bias = stm32_pconf_get_bias(bank, offset); in stm32_pconf_dbg_show()
929 val = stm32_pconf_get(bank, offset, true); in stm32_pconf_dbg_show()
937 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
938 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
939 val = stm32_pconf_get(bank, offset, false); in stm32_pconf_dbg_show()
949 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
950 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
973 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank() local
975 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
990 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
991 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
992 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
994 bank->clk = of_clk_get_by_name(np, NULL); in stm32_gpiolib_register_bank()
995 if (IS_ERR(bank->clk)) { in stm32_gpiolib_register_bank()
996 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); in stm32_gpiolib_register_bank()
997 return PTR_ERR(bank->clk); in stm32_gpiolib_register_bank()
1000 err = clk_prepare(bank->clk); in stm32_gpiolib_register_bank()
1006 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1008 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1012 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1015 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1016 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1021 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1026 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) in stm32_gpiolib_register_bank()
1029 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1031 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1032 bank->gpio_chip.of_node = np; in stm32_gpiolib_register_bank()
1033 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1034 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1035 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1036 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1039 bank->fwnode = of_node_to_fwnode(np); in stm32_gpiolib_register_bank()
1041 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, in stm32_gpiolib_register_bank()
1042 STM32_GPIO_IRQ_LINE, bank->fwnode, in stm32_gpiolib_register_bank()
1043 &stm32_gpio_domain_ops, bank); in stm32_gpiolib_register_bank()
1045 if (!bank->domain) in stm32_gpiolib_register_bank()
1048 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1054 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1213 dev_err(dev, "at least one GPIO bank is required\n"); in stm32_pctl_probe()