Lines Matching +full:bank +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/pinctrl/pinconf-generic.h>
32 #include "../pinctrl-utils.h"
33 #include "pinctrl-stm32.h"
64 const char *name; member
121 return function - 1; in stm32_gpio_get_alt()
131 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, in __stm32_gpio_set() argument
137 clk_enable(bank->clk); in __stm32_gpio_set()
139 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
141 clk_disable(bank->clk); in __stm32_gpio_set()
146 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_request() local
147 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
149 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
151 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); in stm32_gpio_request()
153 dev_err(pctl->dev, "pin %d not in range.\n", pin); in stm32_gpio_request()
154 return -EINVAL; in stm32_gpio_request()
157 return pinctrl_gpio_request(chip->base + offset); in stm32_gpio_request()
162 pinctrl_gpio_free(chip->base + offset); in stm32_gpio_free()
167 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get() local
170 clk_enable(bank->clk); in stm32_gpio_get()
172 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
174 clk_disable(bank->clk); in stm32_gpio_get()
181 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_set() local
183 __stm32_gpio_set(bank, offset, value); in stm32_gpio_set()
188 return pinctrl_gpio_direction_input(chip->base + offset); in stm32_gpio_direction_input()
194 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_direction_output() local
196 __stm32_gpio_set(bank, offset, value); in stm32_gpio_direction_output()
197 pinctrl_gpio_direction_output(chip->base + offset); in stm32_gpio_direction_output()
205 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_to_irq() local
208 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
218 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get_direction() local
223 stm32_pmx_get_mode(bank, pin, &mode, &alt); in stm32_gpio_get_direction()
229 ret = -EINVAL; in stm32_gpio_get_direction()
247 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources() local
248 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources()
251 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
255 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
257 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", in stm32_gpio_irq_request_resources()
258 irq_data->hwirq); in stm32_gpio_irq_request_resources()
267 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources() local
269 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
273 .name = "stm32gpio",
289 if ((fwspec->param_count != 2) || in stm32_gpio_domain_translate()
290 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) in stm32_gpio_domain_translate()
291 return -EINVAL; in stm32_gpio_domain_translate()
293 *hwirq = fwspec->param[0]; in stm32_gpio_domain_translate()
294 *type = fwspec->param[1]; in stm32_gpio_domain_translate()
301 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate() local
302 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate()
304 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
312 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc() local
317 hwirq = fwspec->param[0]; in stm32_gpio_domain_alloc()
318 parent_fwspec.fwnode = d->parent->fwnode; in stm32_gpio_domain_alloc()
320 parent_fwspec.param[0] = fwspec->param[0]; in stm32_gpio_domain_alloc()
321 parent_fwspec.param[1] = fwspec->param[1]; in stm32_gpio_domain_alloc()
324 bank); in stm32_gpio_domain_alloc()
342 for (i = 0; i < pctl->ngroups; i++) { in stm32_pctrl_find_group_by_pin()
343 struct stm32_pinctrl_group *grp = pctl->groups + i; in stm32_pctrl_find_group_by_pin()
345 if (grp->pin == pin) in stm32_pctrl_find_group_by_pin()
357 for (i = 0; i < pctl->match_data->npins; i++) { in stm32_pctrl_is_function_valid()
358 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; in stm32_pctrl_is_function_valid()
359 const struct stm32_desc_function *func = pin->functions; in stm32_pctrl_is_function_valid()
361 if (pin->pin.number != pin_num) in stm32_pctrl_is_function_valid()
364 while (func && func->name) { in stm32_pctrl_is_function_valid()
365 if (func->num == fnum) in stm32_pctrl_is_function_valid()
382 return -ENOSPC; in stm32_pctrl_dt_node_to_map_func()
385 (*map)[*num_maps].data.mux.group = grp->name; in stm32_pctrl_dt_node_to_map_func()
388 dev_err(pctl->dev, "invalid function %d on pin %d .\n", in stm32_pctrl_dt_node_to_map_func()
390 return -EINVAL; in stm32_pctrl_dt_node_to_map_func()
419 dev_err(pctl->dev, "missing pins property in node %s .\n", in stm32_pctrl_dt_subnode_to_map()
420 node->name); in stm32_pctrl_dt_subnode_to_map()
421 return -EINVAL; in stm32_pctrl_dt_subnode_to_map()
432 num_pins = pins->length / sizeof(u32); in stm32_pctrl_dt_subnode_to_map()
441 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
462 dev_err(pctl->dev, "invalid function.\n"); in stm32_pctrl_dt_subnode_to_map()
463 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
469 dev_err(pctl->dev, "unable to match pin %d to group\n", in stm32_pctrl_dt_subnode_to_map()
471 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
482 reserved_maps, num_maps, grp->name, in stm32_pctrl_dt_subnode_to_map()
523 return pctl->ngroups; in stm32_pctrl_get_groups_count()
531 return pctl->groups[group].name; in stm32_pctrl_get_group_name()
541 *pins = (unsigned *)&pctl->groups[group].pin; in stm32_pctrl_get_group_pins()
576 *groups = pctl->grp_names; in stm32_pmx_get_func_groups()
577 *num_groups = pctl->ngroups; in stm32_pmx_get_func_groups()
582 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, in stm32_pmx_set_mode() argument
590 clk_enable(bank->clk); in stm32_pmx_set_mode()
591 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
593 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
596 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
598 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
601 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
603 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
604 clk_disable(bank->clk); in stm32_pmx_set_mode()
607 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, in stm32_pmx_get_mode() argument
615 clk_enable(bank->clk); in stm32_pmx_get_mode()
616 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
618 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
622 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
626 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
627 clk_disable(bank->clk); in stm32_pmx_get_mode()
636 struct stm32_pinctrl_group *g = pctl->groups + group; in stm32_pmx_set_mux()
638 struct stm32_gpio_bank *bank; in stm32_pmx_set_mux() local
642 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); in stm32_pmx_set_mux()
644 dev_err(pctl->dev, "invalid function %d on group %d .\n", in stm32_pmx_set_mux()
646 return -EINVAL; in stm32_pmx_set_mux()
649 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); in stm32_pmx_set_mux()
651 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_set_mux()
652 return -EINVAL; in stm32_pmx_set_mux()
655 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
656 pin = stm32_gpio_pin(g->pin); in stm32_pmx_set_mux()
661 stm32_pmx_set_mode(bank, pin, mode, alt); in stm32_pmx_set_mux()
670 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction() local
673 stm32_pmx_set_mode(bank, pin, !input, 0); in stm32_pmx_gpio_set_direction()
689 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, in stm32_pconf_set_driving() argument
695 clk_enable(bank->clk); in stm32_pconf_set_driving()
696 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
698 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
701 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
703 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
704 clk_disable(bank->clk); in stm32_pconf_set_driving()
707 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, in stm32_pconf_get_driving() argument
713 clk_enable(bank->clk); in stm32_pconf_get_driving()
714 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
716 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
719 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
720 clk_disable(bank->clk); in stm32_pconf_get_driving()
725 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, in stm32_pconf_set_speed() argument
731 clk_enable(bank->clk); in stm32_pconf_set_speed()
732 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
734 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
737 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
739 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
740 clk_disable(bank->clk); in stm32_pconf_set_speed()
743 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, in stm32_pconf_get_speed() argument
749 clk_enable(bank->clk); in stm32_pconf_get_speed()
750 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
752 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
755 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
756 clk_disable(bank->clk); in stm32_pconf_get_speed()
761 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, in stm32_pconf_set_bias() argument
767 clk_enable(bank->clk); in stm32_pconf_set_bias()
768 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
770 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
773 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
775 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
776 clk_disable(bank->clk); in stm32_pconf_set_bias()
779 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, in stm32_pconf_get_bias() argument
785 clk_enable(bank->clk); in stm32_pconf_get_bias()
786 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
788 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
791 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
792 clk_disable(bank->clk); in stm32_pconf_get_bias()
797 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, in stm32_pconf_get() argument
803 clk_enable(bank->clk); in stm32_pconf_get()
804 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
807 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
810 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
813 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
814 clk_disable(bank->clk); in stm32_pconf_get()
825 struct stm32_gpio_bank *bank; in stm32_pconf_parse_conf() local
830 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pconf_parse_conf()
831 return -EINVAL; in stm32_pconf_parse_conf()
834 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
839 stm32_pconf_set_driving(bank, offset, 0); in stm32_pconf_parse_conf()
842 stm32_pconf_set_driving(bank, offset, 1); in stm32_pconf_parse_conf()
845 stm32_pconf_set_speed(bank, offset, arg); in stm32_pconf_parse_conf()
848 stm32_pconf_set_bias(bank, offset, 0); in stm32_pconf_parse_conf()
851 stm32_pconf_set_bias(bank, offset, 1); in stm32_pconf_parse_conf()
854 stm32_pconf_set_bias(bank, offset, 2); in stm32_pconf_parse_conf()
857 __stm32_gpio_set(bank, offset, arg); in stm32_pconf_parse_conf()
861 ret = -EINVAL; in stm32_pconf_parse_conf()
873 *config = pctl->groups[group].config; in stm32_pconf_group_get()
882 struct stm32_pinctrl_group *g = &pctl->groups[group]; in stm32_pconf_group_set()
886 ret = stm32_pconf_parse_conf(pctldev, g->pin, in stm32_pconf_group_set()
892 g->config = configs[i]; in stm32_pconf_group_set()
903 struct stm32_gpio_bank *bank; in stm32_pconf_dbg_show() local
918 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
921 stm32_pmx_get_mode(bank, offset, &mode, &alt); in stm32_pconf_dbg_show()
922 bias = stm32_pconf_get_bias(bank, offset); in stm32_pconf_dbg_show()
929 val = stm32_pconf_get(bank, offset, true); in stm32_pconf_dbg_show()
930 seq_printf(s, "- %s - %s", in stm32_pconf_dbg_show()
937 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
938 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
939 val = stm32_pconf_get(bank, offset, false); in stm32_pconf_dbg_show()
940 seq_printf(s, "- %s - %s - %s - %s %s", in stm32_pconf_dbg_show()
949 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
950 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
951 seq_printf(s, "%d - %s - %s - %s %s", alt, in stm32_pconf_dbg_show()
973 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank() local
975 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
977 struct device *dev = pctl->dev; in stm32_gpiolib_register_bank()
988 return -ENODEV; in stm32_gpiolib_register_bank()
990 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
991 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
992 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
994 bank->clk = of_clk_get_by_name(np, NULL); in stm32_gpiolib_register_bank()
995 if (IS_ERR(bank->clk)) { in stm32_gpiolib_register_bank()
996 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); in stm32_gpiolib_register_bank()
997 return PTR_ERR(bank->clk); in stm32_gpiolib_register_bank()
1000 err = clk_prepare(bank->clk); in stm32_gpiolib_register_bank()
1006 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1008 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1010 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { in stm32_gpiolib_register_bank()
1012 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1014 bank_nr = pctl->nbanks; in stm32_gpiolib_register_bank()
1015 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1016 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1017 range->id = bank_nr; in stm32_gpiolib_register_bank()
1018 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1019 range->base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1020 range->npins = npins; in stm32_gpiolib_register_bank()
1021 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1022 pinctrl_add_gpio_range(pctl->pctl_dev, in stm32_gpiolib_register_bank()
1023 &pctl->banks[bank_nr].range); in stm32_gpiolib_register_bank()
1026 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) in stm32_gpiolib_register_bank()
1029 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1031 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1032 bank->gpio_chip.of_node = np; in stm32_gpiolib_register_bank()
1033 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1034 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1035 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1036 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1039 bank->fwnode = of_node_to_fwnode(np); in stm32_gpiolib_register_bank()
1041 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, in stm32_gpiolib_register_bank()
1042 STM32_GPIO_IRQ_LINE, bank->fwnode, in stm32_gpiolib_register_bank()
1043 &stm32_gpio_domain_ops, bank); in stm32_gpiolib_register_bank()
1045 if (!bank->domain) in stm32_gpiolib_register_bank()
1046 return -ENODEV; in stm32_gpiolib_register_bank()
1048 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1054 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1061 struct device_node *np = pdev->dev.of_node, *parent; in stm32_pctrl_dt_setup_irq()
1062 struct device *dev = &pdev->dev; in stm32_pctrl_dt_setup_irq()
1069 return -ENXIO; in stm32_pctrl_dt_setup_irq()
1071 pctl->domain = irq_find_host(parent); in stm32_pctrl_dt_setup_irq()
1072 if (!pctl->domain) in stm32_pctrl_dt_setup_irq()
1073 return -ENXIO; in stm32_pctrl_dt_setup_irq()
1075 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in stm32_pctrl_dt_setup_irq()
1076 if (IS_ERR(pctl->regmap)) in stm32_pctrl_dt_setup_irq()
1077 return PTR_ERR(pctl->regmap); in stm32_pctrl_dt_setup_irq()
1079 rm = pctl->regmap; in stm32_pctrl_dt_setup_irq()
1096 mux.msb = mux.lsb + mask_width - 1; in stm32_pctrl_dt_setup_irq()
1101 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); in stm32_pctrl_dt_setup_irq()
1102 if (IS_ERR(pctl->irqmux[i])) in stm32_pctrl_dt_setup_irq()
1103 return PTR_ERR(pctl->irqmux[i]); in stm32_pctrl_dt_setup_irq()
1114 pctl->ngroups = pctl->match_data->npins; in stm32_pctrl_build_state()
1117 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1118 sizeof(*pctl->groups), GFP_KERNEL); in stm32_pctrl_build_state()
1119 if (!pctl->groups) in stm32_pctrl_build_state()
1120 return -ENOMEM; in stm32_pctrl_build_state()
1122 /* We assume that one pin is one group, use pin name as group name. */ in stm32_pctrl_build_state()
1123 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1124 sizeof(*pctl->grp_names), GFP_KERNEL); in stm32_pctrl_build_state()
1125 if (!pctl->grp_names) in stm32_pctrl_build_state()
1126 return -ENOMEM; in stm32_pctrl_build_state()
1128 for (i = 0; i < pctl->match_data->npins; i++) { in stm32_pctrl_build_state()
1129 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; in stm32_pctrl_build_state()
1130 struct stm32_pinctrl_group *group = pctl->groups + i; in stm32_pctrl_build_state()
1132 group->name = pin->pin.name; in stm32_pctrl_build_state()
1133 group->pin = pin->pin.number; in stm32_pctrl_build_state()
1135 pctl->grp_names[i] = pin->pin.name; in stm32_pctrl_build_state()
1143 struct device_node *np = pdev->dev.of_node; in stm32_pctl_probe()
1146 struct device *dev = &pdev->dev; in stm32_pctl_probe()
1152 return -EINVAL; in stm32_pctl_probe()
1154 match = of_match_device(dev->driver->of_match_table, dev); in stm32_pctl_probe()
1155 if (!match || !match->data) in stm32_pctl_probe()
1156 return -EINVAL; in stm32_pctl_probe()
1158 if (!of_find_property(np, "pins-are-numbered", NULL)) { in stm32_pctl_probe()
1159 dev_err(dev, "only support pins-are-numbered format\n"); in stm32_pctl_probe()
1160 return -EINVAL; in stm32_pctl_probe()
1165 return -ENOMEM; in stm32_pctl_probe()
1169 pctl->dev = dev; in stm32_pctl_probe()
1170 pctl->match_data = match->data; in stm32_pctl_probe()
1174 return -EINVAL; in stm32_pctl_probe()
1177 if (of_find_property(np, "interrupt-parent", NULL)) { in stm32_pctl_probe()
1183 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), in stm32_pctl_probe()
1186 return -ENOMEM; in stm32_pctl_probe()
1188 for (i = 0; i < pctl->match_data->npins; i++) in stm32_pctl_probe()
1189 pins[i] = pctl->match_data->pins[i].pin; in stm32_pctl_probe()
1191 pctl->pctl_desc.name = dev_name(&pdev->dev); in stm32_pctl_probe()
1192 pctl->pctl_desc.owner = THIS_MODULE; in stm32_pctl_probe()
1193 pctl->pctl_desc.pins = pins; in stm32_pctl_probe()
1194 pctl->pctl_desc.npins = pctl->match_data->npins; in stm32_pctl_probe()
1195 pctl->pctl_desc.confops = &stm32_pconf_ops; in stm32_pctl_probe()
1196 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; in stm32_pctl_probe()
1197 pctl->pctl_desc.pmxops = &stm32_pmx_ops; in stm32_pctl_probe()
1198 pctl->dev = &pdev->dev; in stm32_pctl_probe()
1200 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, in stm32_pctl_probe()
1203 if (IS_ERR(pctl->pctl_dev)) { in stm32_pctl_probe()
1204 dev_err(&pdev->dev, "Failed pinctrl registration\n"); in stm32_pctl_probe()
1205 return PTR_ERR(pctl->pctl_dev); in stm32_pctl_probe()
1209 if (of_property_read_bool(child, "gpio-controller")) in stm32_pctl_probe()
1213 dev_err(dev, "at least one GPIO bank is required\n"); in stm32_pctl_probe()
1214 return -EINVAL; in stm32_pctl_probe()
1216 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), in stm32_pctl_probe()
1218 if (!pctl->banks) in stm32_pctl_probe()
1219 return -ENOMEM; in stm32_pctl_probe()
1222 if (of_property_read_bool(child, "gpio-controller")) { in stm32_pctl_probe()
1227 pctl->nbanks++; in stm32_pctl_probe()