Lines Matching +full:bank +full:- +full:width
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
9 * Copyright (C) 2009-2011 ST-Ericsson AB
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-tegra.h"
36 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) in pmx_readl() argument
38 return readl(pmx->regs[bank] + reg); in pmx_readl()
41 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) in pmx_writel() argument
43 writel_relaxed(val, pmx->regs[bank] + reg); in pmx_writel()
45 pmx_readl(pmx, bank, reg); in pmx_writel()
52 return pmx->soc->ngroups; in tegra_pinctrl_get_groups_count()
60 return pmx->soc->groups[group].name; in tegra_pinctrl_get_group_name()
70 *pins = pmx->soc->groups[group].pins; in tegra_pinctrl_get_group_pins()
71 *num_pins = pmx->soc->groups[group].npins; in tegra_pinctrl_get_group_pins()
81 seq_printf(s, " %s", dev_name(pctldev->dev)); in tegra_pinctrl_pin_dbg_show()
91 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
92 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
94 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
95 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
96 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
97 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
99 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
100 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
101 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
102 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
103 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
104 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
113 struct device *dev = pctldev->dev; in tegra_pinctrl_dt_subnode_to_map()
127 if (ret != -EINVAL) in tegra_pinctrl_dt_subnode_to_map()
142 } else if (ret != -EINVAL) { in tegra_pinctrl_dt_subnode_to_map()
233 return pmx->soc->nfunctions; in tegra_pinctrl_get_funcs_count()
241 return pmx->soc->functions[function].name; in tegra_pinctrl_get_func_name()
251 *groups = pmx->soc->functions[function].groups; in tegra_pinctrl_get_func_groups()
252 *num_groups = pmx->soc->functions[function].ngroups; in tegra_pinctrl_get_func_groups()
266 g = &pmx->soc->groups[group]; in tegra_pinctrl_set_mux()
268 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
269 return -EINVAL; in tegra_pinctrl_set_mux()
271 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { in tegra_pinctrl_set_mux()
272 if (g->funcs[i] == function) in tegra_pinctrl_set_mux()
275 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) in tegra_pinctrl_set_mux()
276 return -EINVAL; in tegra_pinctrl_set_mux()
278 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
279 val &= ~(0x3 << g->mux_bit); in tegra_pinctrl_set_mux()
280 val |= i << g->mux_bit; in tegra_pinctrl_set_mux()
281 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
297 s8 *bank, s16 *reg, s8 *bit, s8 *width) in tegra_pinconf_reg() argument
301 *bank = g->pupd_bank; in tegra_pinconf_reg()
302 *reg = g->pupd_reg; in tegra_pinconf_reg()
303 *bit = g->pupd_bit; in tegra_pinconf_reg()
304 *width = 2; in tegra_pinconf_reg()
307 *bank = g->tri_bank; in tegra_pinconf_reg()
308 *reg = g->tri_reg; in tegra_pinconf_reg()
309 *bit = g->tri_bit; in tegra_pinconf_reg()
310 *width = 1; in tegra_pinconf_reg()
313 *bank = g->mux_bank; in tegra_pinconf_reg()
314 *reg = g->mux_reg; in tegra_pinconf_reg()
315 *bit = g->einput_bit; in tegra_pinconf_reg()
316 *width = 1; in tegra_pinconf_reg()
319 *bank = g->mux_bank; in tegra_pinconf_reg()
320 *reg = g->mux_reg; in tegra_pinconf_reg()
321 *bit = g->odrain_bit; in tegra_pinconf_reg()
322 *width = 1; in tegra_pinconf_reg()
325 *bank = g->mux_bank; in tegra_pinconf_reg()
326 *reg = g->mux_reg; in tegra_pinconf_reg()
327 *bit = g->lock_bit; in tegra_pinconf_reg()
328 *width = 1; in tegra_pinconf_reg()
331 *bank = g->mux_bank; in tegra_pinconf_reg()
332 *reg = g->mux_reg; in tegra_pinconf_reg()
333 *bit = g->ioreset_bit; in tegra_pinconf_reg()
334 *width = 1; in tegra_pinconf_reg()
337 *bank = g->mux_bank; in tegra_pinconf_reg()
338 *reg = g->mux_reg; in tegra_pinconf_reg()
339 *bit = g->rcv_sel_bit; in tegra_pinconf_reg()
340 *width = 1; in tegra_pinconf_reg()
343 if (pmx->soc->hsm_in_mux) { in tegra_pinconf_reg()
344 *bank = g->mux_bank; in tegra_pinconf_reg()
345 *reg = g->mux_reg; in tegra_pinconf_reg()
347 *bank = g->drv_bank; in tegra_pinconf_reg()
348 *reg = g->drv_reg; in tegra_pinconf_reg()
350 *bit = g->hsm_bit; in tegra_pinconf_reg()
351 *width = 1; in tegra_pinconf_reg()
354 if (pmx->soc->schmitt_in_mux) { in tegra_pinconf_reg()
355 *bank = g->mux_bank; in tegra_pinconf_reg()
356 *reg = g->mux_reg; in tegra_pinconf_reg()
358 *bank = g->drv_bank; in tegra_pinconf_reg()
359 *reg = g->drv_reg; in tegra_pinconf_reg()
361 *bit = g->schmitt_bit; in tegra_pinconf_reg()
362 *width = 1; in tegra_pinconf_reg()
365 *bank = g->drv_bank; in tegra_pinconf_reg()
366 *reg = g->drv_reg; in tegra_pinconf_reg()
367 *bit = g->lpmd_bit; in tegra_pinconf_reg()
368 *width = 2; in tegra_pinconf_reg()
371 *bank = g->drv_bank; in tegra_pinconf_reg()
372 *reg = g->drv_reg; in tegra_pinconf_reg()
373 *bit = g->drvdn_bit; in tegra_pinconf_reg()
374 *width = g->drvdn_width; in tegra_pinconf_reg()
377 *bank = g->drv_bank; in tegra_pinconf_reg()
378 *reg = g->drv_reg; in tegra_pinconf_reg()
379 *bit = g->drvup_bit; in tegra_pinconf_reg()
380 *width = g->drvup_width; in tegra_pinconf_reg()
383 *bank = g->drv_bank; in tegra_pinconf_reg()
384 *reg = g->drv_reg; in tegra_pinconf_reg()
385 *bit = g->slwf_bit; in tegra_pinconf_reg()
386 *width = g->slwf_width; in tegra_pinconf_reg()
389 *bank = g->drv_bank; in tegra_pinconf_reg()
390 *reg = g->drv_reg; in tegra_pinconf_reg()
391 *bit = g->slwr_bit; in tegra_pinconf_reg()
392 *width = g->slwr_width; in tegra_pinconf_reg()
395 if (pmx->soc->drvtype_in_mux) { in tegra_pinconf_reg()
396 *bank = g->mux_bank; in tegra_pinconf_reg()
397 *reg = g->mux_reg; in tegra_pinconf_reg()
399 *bank = g->drv_bank; in tegra_pinconf_reg()
400 *reg = g->drv_reg; in tegra_pinconf_reg()
402 *bit = g->drvtype_bit; in tegra_pinconf_reg()
403 *width = 2; in tegra_pinconf_reg()
406 dev_err(pmx->dev, "Invalid config param %04x\n", param); in tegra_pinconf_reg()
407 return -ENOTSUPP; in tegra_pinconf_reg()
422 dev_err(pmx->dev, in tegra_pinconf_reg()
424 param, prop, g->name); in tegra_pinconf_reg()
426 return -ENOTSUPP; in tegra_pinconf_reg()
435 dev_err(pctldev->dev, "pin_config_get op not supported\n"); in tegra_pinconf_get()
436 return -ENOTSUPP; in tegra_pinconf_get()
443 dev_err(pctldev->dev, "pin_config_set op not supported\n"); in tegra_pinconf_set()
444 return -ENOTSUPP; in tegra_pinconf_set()
455 s8 bank, bit, width; in tegra_pinconf_group_get() local
459 g = &pmx->soc->groups[group]; in tegra_pinconf_group_get()
461 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, in tegra_pinconf_group_get()
462 &width); in tegra_pinconf_group_get()
466 val = pmx_readl(pmx, bank, reg); in tegra_pinconf_group_get()
467 mask = (1 << width) - 1; in tegra_pinconf_group_get()
484 s8 bank, bit, width; in tegra_pinconf_group_set() local
488 g = &pmx->soc->groups[group]; in tegra_pinconf_group_set()
494 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, in tegra_pinconf_group_set()
495 &width); in tegra_pinconf_group_set()
499 val = pmx_readl(pmx, bank, reg); in tegra_pinconf_group_set()
504 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); in tegra_pinconf_group_set()
505 return -EINVAL; in tegra_pinconf_group_set()
509 /* Special-case Boolean values; allow any non-zero as true */ in tegra_pinconf_group_set()
510 if (width == 1) in tegra_pinconf_group_set()
513 /* Range-check user-supplied value */ in tegra_pinconf_group_set()
514 mask = (1 << width) - 1; in tegra_pinconf_group_set()
516 dev_err(pctldev->dev, in tegra_pinconf_group_set()
518 configs[i], arg, width); in tegra_pinconf_group_set()
519 return -EINVAL; in tegra_pinconf_group_set()
525 pmx_writel(pmx, val, bank, reg); in tegra_pinconf_group_set()
552 s8 bank, bit, width; in tegra_pinconf_group_dbg_show() local
556 g = &pmx->soc->groups[group]; in tegra_pinconf_group_dbg_show()
560 &bank, ®, &bit, &width); in tegra_pinconf_group_dbg_show()
564 val = pmx_readl(pmx, bank, reg); in tegra_pinconf_group_dbg_show()
566 val &= (1 << width) - 1; in tegra_pinconf_group_dbg_show()
624 for (i = 0; i < pmx->soc->ngroups; ++i) { in tegra_pinctrl_clear_parked_bits()
625 g = &pmx->soc->groups[i]; in tegra_pinctrl_clear_parked_bits()
626 if (g->parked_bit >= 0) { in tegra_pinctrl_clear_parked_bits()
627 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_clear_parked_bits()
628 val &= ~(1 << g->parked_bit); in tegra_pinctrl_clear_parked_bits()
629 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_clear_parked_bits()
643 has_prop = of_find_property(np, "gpio-ranges", NULL); in gpio_node_has_range()
659 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in tegra_pinctrl_probe()
661 return -ENOMEM; in tegra_pinctrl_probe()
663 pmx->dev = &pdev->dev; in tegra_pinctrl_probe()
664 pmx->soc = soc_data; in tegra_pinctrl_probe()
668 * This over-allocates slightly, since not all groups are mux groups. in tegra_pinctrl_probe()
670 pmx->group_pins = devm_kcalloc(&pdev->dev, in tegra_pinctrl_probe()
671 soc_data->ngroups * 4, sizeof(*pmx->group_pins), in tegra_pinctrl_probe()
673 if (!pmx->group_pins) in tegra_pinctrl_probe()
674 return -ENOMEM; in tegra_pinctrl_probe()
676 group_pins = pmx->group_pins; in tegra_pinctrl_probe()
677 for (fn = 0; fn < soc_data->nfunctions; fn++) { in tegra_pinctrl_probe()
678 struct tegra_function *func = &soc_data->functions[fn]; in tegra_pinctrl_probe()
680 func->groups = group_pins; in tegra_pinctrl_probe()
682 for (gn = 0; gn < soc_data->ngroups; gn++) { in tegra_pinctrl_probe()
683 const struct tegra_pingroup *g = &soc_data->groups[gn]; in tegra_pinctrl_probe()
685 if (g->mux_reg == -1) in tegra_pinctrl_probe()
689 if (g->funcs[gfn] == fn) in tegra_pinctrl_probe()
694 BUG_ON(group_pins - pmx->group_pins >= in tegra_pinctrl_probe()
695 soc_data->ngroups * 4); in tegra_pinctrl_probe()
696 *group_pins++ = g->name; in tegra_pinctrl_probe()
697 func->ngroups++; in tegra_pinctrl_probe()
701 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; in tegra_pinctrl_probe()
702 tegra_pinctrl_desc.name = dev_name(&pdev->dev); in tegra_pinctrl_probe()
703 tegra_pinctrl_desc.pins = pmx->soc->pins; in tegra_pinctrl_probe()
704 tegra_pinctrl_desc.npins = pmx->soc->npins; in tegra_pinctrl_probe()
711 pmx->nbanks = i; in tegra_pinctrl_probe()
713 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs), in tegra_pinctrl_probe()
715 if (!pmx->regs) in tegra_pinctrl_probe()
716 return -ENOMEM; in tegra_pinctrl_probe()
718 for (i = 0; i < pmx->nbanks; i++) { in tegra_pinctrl_probe()
720 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res); in tegra_pinctrl_probe()
721 if (IS_ERR(pmx->regs[i])) in tegra_pinctrl_probe()
722 return PTR_ERR(pmx->regs[i]); in tegra_pinctrl_probe()
725 pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx); in tegra_pinctrl_probe()
726 if (IS_ERR(pmx->pctl)) { in tegra_pinctrl_probe()
727 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in tegra_pinctrl_probe()
728 return PTR_ERR(pmx->pctl); in tegra_pinctrl_probe()
733 if (!gpio_node_has_range(pmx->soc->gpio_compatible)) in tegra_pinctrl_probe()
734 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); in tegra_pinctrl_probe()
738 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); in tegra_pinctrl_probe()