10 #include <linux/clk.h>
11 #include <linux/delay.h>
70 	struct clk *clk;  member
87 	return readl_relaxed(chip->base + offset);  in atmel_pwm_readl()
93 	writel_relaxed(val, chip->base + offset);  in atmel_pwm_writel()
101 	return readl_relaxed(chip->base + base + offset);  in atmel_pwm_ch_readl()
110 	writel_relaxed(val, chip->base + base + offset);  in atmel_pwm_ch_writel()
118 	unsigned long long cycles = state->period;  in atmel_pwm_calculate_cprd_and_pres()  local
120 	/* Calculate the period cycles and prescale value */  in atmel_pwm_calculate_cprd_and_pres()
121 	cycles *= clk_get_rate(atmel_pwm->clk);  in atmel_pwm_calculate_cprd_and_pres()
122 	do_div(cycles, NSEC_PER_SEC);  in atmel_pwm_calculate_cprd_and_pres()
124 	for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)  in atmel_pwm_calculate_cprd_and_pres()
128 		dev_err(chip->dev, "pres exceeds the maximum value\n");  in atmel_pwm_calculate_cprd_and_pres()
129 		return -EINVAL;  in atmel_pwm_calculate_cprd_and_pres()
132 	*cprd = cycles;  in atmel_pwm_calculate_cprd_and_pres()
140 	unsigned long long cycles = state->duty_cycle;  in atmel_pwm_calculate_cdty()  local
142 	cycles *= cprd;  in atmel_pwm_calculate_cdty()
143 	do_div(cycles, state->period);  in atmel_pwm_calculate_cdty()
144 	*cdty = cprd - cycles;  in atmel_pwm_calculate_cdty()
153 	if (atmel_pwm->regs->duty_upd ==  in atmel_pwm_update_cdty()
154 	    atmel_pwm->regs->period_upd) {  in atmel_pwm_update_cdty()
155 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_update_cdty()
157 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);  in atmel_pwm_update_cdty()
160 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_update_cdty()
161 			    atmel_pwm->regs->duty_upd, cdty);  in atmel_pwm_update_cdty()
170 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_set_cprd_cdty()
171 			    atmel_pwm->regs->duty, cdty);  in atmel_pwm_set_cprd_cdty()
172 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_set_cprd_cdty()
173 			    atmel_pwm->regs->period, cprd);  in atmel_pwm_set_cprd_cdty()
186 	mutex_lock(&atmel_pwm->isr_lock);  in atmel_pwm_disable()
187 	atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);  in atmel_pwm_disable()
189 	while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&  in atmel_pwm_disable()
192 		atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);  in atmel_pwm_disable()
195 	mutex_unlock(&atmel_pwm->isr_lock);  in atmel_pwm_disable()
196 	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);  in atmel_pwm_disable()
204 	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&  in atmel_pwm_disable()
209 		clk_disable(atmel_pwm->clk);  in atmel_pwm_disable()
223 	if (state->enabled) {  in atmel_pwm_apply()
225 		    cstate.polarity == state->polarity &&  in atmel_pwm_apply()
226 		    cstate.period == state->period) {  in atmel_pwm_apply()
227 			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,  in atmel_pwm_apply()
228 						  atmel_pwm->regs->period);  in atmel_pwm_apply()
237 			dev_err(chip->dev,  in atmel_pwm_apply()
247 			ret = clk_enable(atmel_pwm->clk);  in atmel_pwm_apply()
249 				dev_err(chip->dev, "failed to enable clock\n");  in atmel_pwm_apply()
255 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_apply()
257 		if (state->polarity == PWM_POLARITY_NORMAL)  in atmel_pwm_apply()
261 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);  in atmel_pwm_apply()
263 		mutex_lock(&atmel_pwm->isr_lock);  in atmel_pwm_apply()
264 		atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);  in atmel_pwm_apply()
265 		atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);  in atmel_pwm_apply()
266 		mutex_unlock(&atmel_pwm->isr_lock);  in atmel_pwm_apply()
267 		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);  in atmel_pwm_apply()
296 		.name = "at91sam9rl-pwm",
299 		.name = "sama5d3-pwm",
309 		.compatible = "atmel,at91sam9rl-pwm",
312 		.compatible = "atmel,sama5d3-pwm",
315 		.compatible = "atmel,sama5d2-pwm",
328 	if (pdev->dev.of_node)  in atmel_pwm_get_driver_data()
329 		return of_device_get_match_data(&pdev->dev);  in atmel_pwm_get_driver_data()
333 	return (struct atmel_pwm_registers *)id->driver_data;  in atmel_pwm_get_driver_data()
345 		return -ENODEV;  in atmel_pwm_probe()
347 	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);  in atmel_pwm_probe()
349 		return -ENOMEM;  in atmel_pwm_probe()
352 	atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);  in atmel_pwm_probe()
353 	if (IS_ERR(atmel_pwm->base))  in atmel_pwm_probe()
354 		return PTR_ERR(atmel_pwm->base);  in atmel_pwm_probe()
356 	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);  in atmel_pwm_probe()
357 	if (IS_ERR(atmel_pwm->clk))  in atmel_pwm_probe()
358 		return PTR_ERR(atmel_pwm->clk);  in atmel_pwm_probe()
360 	ret = clk_prepare(atmel_pwm->clk);  in atmel_pwm_probe()
362 		dev_err(&pdev->dev, "failed to prepare PWM clock\n");  in atmel_pwm_probe()
366 	atmel_pwm->chip.dev = &pdev->dev;  in atmel_pwm_probe()
367 	atmel_pwm->chip.ops = &atmel_pwm_ops;  in atmel_pwm_probe()
369 	if (pdev->dev.of_node) {  in atmel_pwm_probe()
370 		atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;  in atmel_pwm_probe()
371 		atmel_pwm->chip.of_pwm_n_cells = 3;  in atmel_pwm_probe()
374 	atmel_pwm->chip.base = -1;  in atmel_pwm_probe()
375 	atmel_pwm->chip.npwm = 4;  in atmel_pwm_probe()
376 	atmel_pwm->regs = regs;  in atmel_pwm_probe()
377 	atmel_pwm->updated_pwms = 0;  in atmel_pwm_probe()
378 	mutex_init(&atmel_pwm->isr_lock);  in atmel_pwm_probe()
380 	ret = pwmchip_add(&atmel_pwm->chip);  in atmel_pwm_probe()
382 		dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);  in atmel_pwm_probe()
391 	clk_unprepare(atmel_pwm->clk);  in atmel_pwm_probe()
399 	clk_unprepare(atmel_pwm->clk);  in atmel_pwm_remove()
400 	mutex_destroy(&atmel_pwm->isr_lock);  in atmel_pwm_remove()
402 	return pwmchip_remove(&atmel_pwm->chip);  in atmel_pwm_remove()
407 		.name = "atmel-pwm",
416 MODULE_ALIAS("platform:atmel-pwm");