30 #define PWM_CFG0_ADDR(x)    (((x) * 0x20) + 0x0)  argument
31 #define PWM_CFG1_ADDR(x)    (((x) * 0x20) + 0x4)  argument
32 #define PWM_CFG2_ADDR(x)    (((x) * 0x20) + 0x8)  argument
33 #define PWM_CTRL_ADDR(x)    (((x) * 0x20) + 0xC)  argument
50 	void __iomem *base;  member
68 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,  in hibvt_pwm_set_bits()  argument
71 	void __iomem *address = base + offset;  in hibvt_pwm_set_bits()
84 	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),  in hibvt_pwm_enable()
92 	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),  in hibvt_pwm_disable()
102 	freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);  in hibvt_pwm_config()
104 	period = div_u64(freq * period_ns, 1000);  in hibvt_pwm_config()
107 	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),  in hibvt_pwm_config()
110 	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),  in hibvt_pwm_config()
121 		hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),  in hibvt_pwm_set_polarity()
124 		hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),  in hibvt_pwm_set_polarity()
132 	void __iomem *base;  in hibvt_pwm_get_state()  local
135 	freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);  in hibvt_pwm_get_state()
136 	base = hi_pwm_chip->base;  in hibvt_pwm_get_state()
138 	value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));  in hibvt_pwm_get_state()
139 	state->period = div_u64(value * 1000, freq);  in hibvt_pwm_get_state()
141 	value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));  in hibvt_pwm_get_state()
142 	state->duty_cycle = div_u64(value * 1000, freq);  in hibvt_pwm_get_state()
144 	value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));  in hibvt_pwm_get_state()
145 	state->enabled = (PWM_ENABLE_MASK & value);  in hibvt_pwm_get_state()
151 	if (state->polarity != pwm->state.polarity)  in hibvt_pwm_apply()
152 		hibvt_pwm_set_polarity(chip, pwm, state->polarity);  in hibvt_pwm_apply()
154 	if (state->period != pwm->state.period ||  in hibvt_pwm_apply()
155 		state->duty_cycle != pwm->state.duty_cycle)  in hibvt_pwm_apply()
156 		hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);  in hibvt_pwm_apply()
158 	if (state->enabled != pwm->state.enabled) {  in hibvt_pwm_apply()
159 		if (state->enabled)  in hibvt_pwm_apply()
178 				of_device_get_match_data(&pdev->dev);  in hibvt_pwm_probe()
184 	pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);  in hibvt_pwm_probe()
186 		return -ENOMEM;  in hibvt_pwm_probe()
188 	pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);  in hibvt_pwm_probe()
189 	if (IS_ERR(pwm_chip->clk)) {  in hibvt_pwm_probe()
190 		dev_err(&pdev->dev, "getting clock failed with %ld\n",  in hibvt_pwm_probe()
191 				PTR_ERR(pwm_chip->clk));  in hibvt_pwm_probe()
192 		return PTR_ERR(pwm_chip->clk);  in hibvt_pwm_probe()
195 	pwm_chip->chip.ops = &hibvt_pwm_ops;  in hibvt_pwm_probe()
196 	pwm_chip->chip.dev = &pdev->dev;  in hibvt_pwm_probe()
197 	pwm_chip->chip.base = -1;  in hibvt_pwm_probe()
198 	pwm_chip->chip.npwm = soc->num_pwms;  in hibvt_pwm_probe()
199 	pwm_chip->chip.of_xlate = of_pwm_xlate_with_flags;  in hibvt_pwm_probe()
200 	pwm_chip->chip.of_pwm_n_cells = 3;  in hibvt_pwm_probe()
203 	pwm_chip->base = devm_ioremap_resource(&pdev->dev, res);  in hibvt_pwm_probe()
204 	if (IS_ERR(pwm_chip->base))  in hibvt_pwm_probe()
205 		return PTR_ERR(pwm_chip->base);  in hibvt_pwm_probe()
207 	ret = clk_prepare_enable(pwm_chip->clk);  in hibvt_pwm_probe()
211 	pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in hibvt_pwm_probe()
212 	if (IS_ERR(pwm_chip->rstc)) {  in hibvt_pwm_probe()
213 		clk_disable_unprepare(pwm_chip->clk);  in hibvt_pwm_probe()
214 		return PTR_ERR(pwm_chip->rstc);  in hibvt_pwm_probe()
217 	reset_control_assert(pwm_chip->rstc);  in hibvt_pwm_probe()
219 	reset_control_deassert(pwm_chip->rstc);  in hibvt_pwm_probe()
221 	ret = pwmchip_add(&pwm_chip->chip);  in hibvt_pwm_probe()
223 		clk_disable_unprepare(pwm_chip->clk);  in hibvt_pwm_probe()
227 	for (i = 0; i < pwm_chip->chip.npwm; i++) {  in hibvt_pwm_probe()
228 		hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),  in hibvt_pwm_probe()
243 	reset_control_assert(pwm_chip->rstc);  in hibvt_pwm_remove()
245 	reset_control_deassert(pwm_chip->rstc);  in hibvt_pwm_remove()
247 	clk_disable_unprepare(pwm_chip->clk);  in hibvt_pwm_remove()
249 	return pwmchip_remove(&pwm_chip->chip);  in hibvt_pwm_remove()
253 	{ .compatible = "hisilicon,hi3516cv300-pwm", .data = &pwm_soc[0] },
254 	{ .compatible = "hisilicon,hi3519v100-pwm", .data = &pwm_soc[1] },
261 		.name = "hibvt-pwm",