1 // SPDX-License-Identifier: GPL-2.0
3  * simple driver for PWM (Pulse Width Modulator) controller
5  * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
16 #include <linux/pwm.h>
20 /* i.MX1 and i.MX21 share the same PWM function block: */
22 #define MX1_PWMC			0x00   /* PWM Control Register */
23 #define MX1_PWMS			0x04   /* PWM Sample Register */
24 #define MX1_PWMP			0x08   /* PWM Period Register */
28 /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
30 #define MX3_PWMCR			0x00    /* PWM Control Register */
31 #define MX3_PWMSR			0x04    /* PWM Status Register */
32 #define MX3_PWMSAR			0x0C    /* PWM Sample Register */
33 #define MX3_PWMPR			0x10    /* PWM Period Register */
34 #define MX3_PWMCR_PRESCALER(x)		((((x) - 1) & 0xFFF) << 4)
60 		struct pwm_device *pwm, int duty_ns, int period_ns)  in imx_pwm_config_v1()  argument
65 	 * The PWM subsystem allows for exact frequencies. However,  in imx_pwm_config_v1()
66 	 * I cannot connect a scope on my device to the PWM line and  in imx_pwm_config_v1()
67 	 * thus cannot provide the program the PWM controller  in imx_pwm_config_v1()
69 	 * Bootloader (u-boot or WinCE+haret) has programmed the PWM  in imx_pwm_config_v1()
70 	 * function group already. So I'll just modify the PWM sample  in imx_pwm_config_v1()
81 	u32 max = readl(imx->mmio_base + MX1_PWMP);  in imx_pwm_config_v1()
83 	writel(max - p, imx->mmio_base + MX1_PWMS);  in imx_pwm_config_v1()
88 static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)  in imx_pwm_enable_v1()  argument
94 	ret = clk_prepare_enable(imx->clk_per);  in imx_pwm_enable_v1()
98 	val = readl(imx->mmio_base + MX1_PWMC);  in imx_pwm_enable_v1()
100 	writel(val, imx->mmio_base + MX1_PWMC);  in imx_pwm_enable_v1()
105 static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)  in imx_pwm_disable_v1()  argument
110 	val = readl(imx->mmio_base + MX1_PWMC);  in imx_pwm_disable_v1()
112 	writel(val, imx->mmio_base + MX1_PWMC);  in imx_pwm_disable_v1()
114 	clk_disable_unprepare(imx->clk_per);  in imx_pwm_disable_v1()
120 	struct device *dev = chip->dev;  in imx_pwm_sw_reset()
124 	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);  in imx_pwm_sw_reset()
127 		cr = readl(imx->mmio_base + MX3_PWMCR);  in imx_pwm_sw_reset()
136 				   struct pwm_device *pwm)  in imx_pwm_wait_fifo_slot()  argument
139 	struct device *dev = chip->dev;  in imx_pwm_wait_fifo_slot()
144 	sr = readl(imx->mmio_base + MX3_PWMSR);  in imx_pwm_wait_fifo_slot()
147 		period_ms = DIV_ROUND_UP(pwm_get_period(pwm),  in imx_pwm_wait_fifo_slot()
151 		sr = readl(imx->mmio_base + MX3_PWMSR);  in imx_pwm_wait_fifo_slot()
157 static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,  in imx_pwm_apply_v2()  argument
167 	pwm_get_state(pwm, &cstate);  in imx_pwm_apply_v2()
169 	if (state->enabled) {  in imx_pwm_apply_v2()
170 		c = clk_get_rate(imx->clk_per);  in imx_pwm_apply_v2()
171 		c *= state->period;  in imx_pwm_apply_v2()
179 		c = (unsigned long long)period_cycles * state->duty_cycle;  in imx_pwm_apply_v2()
180 		do_div(c, state->period);  in imx_pwm_apply_v2()
184 		 * according to imx pwm RM, the real period value should be  in imx_pwm_apply_v2()
188 			period_cycles -= 2;  in imx_pwm_apply_v2()
193 		 * Wait for a free FIFO slot if the PWM is already enabled, and  in imx_pwm_apply_v2()
194 		 * flush the FIFO if the PWM was disabled and is about to be  in imx_pwm_apply_v2()
198 			imx_pwm_wait_fifo_slot(chip, pwm);  in imx_pwm_apply_v2()
200 			ret = clk_prepare_enable(imx->clk_per);  in imx_pwm_apply_v2()
207 		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);  in imx_pwm_apply_v2()
208 		writel(period_cycles, imx->mmio_base + MX3_PWMPR);  in imx_pwm_apply_v2()
215 		if (state->polarity == PWM_POLARITY_INVERSED)  in imx_pwm_apply_v2()
218 		writel(cr, imx->mmio_base + MX3_PWMCR);  in imx_pwm_apply_v2()
220 		writel(0, imx->mmio_base + MX3_PWMCR);  in imx_pwm_apply_v2()
222 		clk_disable_unprepare(imx->clk_per);  in imx_pwm_apply_v2()
255 	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
256 	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
264 			of_match_device(imx_pwm_dt_ids, &pdev->dev);  in imx_pwm_probe()
271 		return -ENODEV;  in imx_pwm_probe()
273 	data = of_id->data;  in imx_pwm_probe()
275 	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);  in imx_pwm_probe()
277 		return -ENOMEM;  in imx_pwm_probe()
279 	imx->clk_per = devm_clk_get(&pdev->dev, "per");  in imx_pwm_probe()
280 	if (IS_ERR(imx->clk_per)) {  in imx_pwm_probe()
281 		dev_err(&pdev->dev, "getting per clock failed with %ld\n",  in imx_pwm_probe()
282 				PTR_ERR(imx->clk_per));  in imx_pwm_probe()
283 		return PTR_ERR(imx->clk_per);  in imx_pwm_probe()
286 	imx->chip.ops = data->ops;  in imx_pwm_probe()
287 	imx->chip.dev = &pdev->dev;  in imx_pwm_probe()
288 	imx->chip.base = -1;  in imx_pwm_probe()
289 	imx->chip.npwm = 1;  in imx_pwm_probe()
291 	if (data->polarity_supported) {  in imx_pwm_probe()
292 		dev_dbg(&pdev->dev, "PWM supports output inversion\n");  in imx_pwm_probe()
293 		imx->chip.of_xlate = of_pwm_xlate_with_flags;  in imx_pwm_probe()
294 		imx->chip.of_pwm_n_cells = 3;  in imx_pwm_probe()
298 	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);  in imx_pwm_probe()
299 	if (IS_ERR(imx->mmio_base))  in imx_pwm_probe()
300 		return PTR_ERR(imx->mmio_base);  in imx_pwm_probe()
302 	ret = pwmchip_add(&imx->chip);  in imx_pwm_probe()
316 		return -ENODEV;  in imx_pwm_remove()
318 	return pwmchip_remove(&imx->chip);  in imx_pwm_remove()
323 		.name	= "imx-pwm",