Lines Matching +full:0 +full:x03
222 if (ret < 0) { in ab8500_regulator_enable()
229 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", in ab8500_regulator_enable()
248 info->update_mask, 0x0); in ab8500_regulator_disable()
249 if (ret < 0) { in ab8500_regulator_disable()
256 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", in ab8500_regulator_disable()
258 info->update_mask, 0x0); in ab8500_regulator_disable()
276 if (ret < 0) { in ab8500_regulator_is_enabled()
278 "couldn't read 0x%x register\n", info->update_reg); in ab8500_regulator_is_enabled()
283 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," in ab8500_regulator_is_enabled()
284 " 0x%x\n", in ab8500_regulator_is_enabled()
291 return 0; in ab8500_regulator_is_enabled()
318 int ret = 0; in ab8500_regulator_set_mode()
378 if (ret < 0) { in ab8500_regulator_set_mode()
386 "0x%x, 0x%x, 0x%x, 0x%x\n", in ab8500_regulator_set_mode()
465 if (ret < 0) { in ab8500_regulator_get_voltage_sel()
473 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", in ab8500_regulator_get_voltage_sel()
500 if (ret < 0) in ab8500_regulator_set_voltage_sel()
505 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," in ab8500_regulator_set_voltage_sel()
506 " 0x%x\n", in ab8500_regulator_set_voltage_sel()
582 .update_bank = 0x04,
583 .update_reg = 0x09,
584 .update_mask = 0x03,
585 .update_val = 0x01,
586 .update_val_idle = 0x03,
587 .update_val_normal = 0x01,
588 .voltage_bank = 0x04,
589 .voltage_reg = 0x1f,
590 .voltage_mask = 0x0f,
605 .update_bank = 0x04,
606 .update_reg = 0x09,
607 .update_mask = 0x0c,
608 .update_val = 0x04,
609 .update_val_idle = 0x0c,
610 .update_val_normal = 0x04,
611 .voltage_bank = 0x04,
612 .voltage_reg = 0x20,
613 .voltage_mask = 0x0f,
628 .update_bank = 0x04,
629 .update_reg = 0x0a,
630 .update_mask = 0x03,
631 .update_val = 0x01,
632 .update_val_idle = 0x03,
633 .update_val_normal = 0x01,
634 .voltage_bank = 0x04,
635 .voltage_reg = 0x21,
636 .voltage_mask = 0x07,
650 .update_bank = 0x03,
651 .update_reg = 0x80,
652 .update_mask = 0x44,
653 .update_val = 0x44,
654 .update_val_idle = 0x44,
655 .update_val_normal = 0x04,
656 .voltage_bank = 0x03,
657 .voltage_reg = 0x80,
658 .voltage_mask = 0x38,
678 .update_bank = 0x03,
679 .update_reg = 0x80,
680 .update_mask = 0x82,
681 .update_val = 0x02,
682 .update_val_idle = 0x82,
683 .update_val_normal = 0x02,
696 .update_bank = 0x03,
697 .update_reg = 0x83,
698 .update_mask = 0x02,
699 .update_val = 0x02,
712 .update_bank = 0x03,
713 .update_reg = 0x83,
714 .update_mask = 0x08,
715 .update_val = 0x08,
728 .update_bank = 0x03,
729 .update_reg = 0x83,
730 .update_mask = 0x10,
731 .update_val = 0x10,
744 .update_bank = 0x03,
745 .update_reg = 0x83,
746 .update_mask = 0x04,
747 .update_val = 0x04,
765 .update_bank = 0x04,
766 .update_reg = 0x06,
767 .update_mask = 0x0c,
768 .update_val = 0x04,
769 .update_val_idle = 0x0c,
770 .update_val_normal = 0x04,
794 .update_bank = 0x04,
795 .update_reg = 0x09,
796 .update_mask = 0x03,
797 .update_val = 0x01,
798 .update_val_idle = 0x03,
799 .update_val_normal = 0x01,
800 .voltage_bank = 0x04,
801 .voltage_reg = 0x1f,
802 .voltage_mask = 0x0f,
815 .update_bank = 0x04,
816 .update_reg = 0x09,
817 .update_mask = 0x0c,
818 .update_val = 0x04,
819 .update_val_idle = 0x0c,
820 .update_val_normal = 0x04,
821 .voltage_bank = 0x04,
822 .voltage_reg = 0x20,
823 .voltage_mask = 0x0f,
836 .update_bank = 0x04,
837 .update_reg = 0x0a,
838 .update_mask = 0x03,
839 .update_val = 0x01,
840 .update_val_idle = 0x03,
841 .update_val_normal = 0x01,
842 .voltage_bank = 0x04,
843 .voltage_reg = 0x21,
844 .voltage_mask = 0x07,
858 .update_bank = 0x04,
859 .update_reg = 0x2e,
860 .update_mask = 0x03,
861 .update_val = 0x01,
862 .update_val_idle = 0x03,
863 .update_val_normal = 0x01,
865 .voltage_bank = 0x04,
866 .voltage_reg = 0x2f,
867 .voltage_mask = 0x0f,
881 .update_bank = 0x01,
882 .update_reg = 0x55,
883 .update_mask = 0x18,
884 .update_val = 0x10,
885 .update_val_idle = 0x18,
886 .update_val_normal = 0x10,
887 .voltage_bank = 0x01,
888 .voltage_reg = 0x55,
889 .voltage_mask = 0x07,
903 .update_bank = 0x01,
904 .update_reg = 0x56,
905 .update_mask = 0x18,
906 .update_val = 0x10,
907 .update_val_idle = 0x18,
908 .update_val_normal = 0x10,
909 .voltage_bank = 0x01,
910 .voltage_reg = 0x56,
911 .voltage_mask = 0x07,
924 .update_bank = 0x03,
925 .update_reg = 0x80,
926 .update_mask = 0x44,
927 .update_val = 0x04,
928 .update_val_idle = 0x44,
929 .update_val_normal = 0x04,
930 .voltage_bank = 0x03,
931 .voltage_reg = 0x80,
932 .voltage_mask = 0x38,
952 .update_bank = 0x03,
953 .update_reg = 0x80,
954 .update_mask = 0x82,
955 .update_val = 0x02,
956 .update_val_idle = 0x82,
957 .update_val_normal = 0x02,
969 .update_bank = 0x03,
970 .update_reg = 0x83,
971 .update_mask = 0x02,
972 .update_val = 0x02,
973 .voltage_bank = 0x01,
974 .voltage_reg = 0x57,
975 .voltage_mask = 0x70,
988 .update_bank = 0x03,
989 .update_reg = 0x83,
990 .update_mask = 0x08,
991 .update_val = 0x08,
992 .mode_bank = 0x01,
993 .mode_reg = 0x54,
994 .mode_mask = 0x04,
995 .mode_val_idle = 0x04,
996 .mode_val_normal = 0x00,
1009 .update_bank = 0x03,
1010 .update_reg = 0x83,
1011 .update_mask = 0x10,
1012 .update_val = 0x10,
1013 .mode_bank = 0x01,
1014 .mode_reg = 0x54,
1015 .mode_mask = 0x04,
1016 .mode_val_idle = 0x04,
1017 .mode_val_normal = 0x00,
1029 .update_bank = 0x03,
1030 .update_reg = 0x83,
1031 .update_mask = 0x04,
1032 .update_val = 0x04,
1048 .update_bank = 0x04,
1049 .update_reg = 0x06,
1050 .update_mask = 0x0c,
1051 .update_val = 0x04,
1052 .update_val_idle = 0x0c,
1053 .update_val_normal = 0x04,
1054 .voltage_bank = 0x04,
1055 .voltage_reg = 0x29,
1056 .voltage_mask = 0x7,
1084 * 0x30, VanaRequestCtrl
1085 * 0xc0, VextSupply1RequestCtrl
1087 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
1089 * 0x03, VextSupply2RequestCtrl
1090 * 0x0c, VextSupply3RequestCtrl
1091 * 0x30, Vaux1RequestCtrl
1092 * 0xc0, Vaux2RequestCtrl
1094 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1096 * 0x03, Vaux3RequestCtrl
1097 * 0x04, SwHPReq
1099 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1101 * 0x08, VanaSysClkReq1HPValid
1102 * 0x20, Vaux1SysClkReq1HPValid
1103 * 0x40, Vaux2SysClkReq1HPValid
1104 * 0x80, Vaux3SysClkReq1HPValid
1106 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
1108 * 0x10, VextSupply1SysClkReq1HPValid
1109 * 0x20, VextSupply2SysClkReq1HPValid
1110 * 0x40, VextSupply3SysClkReq1HPValid
1112 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
1114 * 0x08, VanaHwHPReq1Valid
1115 * 0x20, Vaux1HwHPReq1Valid
1116 * 0x40, Vaux2HwHPReq1Valid
1117 * 0x80, Vaux3HwHPReq1Valid
1119 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
1121 * 0x01, VextSupply1HwHPReq1Valid
1122 * 0x02, VextSupply2HwHPReq1Valid
1123 * 0x04, VextSupply3HwHPReq1Valid
1125 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
1127 * 0x08, VanaHwHPReq2Valid
1128 * 0x20, Vaux1HwHPReq2Valid
1129 * 0x40, Vaux2HwHPReq2Valid
1130 * 0x80, Vaux3HwHPReq2Valid
1132 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
1134 * 0x01, VextSupply1HwHPReq2Valid
1135 * 0x02, VextSupply2HwHPReq2Valid
1136 * 0x04, VextSupply3HwHPReq2Valid
1138 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
1140 * 0x20, VanaSwHPReqValid
1141 * 0x80, Vaux1SwHPReqValid
1143 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
1145 * 0x01, Vaux2SwHPReqValid
1146 * 0x02, Vaux3SwHPReqValid
1147 * 0x04, VextSupply1SwHPReqValid
1148 * 0x08, VextSupply2SwHPReqValid
1149 * 0x10, VextSupply3SwHPReqValid
1151 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
1153 * 0x02, SysClkReq2Valid1
1154 * 0x04, SysClkReq3Valid1
1155 * 0x08, SysClkReq4Valid1
1156 * 0x10, SysClkReq5Valid1
1157 * 0x20, SysClkReq6Valid1
1158 * 0x40, SysClkReq7Valid1
1159 * 0x80, SysClkReq8Valid1
1161 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1163 * 0x02, SysClkReq2Valid2
1164 * 0x04, SysClkReq3Valid2
1165 * 0x08, SysClkReq4Valid2
1166 * 0x10, SysClkReq5Valid2
1167 * 0x20, SysClkReq6Valid2
1168 * 0x40, SysClkReq7Valid2
1169 * 0x80, SysClkReq8Valid2
1171 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1173 * 0x02, VTVoutEna
1174 * 0x04, Vintcore12Ena
1175 * 0x38, Vintcore12Sel
1176 * 0x40, Vintcore12LP
1177 * 0x80, VTVoutLP
1179 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1181 * 0x02, VaudioEna
1182 * 0x04, VdmicEna
1183 * 0x08, Vamic1Ena
1184 * 0x10, Vamic2Ena
1186 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1188 * 0x01, Vamic1_dzout
1189 * 0x02, Vamic2_dzout
1191 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1193 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1194 * 0x0c, VanaRegu
1196 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1198 * 0x01, VrefDDREna
1199 * 0x02, VrefDDRSleepMode
1201 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1203 * 0x03, VextSupply1Regu
1204 * 0x0c, VextSupply2Regu
1205 * 0x30, VextSupply3Regu
1206 * 0x40, ExtSupply2Bypass
1207 * 0x80, ExtSupply3Bypass
1209 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1211 * 0x03, Vaux1Regu
1212 * 0x0c, Vaux2Regu
1214 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1216 * 0x03, Vaux3Regu
1218 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
1220 * 0x0f, Vaux1Sel
1222 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1224 * 0x0f, Vaux2Sel
1226 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1228 * 0x07, Vaux3Sel
1230 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
1232 * 0x01, VextSupply12LP
1234 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1236 * 0x04, Vaux1Disch
1237 * 0x08, Vaux2Disch
1238 * 0x10, Vaux3Disch
1239 * 0x20, Vintcore12Disch
1240 * 0x40, VTVoutDisch
1241 * 0x80, VaudioDisch
1243 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1245 * 0x02, VanaDisch
1246 * 0x04, VdmicPullDownEna
1247 * 0x10, VdmicDisch
1249 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1255 * 0x03, VarmRequestCtrl
1256 * 0x0c, VsmpsCRequestCtrl
1257 * 0x30, VsmpsARequestCtrl
1258 * 0xc0, VsmpsBRequestCtrl
1260 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1262 * 0x03, VsafeRequestCtrl
1263 * 0x0c, VpllRequestCtrl
1264 * 0x30, VanaRequestCtrl
1266 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1268 * 0x30, Vaux1RequestCtrl
1269 * 0xc0, Vaux2RequestCtrl
1271 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1273 * 0x03, Vaux3RequestCtrl
1274 * 0x04, SwHPReq
1276 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1278 * 0x01, VsmpsASysClkReq1HPValid
1279 * 0x02, VsmpsBSysClkReq1HPValid
1280 * 0x04, VsafeSysClkReq1HPValid
1281 * 0x08, VanaSysClkReq1HPValid
1282 * 0x10, VpllSysClkReq1HPValid
1283 * 0x20, Vaux1SysClkReq1HPValid
1284 * 0x40, Vaux2SysClkReq1HPValid
1285 * 0x80, Vaux3SysClkReq1HPValid
1287 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1289 * 0x01, VsmpsCSysClkReq1HPValid
1290 * 0x02, VarmSysClkReq1HPValid
1291 * 0x04, VbbSysClkReq1HPValid
1292 * 0x08, VsmpsMSysClkReq1HPValid
1294 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
1296 * 0x01, VsmpsAHwHPReq1Valid
1297 * 0x02, VsmpsBHwHPReq1Valid
1298 * 0x04, VsafeHwHPReq1Valid
1299 * 0x08, VanaHwHPReq1Valid
1300 * 0x10, VpllHwHPReq1Valid
1301 * 0x20, Vaux1HwHPReq1Valid
1302 * 0x40, Vaux2HwHPReq1Valid
1303 * 0x80, Vaux3HwHPReq1Valid
1305 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
1307 * 0x08, VsmpsMHwHPReq1Valid
1309 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
1311 * 0x01, VsmpsAHwHPReq2Valid
1312 * 0x02, VsmpsBHwHPReq2Valid
1313 * 0x04, VsafeHwHPReq2Valid
1314 * 0x08, VanaHwHPReq2Valid
1315 * 0x10, VpllHwHPReq2Valid
1316 * 0x20, Vaux1HwHPReq2Valid
1317 * 0x40, Vaux2HwHPReq2Valid
1318 * 0x80, Vaux3HwHPReq2Valid
1320 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
1322 * 0x08, VsmpsMHwHPReq2Valid
1324 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
1326 * 0x01, VsmpsCSwHPReqValid
1327 * 0x02, VarmSwHPReqValid
1328 * 0x04, VsmpsASwHPReqValid
1329 * 0x08, VsmpsBSwHPReqValid
1330 * 0x10, VsafeSwHPReqValid
1331 * 0x20, VanaSwHPReqValid
1332 * 0x40, VpllSwHPReqValid
1333 * 0x80, Vaux1SwHPReqValid
1335 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
1337 * 0x01, Vaux2SwHPReqValid
1338 * 0x02, Vaux3SwHPReqValid
1339 * 0x20, VsmpsMSwHPReqValid
1341 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
1343 * 0x02, SysClkReq2Valid1
1344 * 0x04, SysClkReq3Valid1
1345 * 0x08, SysClkReq4Valid1
1347 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
1349 * 0x02, SysClkReq2Valid2
1350 * 0x04, SysClkReq3Valid2
1351 * 0x08, SysClkReq4Valid2
1353 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
1355 * 0x01, Vaux4SwHPReqValid
1356 * 0x02, Vaux4HwHPReq2Valid
1357 * 0x04, Vaux4HwHPReq1Valid
1358 * 0x08, Vaux4SysClkReq1HPValid
1360 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
1362 * 0x02, VadcEna
1363 * 0x04, VintCore12Ena
1364 * 0x38, VintCore12Sel
1365 * 0x40, VintCore12LP
1366 * 0x80, VadcLP
1368 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
1370 * 0x02, VaudioEna
1371 * 0x04, VdmicEna
1372 * 0x08, Vamic1Ena
1373 * 0x10, Vamic2Ena
1375 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1377 * 0x01, Vamic1_dzout
1378 * 0x02, Vamic2_dzout
1380 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1382 * 0x03, VsmpsARegu
1383 * 0x0c, VsmpsASelCtrl
1384 * 0x10, VsmpsAAutoMode
1385 * 0x20, VsmpsAPWMMode
1387 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
1389 * 0x03, VsmpsBRegu
1390 * 0x0c, VsmpsBSelCtrl
1391 * 0x10, VsmpsBAutoMode
1392 * 0x20, VsmpsBPWMMode
1394 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
1396 * 0x03, VsafeRegu
1397 * 0x0c, VsafeSelCtrl
1398 * 0x10, VsafeAutoMode
1399 * 0x20, VsafePWMMode
1401 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
1403 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1404 * 0x0c, VanaRegu
1406 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1408 * 0x03, VextSupply1Regu
1409 * 0x0c, VextSupply2Regu
1410 * 0x30, VextSupply3Regu
1411 * 0x40, ExtSupply2Bypass
1412 * 0x80, ExtSupply3Bypass
1414 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1416 * 0x03, Vaux1Regu
1417 * 0x0c, Vaux2Regu
1419 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
1421 * 0x0f, Vaux3Regu
1423 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
1425 * 0x3f, VsmpsASel1
1427 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
1429 * 0x3f, VsmpsASel2
1431 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
1433 * 0x3f, VsmpsASel3
1435 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
1437 * 0x3f, VsmpsBSel1
1439 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
1441 * 0x3f, VsmpsBSel2
1443 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
1445 * 0x3f, VsmpsBSel3
1447 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
1449 * 0x7f, VsafeSel1
1451 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
1453 * 0x3f, VsafeSel2
1455 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
1457 * 0x3f, VsafeSel3
1459 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
1461 * 0x0f, Vaux1Sel
1463 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
1465 * 0x0f, Vaux2Sel
1467 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
1469 * 0x07, Vaux3Sel
1470 * 0x30, VRF1Sel
1472 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
1474 * 0x03, Vaux4RequestCtrl
1476 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
1478 * 0x03, Vaux4Regu
1480 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
1482 * 0x0f, Vaux4Sel
1484 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
1486 * 0x04, Vaux1Disch
1487 * 0x08, Vaux2Disch
1488 * 0x10, Vaux3Disch
1489 * 0x20, Vintcore12Disch
1490 * 0x40, VTVoutDisch
1491 * 0x80, VaudioDisch
1493 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1495 * 0x02, VanaDisch
1496 * 0x04, VdmicPullDownEna
1497 * 0x10, VdmicDisch
1499 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1501 * 0x01, Vaux4Disch
1503 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
1505 * 0x07, Vaux5Sel
1506 * 0x08, Vaux5LP
1507 * 0x10, Vaux5Ena
1508 * 0x20, Vaux5Disch
1509 * 0x40, Vaux5DisSfst
1510 * 0x80, Vaux5DisPulld
1512 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
1514 * 0x07, Vaux6Sel
1515 * 0x08, Vaux6LP
1516 * 0x10, Vaux6Ena
1517 * 0x80, Vaux6DisPulld
1519 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
1596 /* fix for hardware before ab8500v2.0 */ in ab8500_regulator_register()
1602 info->voltage_mask = 0xf; in ab8500_regulator_register()
1615 return 0; in ab8500_regulator_register()
1635 if (err < 0) { in ab8500_regulator_probe()
1642 for (i = 0; i < abx500_regulator.info_size; i++) { in ab8500_regulator_probe()
1649 return 0; in ab8500_regulator_probe()
1664 if (ret != 0) in ab8500_regulator_init()