Lines Matching +full:per +full:- +full:context

28  * except for SCSI CDB which remains big endian per SCSI standards.
53 				 * 0x1 -> port#0 can be selected,
54 				 * 0x2 -> port#1 can be selected.
69 #define SISL_MSI_ASYNC_ERROR       3	/* master only - for AFU async error */
151 #define SISL_FC_RC_NOLOGI	0x54	/* port not logged in, in-flight cmds */
154 #define SISL_FC_RC_LINKDOWN	0x57	/* link down, in-flight cmds */
226 /* MMIO space is required to support only 64-bit access */
229  * This AFU has two mechanisms to deal with endian-ness.
231  * below that specifies the endian-ness of the host.
232  * The other is a per context (i.e. application) specification
234  * context is one such application the master context's
235  * endian-ness is set to be the same as the host.
237  * As per the SISlite spec, the MMIO registers are always
249 /* per context host transport MMIO  */
251 	__be64 endian_ctrl;	/* Per context Endian Control. The AFU will
252 				 * operate on whatever the context is of the
257 				 * Only recovery in a PERM_ERR is a context
300 	__be64 sq_ctx_reset;	/* Submission Queue Context Reset (R/W)	      */
303 /* per context provisioning & control MMIO */
433 #define CXLFLASH_NUM_FC_PORTS_PER_BANK	2	/* fixed # of ports per bank */
437 #define CXLFLASH_MAX_CONTEXT	512	/* number of contexts per AFU */
438 #define CXLFLASH_NUM_VLUNS	512	/* number of vluns per AFU/port */
439 #define CXLFLASH_NUM_REGS	512	/* number of registers per port */
454 	struct fc_port_bank bank[CXLFLASH_MAX_FC_BANKS]; /* pages 2 - 9 */
456 	/* pages 10 - 15 are reserved */
463  *	+-------------------------------+
465  *	|        (per context)          |
467  *	+-------------------------------+
468  *	|    512 * 128 B per context    |
471  *	+-------------------------------+
474  *	+-------------------------------+
494  * LXT - LBA Translation Table
507  * RHT - Resource Handle Table
508  * Per the SISlite spec, RHT entries are to be 16-byte aligned
553 #define PORT_MASK(_n)	((1 << (_n)) - 1)