Lines Matching +full:0 +full:x0000000f
33 * #define example_bit_field_MASK 0x03
44 * bf_set(example_bit_field, &t1, 0);
68 #define lpfc_sli_intf_valid_MASK 0x00000007
72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
82 #define lpfc_sli_intf_if_type_MASK 0x0000000F
84 #define LPFC_SLI_INTF_IF_TYPE_0 0
89 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
91 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
92 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
93 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
94 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
96 #define lpfc_sli_intf_slirev_MASK 0x0000000F
100 #define lpfc_sli_intf_func_type_SHIFT 0
101 #define lpfc_sli_intf_func_type_MASK 0x00000001
103 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
120 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
129 #define LPFC_MBX_ERROR_RANGE 0x4000
130 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
131 #define LPFC_BMBX_BIT1_ADDR_LO 0
134 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
136 #define LPFC_ENTIRE_FCF_DATABASE 0
137 #define LPFC_DFLT_FCF_INDEX 0
140 #define LPFC_VF0 0
174 #define LPFC_PCI_FUNC0 0
181 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
182 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
183 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
184 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
185 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
186 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
188 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
196 #define LPFC_FCP_SCHED_ROUND_ROBIN 0
208 #define LPFC_MIN_CPU_MAP 0
221 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
226 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
229 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
230 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
231 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
232 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
233 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
234 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
235 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
247 #define lpfc_idx_rsrc_rdy_SHIFT 0
248 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
252 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
256 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
260 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
268 #define lpfc_abts_orig_SHIFT 0
269 #define lpfc_abts_orig_MASK 0x00000001
272 #define LPFC_ABTS_UNSOL_INT 0
274 #define lpfc_abts_rxid_SHIFT 0
275 #define lpfc_abts_rxid_MASK 0x0000FFFF
278 #define lpfc_abts_oxid_MASK 0x0000FFFF
281 #define lpfc_vndr_code_SHIFT 0
282 #define lpfc_vndr_code_MASK 0x000000FF
285 #define lpfc_rsn_expln_MASK 0x000000FF
288 #define lpfc_rsn_code_MASK 0x000000FF
299 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
302 #define lpfc_eqe_minor_code_MASK 0x00000FFF
305 #define lpfc_eqe_major_code_MASK 0x00000007
307 #define lpfc_eqe_valid_SHIFT 0
308 #define lpfc_eqe_valid_MASK 0x00000001
319 #define lpfc_cqe_valid_MASK 0x00000001
322 #define lpfc_cqe_code_MASK 0x000000FF
327 #define CQE_STATUS_SUCCESS 0x0
328 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
329 #define CQE_STATUS_REMOTE_STOP 0x2
330 #define CQE_STATUS_LOCAL_REJECT 0x3
331 #define CQE_STATUS_NPORT_RJT 0x4
332 #define CQE_STATUS_FABRIC_RJT 0x5
333 #define CQE_STATUS_NPORT_BSY 0x6
334 #define CQE_STATUS_FABRIC_BSY 0x7
335 #define CQE_STATUS_INTERMED_RSP 0x8
336 #define CQE_STATUS_LS_RJT 0x9
337 #define CQE_STATUS_CMD_REJECT 0xb
338 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
339 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
340 #define CQE_STATUS_DI_ERROR 0x16
343 #define LPFC_IOCB_STATUS_MASK 0xf
346 #define CQE_HW_STATUS_NO_ERR 0x0
347 #define CQE_HW_STATUS_UNDERRUN 0x1
348 #define CQE_HW_STATUS_OVERRUN 0x2
351 #define CQE_CODE_COMPL_WQE 0x1
352 #define CQE_CODE_RELEASE_WQE 0x2
353 #define CQE_CODE_RECEIVE 0x4
354 #define CQE_CODE_XRI_ABORTED 0x5
355 #define CQE_CODE_RECEIVE_V1 0x9
356 #define CQE_CODE_NVME_ERSP 0xd
360 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
362 #define WCQE_PARAM_MASK 0x1FF
368 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
371 #define lpfc_wcqe_c_status_MASK 0x000000FF
373 #define lpfc_wcqe_c_hw_status_SHIFT 0
374 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
376 #define lpfc_wcqe_c_ersp0_SHIFT 0
377 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
382 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
385 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
388 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
391 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
393 #define lpfc_wcqe_c_bg_ge_SHIFT 0
394 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
401 #define lpfc_wcqe_c_xb_MASK 0x00000001
404 #define lpfc_wcqe_c_pv_MASK 0x00000001
407 #define lpfc_wcqe_c_priority_MASK 0x00000007
412 #define lpfc_wcqe_c_sqhead_SHIFT 0
413 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
423 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
425 #define lpfc_wcqe_r_wqe_index_SHIFT 0
426 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
440 #define lpfc_wcqe_xa_status_MASK 0x000000FF
445 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
447 #define lpfc_wcqe_xa_xri_SHIFT 0
448 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
455 #define lpfc_wcqe_xa_ia_MASK 0x00000001
457 #define CQE_XRI_ABORTED_IA_REMOTE 0
460 #define lpfc_wcqe_xa_br_MASK 0x00000001
462 #define CQE_XRI_ABORTED_BR_BA_ACC 0
465 #define lpfc_wcqe_xa_eo_MASK 0x00000001
467 #define CQE_XRI_ABORTED_EO_REMOTE 0
478 #define lpfc_rcqe_bindex_MASK 0x0000FFF
481 #define lpfc_rcqe_status_MASK 0x000000FF
483 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
484 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
485 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
486 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
488 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
489 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
493 #define lpfc_rcqe_length_MASK 0x0000FFFF
496 #define lpfc_rcqe_rq_id_MASK 0x000003FF
498 #define lpfc_rcqe_fcf_id_SHIFT 0
499 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
501 #define lpfc_rcqe_rq_id_v1_SHIFT 0
502 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
509 #define lpfc_rcqe_port_MASK 0x00000001
512 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
518 #define lpfc_rcqe_eof_MASK 0x000000FF
520 #define FCOE_EOFn 0x41
521 #define FCOE_EOFt 0x42
522 #define FCOE_EOFni 0x49
523 #define FCOE_EOFa 0x50
524 #define lpfc_rcqe_sof_SHIFT 0
525 #define lpfc_rcqe_sof_MASK 0x000000FF
527 #define FCOE_SOFi2 0x2d
528 #define FCOE_SOFi3 0x2e
529 #define FCOE_SOFn2 0x35
530 #define FCOE_SOFn3 0x36
544 #define lpfc_bde4_last_MASK 0x00000001
546 #define lpfc_bde4_sge_offset_SHIFT 0
547 #define lpfc_bde4_sge_offset_MASK 0x000003FF
550 #define lpfc_bde4_length_SHIFT 0
551 #define lpfc_bde4_length_MASK 0x000000FF
559 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
560 #define LPFC_PORT_SEM_MASK 0xF000
561 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
562 #define LPFC_UERR_STATUS_HI 0x00A4
563 #define LPFC_UERR_STATUS_LO 0x00A0
564 #define LPFC_UE_MASK_HI 0x00AC
565 #define LPFC_UE_MASK_LO 0x00A8
567 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
568 #define LPFC_SLI_INTF 0x0058
569 #define LPFC_SLI_ASIC_VER 0x009C
571 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
573 #define lpfc_port_smphr_perr_MASK 0x1
576 #define lpfc_port_smphr_sfi_MASK 0x1
579 #define lpfc_port_smphr_nip_MASK 0x1
582 #define lpfc_port_smphr_ipc_MASK 0x1
585 #define lpfc_port_smphr_scr1_MASK 0x1
588 #define lpfc_port_smphr_scr2_MASK 0x1
591 #define lpfc_port_smphr_host_scratch_MASK 0xFF
593 #define lpfc_port_smphr_port_status_SHIFT 0
594 #define lpfc_port_smphr_port_status_MASK 0xFFFF
597 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
598 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
599 #define LPFC_POST_STAGE_HOST_RDY 0x0002
600 #define LPFC_POST_STAGE_BE_RESET 0x0003
601 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
602 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
603 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
604 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
605 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
606 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
607 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
608 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
609 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
610 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
611 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
612 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
613 #define LPFC_POST_STAGE_ARMFW_START 0x0800
614 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
615 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
616 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
617 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
618 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
619 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
620 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
621 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
622 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
623 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
624 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
625 #define LPFC_POST_STAGE_RC_DONE 0x0B07
626 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
627 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
628 #define LPFC_POST_STAGE_PORT_READY 0xC000
629 #define LPFC_POST_STAGE_PORT_UE 0xF000
631 #define LPFC_CTL_PORT_STA_OFFSET 0x404
633 #define lpfc_sliport_status_err_MASK 0x1
636 #define lpfc_sliport_status_end_MASK 0x1
639 #define lpfc_sliport_status_oti_MASK 0x1
642 #define lpfc_sliport_status_rn_MASK 0x1
645 #define lpfc_sliport_status_rdy_MASK 0x1
649 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
651 #define lpfc_sliport_ctrl_end_MASK 0x1
653 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
656 #define lpfc_sliport_ctrl_ip_MASK 0x1
660 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
661 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
663 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
665 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
667 #define lpfc_sliport_eqdelay_id_SHIFT 0
668 #define lpfc_sliport_eqdelay_id_MASK 0xfff
672 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
675 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
677 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
678 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
680 #define LPFC_HST_ISR0 0x0C18
681 #define LPFC_HST_ISR1 0x0C1C
682 #define LPFC_HST_ISR2 0x0C20
683 #define LPFC_HST_ISR3 0x0C24
684 #define LPFC_HST_ISR4 0x0C28
686 #define LPFC_HST_IMR0 0x0C48
687 #define LPFC_HST_IMR1 0x0C4C
688 #define LPFC_HST_IMR2 0x0C50
689 #define LPFC_HST_IMR3 0x0C54
690 #define LPFC_HST_IMR4 0x0C58
692 #define LPFC_HST_ISCR0 0x0C78
693 #define LPFC_HST_ISCR1 0x0C7C
694 #define LPFC_HST_ISCR2 0x0C80
695 #define LPFC_HST_ISCR3 0x0C84
696 #define LPFC_HST_ISCR4 0x0C88
734 * value. For UCNA ports running SLI4 and if_type 0, they reside in
740 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
741 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
742 #define LPFC_IF6_RQ_DOORBELL 0x0080
744 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
747 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
749 #define lpfc_rq_db_list_fm_id_SHIFT 0
750 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
753 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
755 #define lpfc_rq_db_ring_fm_id_SHIFT 0
756 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
759 #define LPFC_ULP0_WQ_DOORBELL 0x0040
760 #define LPFC_ULP1_WQ_DOORBELL 0x0060
762 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
765 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
767 #define lpfc_wq_db_list_fm_id_SHIFT 0
768 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
771 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
773 #define lpfc_wq_db_ring_fm_id_SHIFT 0
774 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
777 #define LPFC_IF6_WQ_DOORBELL 0x0040
779 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF
782 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001
785 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F
787 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0
788 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF
791 #define LPFC_EQCQ_DOORBELL 0x0120
793 #define lpfc_eqcq_doorbell_se_MASK 0x0001
795 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
798 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
801 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
804 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
806 #define LPFC_QUEUE_TYPE_COMPLETION 0
809 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
811 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
812 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
815 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
817 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
818 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
821 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
826 #define LPFC_IF6_CQ_DOORBELL 0x00C0
828 #define lpfc_if6_cq_doorbell_se_MASK 0x0001
830 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0
833 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001
836 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF
838 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0
839 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF
842 #define LPFC_IF6_EQ_DOORBELL 0x0120
844 #define lpfc_if6_eq_doorbell_io_MASK 0x0001
846 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0
849 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001
852 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF
854 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0
855 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF
858 #define LPFC_BMBX 0x0160
860 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
863 #define lpfc_bmbx_hi_MASK 0x0001
865 #define lpfc_bmbx_rdy_SHIFT 0
866 #define lpfc_bmbx_rdy_MASK 0x0001
869 #define LPFC_MQ_DOORBELL 0x0140
870 #define LPFC_IF6_MQ_DOORBELL 0x0160
872 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
874 #define lpfc_mq_doorbell_id_SHIFT 0
875 #define lpfc_mq_doorbell_id_MASK 0xFFFF
880 #define lpfc_mbox_hdr_emb_SHIFT 0
881 #define lpfc_mbox_hdr_emb_MASK 0x00000001
884 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
895 #define lpfc_mbox_hdr_opcode_SHIFT 0
896 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
899 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
902 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
905 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
910 #define lpfc_mbox_hdr_version_SHIFT 0
911 #define lpfc_mbox_hdr_version_MASK 0x000000FF
914 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
917 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
921 #define LPFC_Q_CREATE_VERSION_0 0
922 #define LPFC_OPCODE_VERSION_0 0
927 #define lpfc_mbox_hdr_opcode_SHIFT 0
928 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
931 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
934 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
937 #define lpfc_mbox_hdr_status_SHIFT 0
938 #define lpfc_mbox_hdr_status_MASK 0x000000FF
941 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
960 #define LPFC_EXTENT_LOCAL 0
961 #define LPFC_TIMEOUT_DEFAULT 0
962 #define LPFC_EXTENT_VERSION_DEFAULT 0
965 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
966 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
967 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
972 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
973 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
976 #define LPFC_MBOX_OPCODE_NA 0x00
977 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
978 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
979 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
980 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
981 #define LPFC_MBOX_OPCODE_NOP 0x21
982 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
983 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
984 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
985 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
986 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
987 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
988 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
989 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
990 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
991 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
992 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
993 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
994 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
995 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
996 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
997 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
998 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
999 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
1000 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
1001 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
1002 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
1003 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
1004 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
1005 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
1006 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
1007 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
1008 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
1009 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
1010 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
1011 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
1012 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
1013 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
1014 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
1017 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
1018 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
1019 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
1020 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
1021 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
1022 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
1023 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
1024 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
1025 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
1026 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
1027 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
1028 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
1029 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
1030 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
1031 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
1037 #define lpfc_eq_context_size_MASK 0x00000001
1039 #define LPFC_EQE_SIZE_4 0x0
1040 #define LPFC_EQE_SIZE_16 0x1
1042 #define lpfc_eq_context_valid_MASK 0x00000001
1045 #define lpfc_eq_context_autovalid_MASK 0x00000001
1049 #define lpfc_eq_context_count_MASK 0x00000003
1051 #define LPFC_EQ_CNT_256 0x0
1052 #define LPFC_EQ_CNT_512 0x1
1053 #define LPFC_EQ_CNT_1024 0x2
1054 #define LPFC_EQ_CNT_2048 0x3
1055 #define LPFC_EQ_CNT_4096 0x4
1058 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1080 #define lpfc_post_sgl_pages_xri_SHIFT 0
1081 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1084 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1117 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1118 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1125 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1126 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1150 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1151 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1168 #define lpfc_cq_context_event_MASK 0x00000001
1171 #define lpfc_cq_context_valid_MASK 0x00000001
1174 #define lpfc_cq_context_count_MASK 0x00000003
1176 #define LPFC_CQ_CNT_256 0x0
1177 #define LPFC_CQ_CNT_512 0x1
1178 #define LPFC_CQ_CNT_1024 0x2
1179 #define LPFC_CQ_CNT_WORD7 0x3
1181 #define lpfc_cq_context_autovalid_MASK 0x00000001
1184 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1185 #define lpfc_cq_eq_id_MASK 0x000000FF
1187 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1188 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1200 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1202 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1203 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1210 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1211 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1223 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1225 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1226 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1230 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1233 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1236 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1239 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1242 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001
1245 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1248 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1252 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1255 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF
1257 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1258 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1262 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1264 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1265 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1269 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1271 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1272 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1276 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1278 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1279 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1283 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1285 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1286 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1290 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1292 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1293 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1297 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1299 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1300 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1304 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1306 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1307 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1311 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1313 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1314 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1321 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1323 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1324 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1335 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1336 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1355 struct { /* Version 0 Request */
1357 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1358 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1361 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1364 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1368 #define lpfc_mbx_wq_create_bua_SHIFT 0
1369 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1372 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1376 uint32_t word0; /* Word 0 is the same as in v0 */
1378 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1379 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1381 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1383 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001
1386 #define lpfc_mbx_wq_create_doe_MASK 0x00000001
1389 #define lpfc_mbx_wq_create_toe_MASK 0x00000001
1392 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1394 #define LPFC_WQ_WQE_SIZE_64 0x5
1395 #define LPFC_WQ_WQE_SIZE_128 0x6
1397 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1404 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1405 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1409 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1410 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1412 #define WQ_PCI_BAR_0_AND_1 0x00
1413 #define WQ_PCI_BAR_2_AND_3 0x01
1414 #define WQ_PCI_BAR_4_AND_5 0x02
1416 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1422 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001
1424 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0
1425 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF
1428 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0
1429 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F
1434 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F
1436 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0
1437 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F
1449 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1450 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1464 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1465 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1472 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1475 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1482 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1483 #define lpfc_rq_context_page_size_MASK 0x000000FF
1485 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1488 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1490 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1491 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1495 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1497 #define lpfc_rq_context_buf_size_SHIFT 0
1498 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1500 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1501 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1511 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1512 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1515 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1518 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1521 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1529 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1531 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1532 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1536 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1537 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1540 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1551 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1552 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1555 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1558 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1561 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1564 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1567 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1570 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1573 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1581 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1583 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1584 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1588 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1589 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1592 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1603 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1604 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1615 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1616 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1619 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1621 #define LPFC_MQ_RING_SIZE_16 0x5
1622 #define LPFC_MQ_RING_SIZE_32 0x6
1623 #define LPFC_MQ_RING_SIZE_64 0x7
1624 #define LPFC_MQ_RING_SIZE_128 0x8
1627 #define lpfc_mq_context_valid_MASK 0x00000001
1638 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1639 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1646 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1647 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1658 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1659 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1662 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1666 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1668 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1669 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1670 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1671 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1672 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1674 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1677 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1680 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1682 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1683 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1684 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1685 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1686 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1687 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1688 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1690 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1697 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1698 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1702 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1703 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1704 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1712 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1713 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1725 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1726 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1727 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1728 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1735 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1736 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1741 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1742 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1745 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1755 #define LPFC_FC_FCOE 0x00000007
1759 #define LPFC_FCOE_INI_MODE 0x00000040
1760 #define LPFC_FCOE_TGT_MODE 0x00000080
1761 #define LPFC_DUA_MODE 0x00000800
1763 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1764 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1781 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1782 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1785 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1788 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1791 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1796 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF
1803 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1804 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1807 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1816 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1817 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1820 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1822 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1825 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1828 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1842 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1843 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1845 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1846 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1847 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1849 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1852 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1867 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1870 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1873 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1874 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1877 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1880 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1881 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1884 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1915 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1916 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1919 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1924 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1925 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
1949 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
1950 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
1961 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1962 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1965 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1976 #define lpfc_sli4_sge_offset_SHIFT 0
1977 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
1980 #define lpfc_sli4_sge_type_MASK 0x0000000F
1982 #define LPFC_SGE_TYPE_DATA 0x0
1983 #define LPFC_SGE_TYPE_DIF 0x4
1984 #define LPFC_SGE_TYPE_LSP 0x5
1985 #define LPFC_SGE_TYPE_PEDIF 0x6
1986 #define LPFC_SGE_TYPE_PESEED 0x7
1987 #define LPFC_SGE_TYPE_DISEED 0x8
1988 #define LPFC_SGE_TYPE_ENC 0x9
1989 #define LPFC_SGE_TYPE_ATM 0xA
1990 #define LPFC_SGE_TYPE_SKIP 0xC
1992 #define lpfc_sli4_sge_last_MASK 0x00000001
2002 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2003 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
2006 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
2009 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
2012 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
2015 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
2018 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
2021 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
2022 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
2025 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
2028 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
2031 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
2034 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
2037 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
2040 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
2043 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
2046 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
2056 #define lpfc_fcf_record_mac_0_SHIFT 0
2057 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
2060 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
2063 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
2066 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
2069 #define lpfc_fcf_record_mac_4_SHIFT 0
2070 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
2073 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
2076 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
2079 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
2084 #define lpfc_fcf_record_fab_name_0_SHIFT 0
2085 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
2088 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
2091 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2094 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2097 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2098 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2101 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2104 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2107 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2110 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2111 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2114 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2117 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2120 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2123 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2126 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2129 #define lpfc_fcf_record_fcf_index_SHIFT 0
2130 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2133 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2137 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2138 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2141 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2144 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2147 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2150 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2151 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2154 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2157 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2160 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2169 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2170 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2178 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2179 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2186 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2187 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2195 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2196 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2199 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2206 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2207 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2211 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2212 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2217 #define STATUS_SUCCESS 0x0
2218 #define STATUS_FAILED 0x1
2219 #define STATUS_ILLEGAL_REQUEST 0x2
2220 #define STATUS_ILLEGAL_FIELD 0x3
2221 #define STATUS_INSUFFICIENT_BUFFER 0x4
2222 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2223 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2224 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2225 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2226 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2227 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2228 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2229 #define STATUS_ASSERT_FAILED 0x1e
2230 #define STATUS_INVALID_SESSION 0x1f
2231 #define STATUS_INVALID_CONNECTION 0x20
2232 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2233 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2234 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2235 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2236 #define STATUS_FLASHROM_READ_FAILED 0x27
2237 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2238 #define STATUS_ERROR_ACITMAIN 0x2a
2239 #define STATUS_REBOOT_REQUIRED 0x2c
2240 #define STATUS_FCF_IN_USE 0x3a
2241 #define STATUS_FCF_TABLE_EMPTY 0x43
2247 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2248 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB
2249 #define ADD_STATUS_INVALID_REQUEST 0x4B
2258 #define lpfc_init_vfi_vr_MASK 0x00000001
2261 #define lpfc_init_vfi_vt_MASK 0x00000001
2264 #define lpfc_init_vfi_vf_MASK 0x00000001
2267 #define lpfc_init_vfi_vp_MASK 0x00000001
2269 #define lpfc_init_vfi_vfi_SHIFT 0
2270 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2274 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2276 #define lpfc_init_vfi_fcfi_SHIFT 0
2277 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2281 #define lpfc_init_vfi_pri_MASK 0x00000007
2284 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2288 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2291 #define MBX_VFI_IN_USE 0x9F02
2297 #define lpfc_reg_vfi_upd_MASK 0x00000001
2300 #define lpfc_reg_vfi_vp_MASK 0x00000001
2302 #define lpfc_reg_vfi_vfi_SHIFT 0
2303 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2307 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2309 #define lpfc_reg_vfi_fcfi_SHIFT 0
2310 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2317 #define lpfc_reg_vfi_nport_id_SHIFT 0
2318 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2321 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2324 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2331 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2333 #define lpfc_init_vpi_vpi_SHIFT 0
2334 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2341 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2342 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2346 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2347 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2350 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2353 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2356 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2359 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2363 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2364 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2367 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2368 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2371 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2374 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2377 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2380 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2381 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2384 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2387 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2390 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2397 #define lpfc_unreg_vfi_vfi_SHIFT 0
2398 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2404 #define lpfc_resume_rpi_index_SHIFT 0
2405 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2408 #define lpfc_resume_rpi_ii_MASK 0x00000003
2410 #define RESUME_INDEX_RPI 0
2417 #define REG_FCF_INVALID_QID 0xFFFF
2420 #define lpfc_reg_fcfi_info_index_SHIFT 0
2421 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2424 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2427 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2428 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2431 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2434 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2435 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2438 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2442 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2445 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2448 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2450 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2451 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2455 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2458 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2461 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2463 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2464 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2468 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2471 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2474 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2476 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2477 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2481 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2484 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2487 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2489 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2490 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2494 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2496 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2500 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2502 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2503 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2509 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2510 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2513 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2516 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2517 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2520 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2523 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2524 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2527 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2531 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2534 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2537 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2539 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2540 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2544 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2547 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2550 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2552 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2553 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2557 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2560 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2563 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2565 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2566 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2570 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2573 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2576 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2578 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2579 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2583 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2586 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2589 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2592 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2595 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2598 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2601 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2604 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2607 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2610 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2613 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2616 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2619 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2622 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2625 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2628 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2631 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2634 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2637 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2639 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2640 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2644 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2647 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2649 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2650 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2664 #define lpfc_unreg_fcfi_SHIFT 0
2665 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2672 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2675 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2678 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2680 #define LPFC_PREDCBX_CEE_MODE 0
2683 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2686 #define LPFC_G7_ASIC_1 0xd
2691 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2692 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2695 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2698 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2701 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2710 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2711 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2722 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2725 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2726 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2729 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2731 #define LPFC_LNK_TYPE_GE 0
2734 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2737 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2741 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2742 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2746 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2747 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2750 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2754 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2755 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2758 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2761 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2764 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2765 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2770 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2771 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2774 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2777 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2778 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2781 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2784 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2785 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2788 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2791 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2792 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2795 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2799 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2802 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2803 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2806 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2809 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2810 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2813 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2819 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2820 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2823 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2824 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2827 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2830 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2833 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2836 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2839 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2842 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2845 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2848 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
2851 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2854 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
2857 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2858 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2861 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2864 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2867 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2870 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2873 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2876 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2879 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2882 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2885 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
2891 #define qs_SHIFT 0
2892 #define qs_MASK 0x00000001
2895 #define wr_MASK 0x00000001
2898 #define pf_MASK 0x000000ff
2901 #define cpn_MASK 0x000000ff
2904 #define list_offset_SHIFT 0
2905 #define list_offset_MASK 0x000000ff
2908 #define next_offset_MASK 0x000000ff
2911 #define elem_cnt_MASK 0x000000ff
2915 #define pn_0_MASK 0x000000ff
2918 #define pn_1_MASK 0x000000ff
2921 #define pn_2_MASK 0x000000ff
2923 #define pn_3_SHIFT 0
2924 #define pn_3_MASK 0x000000ff
2928 #define pn_4_MASK 0x000000ff
2931 #define pn_5_MASK 0x000000ff
2934 #define pn_6_MASK 0x000000ff
2936 #define pn_7_SHIFT 0
2937 #define pn_7_MASK 0x000000ff
2940 #define LPFC_SUPP_PAGES 0
2947 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
2948 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
2951 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
2954 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
2955 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
2958 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
2961 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
2962 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
2969 #define DMP_PAGE_A0 0xa0
2970 #define DMP_PAGE_A2 0xa2
2981 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
2982 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
2983 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
2984 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
2985 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
2986 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
2987 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
2988 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
2989 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
2990 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
2991 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
2992 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
2993 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
2994 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
2995 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
2996 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
3000 #define SSF_IDENTIFIER 0
3041 #define SSF_TEMP_HIGH_ALARM 0
3163 #define qs_SHIFT 0
3164 #define qs_MASK 0x00000001
3167 #define wr_MASK 0x00000001
3170 #define pf_MASK 0x000000ff
3173 #define cpn_MASK 0x000000ff
3176 #define if_type_SHIFT 0
3177 #define if_type_MASK 0x00000007
3180 #define sli_rev_MASK 0x0000000f
3183 #define sli_family_MASK 0x000000ff
3186 #define featurelevel_1_MASK 0x000000ff
3189 #define featurelevel_2_MASK 0x0000001f
3192 #define fcoe_SHIFT 0
3193 #define fcoe_MASK 0x00000001
3196 #define fc_MASK 0x00000001
3199 #define nic_MASK 0x00000001
3202 #define iscsi_MASK 0x00000001
3205 #define rdma_MASK 0x00000001
3210 #define if_page_sz_SHIFT 0
3211 #define if_page_sz_MASK 0x0000ffff
3214 #define loopbk_scope_MASK 0x0000000f
3217 #define rq_db_window_MASK 0x0000000f
3220 #define eq_pages_SHIFT 0
3221 #define eq_pages_MASK 0x0000000f
3224 #define eqe_size_MASK 0x000000ff
3227 #define cq_pages_SHIFT 0
3228 #define cq_pages_MASK 0x0000000f
3231 #define cqe_size_MASK 0x000000ff
3234 #define mq_pages_SHIFT 0
3235 #define mq_pages_MASK 0x0000000f
3238 #define mqe_size_MASK 0x000000ff
3241 #define mq_elem_cnt_MASK 0x000000ff
3244 #define wq_pages_SHIFT 0
3245 #define wq_pages_MASK 0x0000ffff
3248 #define wqe_size_MASK 0x000000ff
3251 #define rq_pages_SHIFT 0
3252 #define rq_pages_MASK 0x0000ffff
3255 #define rqe_size_MASK 0x000000ff
3258 #define hdr_pages_SHIFT 0
3259 #define hdr_pages_MASK 0x0000000f
3262 #define hdr_size_MASK 0x0000000f
3265 #define hdr_pp_align_MASK 0x0000ffff
3268 #define sgl_pages_SHIFT 0
3269 #define sgl_pages_MASK 0x0000000f
3272 #define sgl_pp_align_MASK 0x0000ffff
3281 #define cfg_prot_type_SHIFT 0
3282 #define cfg_prot_type_MASK 0x000000FF
3285 #define cfg_ft_SHIFT 0
3286 #define cfg_ft_MASK 0x00000001
3289 #define cfg_sli_rev_MASK 0x0000000f
3292 #define cfg_sli_family_MASK 0x0000000f
3295 #define cfg_if_type_MASK 0x0000000f
3298 #define cfg_sli_hint_1_MASK 0x000000ff
3301 #define cfg_sli_hint_2_MASK 0x0000001f
3305 #define cfg_eqav_MASK 0x00000001
3310 #define cfg_cqv_MASK 0x00000003
3313 #define cfg_cqpsize_MASK 0x000000ff
3316 #define cfg_cqav_MASK 0x00000001
3321 #define cfg_mqv_MASK 0x00000003
3325 #define cfg_wqpcnt_SHIFT 0
3326 #define cfg_wqpcnt_MASK 0x0000000f
3329 #define cfg_wqsize_MASK 0x0000000f
3332 #define cfg_wqv_MASK 0x00000003
3335 #define cfg_wqpsize_MASK 0x000000ff
3340 #define cfg_rqv_MASK 0x00000003
3344 #define cfg_rq_db_window_MASK 0x0000000f
3347 #define cfg_fcoe_SHIFT 0
3348 #define cfg_fcoe_MASK 0x00000001
3351 #define cfg_ext_MASK 0x00000001
3354 #define cfg_hdrr_MASK 0x00000001
3357 #define cfg_phwq_MASK 0x00000001
3360 #define cfg_oas_MASK 0x00000001
3363 #define cfg_loopbk_scope_MASK 0x0000000f
3367 #define cfg_sgl_page_cnt_SHIFT 0
3368 #define cfg_sgl_page_cnt_MASK 0x0000000f
3371 #define cfg_sgl_page_size_MASK 0x000000ff
3374 #define cfg_sgl_pp_align_MASK 0x000000ff
3381 #define cfg_ext_embed_cb_SHIFT 0
3382 #define cfg_ext_embed_cb_MASK 0x00000001
3385 #define cfg_mds_diags_MASK 0x00000001
3388 #define cfg_nvme_MASK 0x00000001
3391 #define cfg_xib_MASK 0x00000001
3394 #define cfg_eqdr_MASK 0x00000001
3397 #define cfg_nosr_MASK 0x00000001
3401 #define cfg_bv1s_MASK 0x00000001
3405 #define cfg_max_tow_xri_SHIFT 0
3406 #define cfg_max_tow_xri_MASK 0x0000ffff
3414 #define cfg_frag_field_offset_SHIFT 0
3415 #define cfg_frag_field_offset_MASK 0x0000ffff
3419 #define cfg_frag_field_size_MASK 0x0000ffff
3423 #define cfg_sgl_field_offset_SHIFT 0
3424 #define cfg_sgl_field_offset_MASK 0x0000ffff
3428 #define cfg_sgl_field_size_MASK 0x0000ffff
3436 #define LPFC_SET_UE_RECOVERY 0x10
3437 #define LPFC_SET_MDS_DIAGS 0x11
3443 #define lpfc_mbx_set_feature_UER_SHIFT 0
3444 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3446 #define lpfc_mbx_set_feature_mds_SHIFT 0
3447 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3450 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3453 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3454 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3457 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3462 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3484 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3485 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3487 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3489 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3492 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3493 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3497 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3498 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3501 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3504 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3507 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3508 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3514 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3515 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3517 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3519 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3521 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3525 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3526 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3529 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3532 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3533 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3536 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3539 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3540 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3543 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3546 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3547 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3550 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3553 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3554 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3557 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3567 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3568 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3571 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3574 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3577 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3580 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3598 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3599 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3600 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3612 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3613 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3614 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3618 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3619 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3622 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3636 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3637 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3640 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3657 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3658 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3661 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3664 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3668 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3669 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3672 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3675 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3678 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3679 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3682 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3685 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3686 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3689 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3692 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3695 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3698 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3705 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3706 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3709 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3712 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3713 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3716 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3719 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3720 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3723 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3726 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3729 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3733 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3734 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3749 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3750 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3755 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3756 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3759 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3762 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3765 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3767 #define LPFC_LINK_NUMBER_0 0
3776 #define MB_CQE_STATUS_SUCCESS 0x0
3777 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3778 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3779 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3780 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3781 #define MB_CQE_STATUS_DMA_FAILED 0x5
3790 #define lpfc_wr_object_eof_MASK 0x00000001
3792 #define lpfc_wr_object_write_length_SHIFT 0
3793 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3810 #define lpfc_mqe_status_MASK 0x0000FFFF
3813 #define lpfc_mqe_command_MASK 0x000000FF
3876 #define lpfc_mcqe_status_SHIFT 0
3877 #define lpfc_mcqe_status_MASK 0x0000FFFF
3880 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
3886 #define lpfc_trailer_valid_MASK 0x00000001
3889 #define lpfc_trailer_async_MASK 0x00000001
3892 #define lpfc_trailer_hpi_MASK 0x00000001
3895 #define lpfc_trailer_completed_MASK 0x00000001
3898 #define lpfc_trailer_consumed_MASK 0x00000001
3901 #define lpfc_trailer_type_MASK 0x000000FF
3904 #define lpfc_trailer_code_MASK 0x000000FF
3906 #define LPFC_TRAILER_CODE_LINK 0x1
3907 #define LPFC_TRAILER_CODE_FCOE 0x2
3908 #define LPFC_TRAILER_CODE_DCBX 0x3
3909 #define LPFC_TRAILER_CODE_GRP5 0x5
3910 #define LPFC_TRAILER_CODE_FC 0x10
3911 #define LPFC_TRAILER_CODE_SLI 0x11
3917 #define lpfc_acqe_link_speed_MASK 0x000000FF
3919 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
3920 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
3921 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
3922 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
3923 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
3924 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
3925 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
3926 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
3927 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
3929 #define lpfc_acqe_link_duplex_MASK 0x000000FF
3931 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
3932 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
3933 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
3935 #define lpfc_acqe_link_status_MASK 0x000000FF
3937 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
3938 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
3939 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
3940 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
3942 #define lpfc_acqe_link_type_MASK 0x00000003
3944 #define lpfc_acqe_link_number_SHIFT 0
3945 #define lpfc_acqe_link_number_MASK 0x0000003F
3948 #define lpfc_acqe_link_fault_SHIFT 0
3949 #define lpfc_acqe_link_fault_MASK 0x000000FF
3951 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
3952 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
3953 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
3954 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3
3956 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
3960 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
3961 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
3967 #define lpfc_acqe_fip_fcf_count_SHIFT 0
3968 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
3971 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
3975 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
3976 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
3977 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
3978 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
3979 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
3992 #define lpfc_acqe_grp5_type_MASK 0x00000003
3994 #define lpfc_acqe_grp5_number_SHIFT 0
3995 #define lpfc_acqe_grp5_number_MASK 0x0000003F
3999 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
4008 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
4010 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
4011 #define LPFC_FC_LA_SPEED_1G 0x1
4012 #define LPFC_FC_LA_SPEED_2G 0x2
4013 #define LPFC_FC_LA_SPEED_4G 0x4
4014 #define LPFC_FC_LA_SPEED_8G 0x8
4015 #define LPFC_FC_LA_SPEED_10G 0xA
4016 #define LPFC_FC_LA_SPEED_16G 0x10
4017 #define LPFC_FC_LA_SPEED_32G 0x20
4018 #define LPFC_FC_LA_SPEED_64G 0x21
4019 #define LPFC_FC_LA_SPEED_128G 0x22
4020 #define LPFC_FC_LA_SPEED_256G 0x23
4022 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
4024 #define LPFC_FC_LA_TOP_UNKOWN 0x0
4025 #define LPFC_FC_LA_TOP_P2P 0x1
4026 #define LPFC_FC_LA_TOP_FCAL 0x2
4027 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
4028 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
4030 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
4032 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
4033 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
4034 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
4035 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
4036 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
4037 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
4039 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
4041 #define LPFC_LINK_TYPE_ETHERNET 0x0
4042 #define LPFC_LINK_TYPE_FC 0x1
4043 #define lpfc_acqe_fc_la_port_number_SHIFT 0
4044 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
4048 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
4050 #define lpfc_acqe_fc_la_fault_SHIFT 0
4051 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
4053 #define LPFC_FC_LA_FAULT_NONE 0x0
4054 #define LPFC_FC_LA_FAULT_LOCAL 0x1
4055 #define LPFC_FC_LA_FAULT_REMOTE 0x2
4058 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
4059 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
4065 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
4066 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
4069 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
4072 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
4075 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
4078 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
4079 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
4082 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
4085 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
4088 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
4091 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
4094 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
4097 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
4100 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
4103 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
4104 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
4105 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
4106 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
4107 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
4108 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
4116 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
4117 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
4118 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
4119 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
4120 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
4121 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
4122 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
4139 #define NO_XRI 0xffff
4143 #define wqe_xri_tag_SHIFT 0
4144 #define wqe_xri_tag_MASK 0x0000FFFF
4147 #define wqe_ctxt_tag_MASK 0x0000FFFF
4150 #define wqe_dif_SHIFT 0
4151 #define wqe_dif_MASK 0x00000003
4157 #define wqe_ct_MASK 0x00000003
4160 #define wqe_status_MASK 0x0000000f
4163 #define wqe_cmnd_MASK 0x000000ff
4166 #define wqe_class_MASK 0x00000007
4169 #define wqe_ar_MASK 0x00000001
4175 #define wqe_pu_MASK 0x00000003
4178 #define wqe_erp_MASK 0x00000001
4184 #define wqe_lnk_MASK 0x00000001
4187 #define wqe_tmo_MASK 0x000000ff
4191 #define wqe_reqtag_SHIFT 0
4192 #define wqe_reqtag_MASK 0x0000FFFF
4195 #define wqe_temp_rpi_MASK 0x0000FFFF
4198 #define wqe_rcvoxid_MASK 0x0000FFFF
4201 #define wqe_ebde_cnt_SHIFT 0
4202 #define wqe_ebde_cnt_MASK 0x0000000f
4205 #define wqe_nvme_MASK 0x00000001
4208 #define wqe_oas_MASK 0x00000001
4211 #define wqe_lenloc_MASK 0x00000003
4213 #define LPFC_WQE_LENLOC_NONE 0
4218 #define wqe_qosd_MASK 0x00000001
4221 #define wqe_xbl_MASK 0x00000001
4224 #define wqe_iod_MASK 0x00000001
4226 #define LPFC_WQE_IOD_NONE 0
4227 #define LPFC_WQE_IOD_WRITE 0
4230 #define wqe_dbde_MASK 0x00000001
4233 #define wqe_wqes_MASK 0x00000001
4237 #define wqe_wqid_MASK 0x00007fff
4240 #define wqe_pri_MASK 0x00000007
4243 #define wqe_pv_MASK 0x00000001
4246 #define wqe_xc_MASK 0x00000001
4249 #define wqe_sr_MASK 0x00000001
4252 #define wqe_ccpe_MASK 0x00000001
4255 #define wqe_ccp_MASK 0x000000ff
4258 #define wqe_cmd_type_SHIFT 0
4259 #define wqe_cmd_type_MASK 0x0000000f
4262 #define wqe_els_id_MASK 0x00000003
4267 #define LPFC_ELS_ID_DEFAULT 0
4269 #define wqe_irsp_MASK 0x00000001
4272 #define wqe_pbde_MASK 0x00000001
4275 #define wqe_sup_MASK 0x00000001
4278 #define wqe_wqec_MASK 0x00000001
4281 #define wqe_irsplen_MASK 0x0000000f
4284 #define wqe_cqid_MASK 0x0000ffff
4286 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4291 #define wqe_els_did_SHIFT 0
4292 #define wqe_els_did_MASK 0x00FFFFFF
4295 #define wqe_xmit_bls_pt_MASK 0x00000003
4298 #define wqe_xmit_bls_ar_MASK 0x00000001
4301 #define wqe_xmit_bls_xo_MASK 0x00000001
4318 #define els_req64_sid_SHIFT 0
4319 #define els_req64_sid_MASK 0x00FFFFFF
4322 #define els_req64_sp_MASK 0x00000001
4325 #define els_req64_vf_MASK 0x00000001
4331 #define els_req64_vfid_MASK 0x00000FFF
4334 #define els_req64_pri_MASK 0x00000007
4338 #define els_req64_hopcnt_MASK 0x000000ff
4348 #define els_rsp64_sid_SHIFT 0
4349 #define els_rsp64_sid_MASK 0x00FFFFFF
4352 #define els_rsp64_sp_MASK 0x00000001
4357 #define wqe_rsp_temp_rpi_SHIFT 0
4358 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4367 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4370 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4373 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4374 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4377 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4380 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4383 #define xmit_bls_rsp64_rxid_SHIFT 0
4384 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4387 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4390 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4391 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4394 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4401 #define xmit_bls_rsp64_temprpi_SHIFT 0
4402 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4410 #define wqe_si_MASK 0x000000001
4413 #define wqe_la_MASK 0x000000001
4416 #define wqe_xo_MASK 0x000000001
4419 #define wqe_ls_MASK 0x000000001
4422 #define wqe_dfctl_MASK 0x0000000ff
4425 #define wqe_type_MASK 0x0000000ff
4428 #define wqe_rctl_MASK 0x0000000ff
4468 #define prli_acc_rsp_code_MASK 0x0000000f
4471 #define prli_estabImagePair_MASK 0x00000001
4474 #define prli_type_code_ext_MASK 0x000000ff
4477 #define prli_type_code_MASK 0x000000ff
4482 #define prli_fba_SHIFT 0
4483 #define prli_fba_MASK 0x00000001
4486 #define prli_disc_MASK 0x00000001
4489 #define prli_tgt_MASK 0x00000001
4492 #define prli_init_MASK 0x00000001
4495 #define prli_conf_MASK 0x00000001
4498 #define prli_fb_sz_SHIFT 0
4499 #define prli_fb_sz_MASK 0x0000ffff
4505 uint32_t rsrvd[5]; /* words 0-4 */
4517 #define abort_cmd_ia_SHIFT 0
4518 #define abort_cmd_ia_MASK 0x000000001
4521 #define abort_cmd_criteria_MASK 0x0000000ff
4533 #define cmd_buff_len_MASK 0x00000ffff
4535 #define payload_offset_len_SHIFT 0
4536 #define payload_offset_len_MASK 0x0000ffff
4549 #define cmd_buff_len_MASK 0x00000ffff
4551 #define payload_offset_len_SHIFT 0
4552 #define payload_offset_len_MASK 0x0000ffff
4562 struct ulp_bde64 bde; /* words 0-2 */
4565 #define cmd_buff_len_MASK 0x00000ffff
4567 #define payload_offset_len_SHIFT 0
4568 #define payload_offset_len_MASK 0x0000ffff
4605 #define CMD_SEND_FRAME 0xE1
4608 struct ulp_bde64 bde; /* words 0-2 */
4659 #define MAGIC_NUMER_G6 0xFEAA0003
4660 #define MAGIC_NUMER_G7 0xFEAA0005
4667 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4670 #define lpfc_grp_hdr_id_MASK 0x000000FF
4678 #define FCP_COMMAND 0x0
4679 #define NVME_READ_CMD 0x0
4680 #define FCP_COMMAND_DATA_OUT 0x1
4681 #define NVME_WRITE_CMD 0x1
4682 #define FCP_COMMAND_TRECEIVE 0x2
4683 #define FCP_COMMAND_TRSP 0x3
4684 #define FCP_COMMAND_TSEND 0x7
4685 #define OTHER_COMMAND 0x8
4686 #define ELS_COMMAND_NON_FIP 0xC
4687 #define ELS_COMMAND_FIP 0xD
4689 #define LPFC_NVME_EMBED_CMD 0x0
4690 #define LPFC_NVME_EMBED_WRITE 0x1
4691 #define LPFC_NVME_EMBED_READ 0x2
4694 #define CMD_ABORT_XRI_WQE 0x0F
4695 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4696 #define CMD_XMIT_BCAST64_WQE 0x84
4697 #define CMD_ELS_REQUEST64_WQE 0x8A
4698 #define CMD_XMIT_ELS_RSP64_WQE 0x95
4699 #define CMD_XMIT_BLS_RSP64_WQE 0x97
4700 #define CMD_FCP_IWRITE64_WQE 0x98
4701 #define CMD_FCP_IREAD64_WQE 0x9A
4702 #define CMD_FCP_ICMND64_WQE 0x9C
4703 #define CMD_FCP_TSEND64_WQE 0x9F
4704 #define CMD_FCP_TRECEIVE64_WQE 0xA1
4705 #define CMD_FCP_TRSP64_WQE 0xA3
4706 #define CMD_GEN_REQUEST64_WQE 0xC2
4708 #define CMD_WQE_MASK 0xff