Lines Matching +full:0 +full:xf007
24 #define PCI_VENDOR_ID_IODATA 0x10fc
25 #define PCI_VENDOR_ID_WORKBIT 0x1145
27 #define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
28 #define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
29 #define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
30 #define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
31 #define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
32 #define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
33 #define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
34 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
35 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
41 MODEL_IODATA = 0,
64 #define EXTENDED_SDTR_LEN 0x03
77 # define FALSE 0
80 #define NEGATE 0
88 * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
90 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
91 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
92 # define IRQSTATUS_LATCHED_MSG BIT(0)
121 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
122 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
123 # define CB_MMIO_MODE BIT(0)
139 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
141 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
142 # define TIMER_CNT_MASK (0xff)
145 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
146 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
148 #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
149 # define FIFO_REST_MASK 0x1ff
153 #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
154 # define SREQSMPLRATE_RATE0 BIT(0)
157 # define SMPL_40M (0) /* 40MHz: 0-100ns/period */
161 #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
162 # define BUSCTL_SEL BIT(0)
171 #define CLR_COUNTER 0x12 /* BASE+12, B, W */
172 # define ACK_COUNTER_CLR BIT(0)
185 #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
186 # define BUSMON_MSG BIT(0)
195 #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
197 #define PARITY_CONTROL 0x16 /* BASE+16, B, W */
198 # define PARITY_CHECK_ENABLE BIT(0)
200 #define PARITY_STATUS 0x16 /* BASE+16, B, R */
201 //# define PARITY_CHECK_ENABLE BIT(0)
206 #define RESELECT_ID 0x18 /* BASE+18, B, R */
208 #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
209 # define CLEAR_CDB_FIFO_POINTER BIT(0)
219 #define SET_ARBIT 0x1a /* BASE+1a, B, W */
220 # define ARBIT_GO BIT(0)
223 #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
224 //# define ARBIT_GO BIT(0)
230 #define SYNC_REG 0x1c /* BASE+1c, B, R/W */
232 #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
234 #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
235 #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
236 #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
238 #define SCAM_CONTROL 0x24 /* BASE+24, B, W */
239 #define SCAM_STATUS 0x24 /* BASE+24, B, R */
240 # define SCAM_MSG BIT(0)
247 #define SCAM_DATA 0x26 /* BASE+26, B, R/W */
248 # define SD0 BIT(0)
257 #define SACK_CNT 0x28 /* BASE+28, DW, R/W */
258 #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
260 #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
261 #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
262 #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
264 #define BM_CNT 0x38 /* BASE+38, DW, R/W */
265 # define BM_COUNT_MASK 0x0001ffffUL
268 #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
269 #define WAIT_REG 0x40 /* Bi only */
271 #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
272 # define COMMAND_PHASE BIT(0)
288 #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
290 #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
291 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
294 #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
295 #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
297 #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
298 #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
299 #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
300 #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
307 #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
308 # define CLOCK_2 BIT(0) /* MCLK/2 */
312 #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
313 # define BPWR BIT(0)
316 #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
317 #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
318 # define LED_ON (0)
319 # define LED_OFF BIT(0)
321 #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
322 # define IRQSELECT_RESELECT_IRQ BIT(0)
334 #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
335 # define OLD_MSG BIT(0)
340 #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
341 #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
343 #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
344 # define ROM_WRITE_ENB BIT(0)
348 #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
350 #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
352 #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
361 #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
362 #define MISC_RD 0x0c
363 # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
373 #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
374 # define BM_CYCLE0 BIT(0)
384 #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
385 # define SREQ_EDGH_SELECT BIT(0)
387 #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
388 # define REQCNT_UP BIT(0)
394 #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
395 #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
396 #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
397 #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
398 #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
400 #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
401 # define SCL BIT(0)
405 #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
406 #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
407 #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
408 #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
409 #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
410 #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
411 #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
412 #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
413 #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
414 #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
415 #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
416 #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
417 #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
418 #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
424 #define BUSMON_BUS_FREE 0
462 u8 cdb[4 * 0x10]; /* SCSI Command */
482 #define NSP32_TRANSFER_BUSMASTER BIT(0)
493 #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
528 #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
533 #define FAST5M 0x32
534 #define FAST10M 0x19
535 #define ULTRA20M 0x0c
538 #define ASYNC_OFFSET 0 /* asynchronous transfer */
539 #define SYNC_OFFSET 0xf /* synchronous transfer max offset */
544 #define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
549 unsigned char period; /* sync period (0-255) */
550 unsigned char offset; /* sync offset (0-15) */
551 int sync_flag; /* SDTR_*, 0 */
562 #define NSP32_MMIO_OFFSET 0x0800