4  * QE UCC API Set - UCC specific routines implementations.
38 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_set_qe_mux_mii_mng()
39 		return -EINVAL;  in ucc_set_qe_mux_mii_mng()
42 	clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,  in ucc_set_qe_mux_mii_mng()
55  * 'ucc_num' is the UCC number, from 0 - 7.
66 	switch (ucc_num) {  in ucc_set_type()
67 	case 0: guemr = &qe_immr->ucc1.slow.guemr;  in ucc_set_type()
69 	case 1: guemr = &qe_immr->ucc2.slow.guemr;  in ucc_set_type()
71 	case 2: guemr = &qe_immr->ucc3.slow.guemr;  in ucc_set_type()
73 	case 3: guemr = &qe_immr->ucc4.slow.guemr;  in ucc_set_type()
75 	case 4: guemr = &qe_immr->ucc5.slow.guemr;  in ucc_set_type()
77 	case 5: guemr = &qe_immr->ucc6.slow.guemr;  in ucc_set_type()
79 	case 6: guemr = &qe_immr->ucc7.slow.guemr;  in ucc_set_type()
81 	case 7: guemr = &qe_immr->ucc8.slow.guemr;  in ucc_set_type()
84 		return -EINVAL;  in ucc_set_type()
99 	*cmxucr = &qe_immr->qmx.cmxucr[cmx];  in get_cmxucr_reg()
100 	*shift = 16 - 8 * (ucc_num & 2);  in get_cmxucr_reg()
110 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_mux_set_grant_tsa_bkpt()
111 		return -EINVAL;  in ucc_mux_set_grant_tsa_bkpt()
124 	enum comm_dir mode)  in ucc_set_qe_mux_rxtx()  argument
132 	if (ucc_num > UCC_MAX_NUM - 1)  in ucc_set_qe_mux_rxtx()
133 		return -EINVAL;  in ucc_set_qe_mux_rxtx()
136 	if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))  in ucc_set_qe_mux_rxtx()
137 		return -EINVAL;  in ucc_set_qe_mux_rxtx()
141 	switch (reg_num) {  in ucc_set_qe_mux_rxtx()
143 		switch (clock) {  in ucc_set_qe_mux_rxtx()
158 		switch (clock) {  in ucc_set_qe_mux_rxtx()
173 		switch (clock) {  in ucc_set_qe_mux_rxtx()
189 		switch (clock) {  in ucc_set_qe_mux_rxtx()
209 		return -ENOENT;  in ucc_set_qe_mux_rxtx()
211 	if (mode == COMM_DIR_RX)  in ucc_set_qe_mux_rxtx()
222 	int clock_bits = -EINVAL;  in ucc_get_tdm_common_clk()
230 	switch (tdm_num) {  in ucc_get_tdm_common_clk()
235 		switch (clock) {  in ucc_get_tdm_common_clk()
256 		switch (clock) {  in ucc_get_tdm_common_clk()
282 	int clock_bits = -EINVAL;  in ucc_get_tdm_rx_clk()
284 	switch (tdm_num) {  in ucc_get_tdm_rx_clk()
286 		switch (clock) {  in ucc_get_tdm_rx_clk()
298 		switch (clock) {  in ucc_get_tdm_rx_clk()
310 		switch (clock) {  in ucc_get_tdm_rx_clk()
322 		switch (clock) {  in ucc_get_tdm_rx_clk()
334 		switch (clock) {  in ucc_get_tdm_rx_clk()
346 		switch (clock) {  in ucc_get_tdm_rx_clk()
358 		switch (clock) {  in ucc_get_tdm_rx_clk()
370 		switch (clock) {  in ucc_get_tdm_rx_clk()
388 	int clock_bits = -EINVAL;  in ucc_get_tdm_tx_clk()
390 	switch (tdm_num) {  in ucc_get_tdm_tx_clk()
392 		switch (clock) {  in ucc_get_tdm_tx_clk()
404 		switch (clock) {  in ucc_get_tdm_tx_clk()
416 		switch (clock) {  in ucc_get_tdm_tx_clk()
428 		switch (clock) {  in ucc_get_tdm_tx_clk()
440 		switch (clock) {  in ucc_get_tdm_tx_clk()
452 		switch (clock) {  in ucc_get_tdm_tx_clk()
464 		switch (clock) {  in ucc_get_tdm_tx_clk()
476 		switch (clock) {  in ucc_get_tdm_tx_clk()
492 /* tdm_num: TDM A-H port num is 0-7 */
493 static int ucc_get_tdm_rxtx_clk(enum comm_dir mode, u32 tdm_num,  in ucc_get_tdm_rxtx_clk()  argument
501 	if (mode == COMM_DIR_RX)  in ucc_get_tdm_rxtx_clk()
503 	if (mode == COMM_DIR_TX)  in ucc_get_tdm_rxtx_clk()
508 static u32 ucc_get_tdm_clk_shift(enum comm_dir mode, u32 tdm_num)  in ucc_get_tdm_clk_shift()  argument
512 	shift = (mode == COMM_DIR_RX) ? RX_CLK_SHIFT_BASE : TX_CLK_SHIFT_BASE;  in ucc_get_tdm_clk_shift()
514 		shift -= tdm_num * 4;  in ucc_get_tdm_clk_shift()
516 		shift -= (tdm_num - 4) * 4;  in ucc_get_tdm_clk_shift()
522 			 enum comm_dir mode)  in ucc_set_tdm_rxtx_clk()  argument
529 	qe_mux_reg = &qe_immr->qmx;  in ucc_set_tdm_rxtx_clk()
532 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
535 	if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)  in ucc_set_tdm_rxtx_clk()
536 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
538 	clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock);  in ucc_set_tdm_rxtx_clk()
540 		return -EINVAL;  in ucc_set_tdm_rxtx_clk()
542 	shift = ucc_get_tdm_clk_shift(mode, tdm_num);  in ucc_set_tdm_rxtx_clk()
544 	cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :  in ucc_set_tdm_rxtx_clk()
545 				  &qe_mux_reg->cmxsi1cr_h;  in ucc_set_tdm_rxtx_clk()
554 				   enum comm_dir mode)  in ucc_get_tdm_sync_source()  argument
556 	int source = -EINVAL;  in ucc_get_tdm_sync_source()
558 	if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) {  in ucc_get_tdm_sync_source()
562 	if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) {  in ucc_get_tdm_sync_source()
567 	switch (tdm_num) {  in ucc_get_tdm_sync_source()
570 		switch (clock) {  in ucc_get_tdm_sync_source()
583 		switch (clock) {  in ucc_get_tdm_sync_source()
596 		switch (clock) {  in ucc_get_tdm_sync_source()
609 		switch (clock) {  in ucc_get_tdm_sync_source()
625 static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num)  in ucc_get_tdm_sync_shift()  argument
629 	shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : TX_SYNC_SHIFT_BASE;  in ucc_get_tdm_sync_shift()
630 	shift -= tdm_num * 2;  in ucc_get_tdm_sync_shift()
636 			  enum comm_dir mode)  in ucc_set_tdm_rxtx_sync()  argument
642 	qe_mux_reg = &qe_immr->qmx;  in ucc_set_tdm_rxtx_sync()
645 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
648 	if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)  in ucc_set_tdm_rxtx_sync()
649 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
651 	source = ucc_get_tdm_sync_source(tdm_num, clock, mode);  in ucc_set_tdm_rxtx_sync()
653 		return -EINVAL;  in ucc_set_tdm_rxtx_sync()
655 	shift = ucc_get_tdm_sync_shift(mode, tdm_num);  in ucc_set_tdm_rxtx_sync()
657 	qe_clrsetbits32(&qe_mux_reg->cmxsi1syr,  in ucc_set_tdm_rxtx_sync()