Lines Matching +full:lp0 +full:- +full:vec
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
52 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
172 * struct tegra_pmc - NVIDIA Tegra PMC
185 * @corereq_high: core power request is active-high
186 * @sysclkreq_high: system clock request is active-high
189 * @lp0_vec_phys: physical base address of the LP0 warm boot code
190 * @lp0_vec_size: size of the LP0 warm boot code
237 return readl(pmc->base + offset); in tegra_pmc_readl()
242 writel(value, pmc->base + offset); in tegra_pmc_writel()
247 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
255 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
260 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
267 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
268 return -EINVAL; in tegra_powergate_lookup()
270 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
274 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
278 return -ENODEV; in tegra_powergate_lookup()
282 * tegra_powergate_set() - set the state of a partition
291 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
292 return -EINVAL; in tegra_powergate_set()
294 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
297 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
306 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
315 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
322 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
342 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
351 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
352 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_disable_clocks()
360 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
361 err = clk_prepare_enable(pg->clks[i]); in tegra_powergate_enable_clocks()
369 while (i--) in tegra_powergate_enable_clocks()
370 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_enable_clocks()
385 err = reset_control_assert(pg->reset); in tegra_powergate_power_up()
391 err = tegra_powergate_set(pg->id, true); in tegra_powergate_power_up()
403 err = __tegra_powergate_remove_clamping(pg->id); in tegra_powergate_power_up()
409 err = reset_control_deassert(pg->reset); in tegra_powergate_power_up()
415 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
416 err = tegra210_clk_handle_mbist_war(pg->id); in tegra_powergate_power_up()
430 tegra_powergate_set(pg->id, false); in tegra_powergate_power_up()
445 err = reset_control_assert(pg->reset); in tegra_powergate_power_down()
455 err = tegra_powergate_set(pg->id, false); in tegra_powergate_power_down()
464 reset_control_deassert(pg->reset); in tegra_powergate_power_down()
480 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, in tegra_genpd_power_on()
494 pg->genpd.name, err); in tegra_genpd_power_off()
500 * tegra_powergate_power_on() - power on partition
506 return -EINVAL; in tegra_powergate_power_on()
512 * tegra_powergate_power_off() - power off partition
518 return -EINVAL; in tegra_powergate_power_off()
525 * tegra_powergate_is_powered() - check if partition is powered
531 return -EINVAL; in tegra_powergate_is_powered()
537 * tegra_powergate_remove_clamping() - remove power clamps for partition
543 return -EINVAL; in tegra_powergate_remove_clamping()
550 * tegra_powergate_sequence_power_up() - power up partition
564 return -EINVAL; in tegra_powergate_sequence_power_up()
568 return -ENOMEM; in tegra_powergate_sequence_power_up()
570 pg->id = id; in tegra_powergate_sequence_power_up()
571 pg->clks = &clk; in tegra_powergate_sequence_power_up()
572 pg->num_clks = 1; in tegra_powergate_sequence_power_up()
573 pg->reset = rst; in tegra_powergate_sequence_power_up()
574 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
588 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
596 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
597 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
599 return -EINVAL; in tegra_get_cpu_powergate_id()
603 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
618 * tegra_pmc_cpu_power_on() - power on CPU partition
633 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
654 value = readl(pmc->scratch + pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
664 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_restart_notify()
668 writel(value, pmc->scratch + pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
689 seq_printf(s, "------------------\n"); in powergate_show()
691 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
696 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
705 return single_open(file, powergate_show, inode->i_private); in powergate_open()
717 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, in tegra_powergate_debugfs_init()
719 if (!pmc->debugfs) in tegra_powergate_debugfs_init()
720 return -ENOMEM; in tegra_powergate_debugfs_init()
734 return -ENODEV; in tegra_powergate_of_get_clks()
736 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); in tegra_powergate_of_get_clks()
737 if (!pg->clks) in tegra_powergate_of_get_clks()
738 return -ENOMEM; in tegra_powergate_of_get_clks()
741 pg->clks[i] = of_clk_get(np, i); in tegra_powergate_of_get_clks()
742 if (IS_ERR(pg->clks[i])) { in tegra_powergate_of_get_clks()
743 err = PTR_ERR(pg->clks[i]); in tegra_powergate_of_get_clks()
748 pg->num_clks = count; in tegra_powergate_of_get_clks()
753 while (i--) in tegra_powergate_of_get_clks()
754 clk_put(pg->clks[i]); in tegra_powergate_of_get_clks()
756 kfree(pg->clks); in tegra_powergate_of_get_clks()
766 pg->reset = of_reset_control_array_get_exclusive(np); in tegra_powergate_of_get_resets()
767 if (IS_ERR(pg->reset)) { in tegra_powergate_of_get_resets()
768 err = PTR_ERR(pg->reset); in tegra_powergate_of_get_resets()
774 err = reset_control_assert(pg->reset); in tegra_powergate_of_get_resets()
776 err = reset_control_deassert(pg->reset); in tegra_powergate_of_get_resets()
779 reset_control_put(pg->reset); in tegra_powergate_of_get_resets()
794 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
796 pr_err("powergate lookup failed for %s: %d\n", np->name, id); in tegra_powergate_add()
804 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
806 pg->id = id; in tegra_powergate_add()
807 pg->genpd.name = np->name; in tegra_powergate_add()
808 pg->genpd.power_off = tegra_genpd_power_off; in tegra_powergate_add()
809 pg->genpd.power_on = tegra_genpd_power_on; in tegra_powergate_add()
810 pg->pmc = pmc; in tegra_powergate_add()
812 off = !tegra_powergate_is_powered(pg->id); in tegra_powergate_add()
816 pr_err("failed to get clocks for %s: %d\n", np->name, err); in tegra_powergate_add()
822 pr_err("failed to get resets for %s: %d\n", np->name, err); in tegra_powergate_add()
834 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB in tegra_powergate_add()
835 * host and super-speed partitions. Once the XHCI driver in tegra_powergate_add()
849 err = pm_genpd_init(&pg->genpd, NULL, off); in tegra_powergate_add()
851 pr_err("failed to initialise PM domain %s: %d\n", np->name, in tegra_powergate_add()
856 err = of_genpd_add_provider_simple(np, &pg->genpd); in tegra_powergate_add()
859 np->name, err); in tegra_powergate_add()
863 pr_debug("added PM domain %s\n", pg->genpd.name); in tegra_powergate_add()
868 pm_genpd_remove(&pg->genpd); in tegra_powergate_add()
871 reset_control_put(pg->reset); in tegra_powergate_add()
874 while (pg->num_clks--) in tegra_powergate_add()
875 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_add()
877 kfree(pg->clks); in tegra_powergate_add()
880 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
893 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_powergate_init()
894 if (pmc->soc->powergates[i]) in tegra_powergate_init()
895 set_bit(i, pmc->powergates_available); in tegra_powergate_init()
912 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
913 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
914 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
928 return -ENOENT; in tegra_io_pad_prepare()
931 if (pad->dpd == UINT_MAX) in tegra_io_pad_prepare()
932 return -ENOTSUPP; in tegra_io_pad_prepare()
934 *mask = BIT(pad->dpd % 32); in tegra_io_pad_prepare()
936 if (pad->dpd < 32) { in tegra_io_pad_prepare()
937 *status = pmc->soc->regs->dpd_status; in tegra_io_pad_prepare()
938 *request = pmc->soc->regs->dpd_req; in tegra_io_pad_prepare()
940 *status = pmc->soc->regs->dpd2_status; in tegra_io_pad_prepare()
941 *request = pmc->soc->regs->dpd2_req; in tegra_io_pad_prepare()
944 if (pmc->clk) { in tegra_io_pad_prepare()
945 rate = clk_get_rate(pmc->clk); in tegra_io_pad_prepare()
948 return -ENODEV; in tegra_io_pad_prepare()
977 return -ETIMEDOUT; in tegra_io_pad_poll()
982 if (pmc->clk) in tegra_io_pad_unprepare()
987 * tegra_io_pad_power_enable() - enable power to I/O pad
998 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1017 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1023 * tegra_io_pad_power_disable() - disable power to I/O pad
1034 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1053 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1066 return -ENOENT; in tegra_io_pad_set_voltage()
1068 if (pad->voltage == UINT_MAX) in tegra_io_pad_set_voltage()
1069 return -ENOTSUPP; in tegra_io_pad_set_voltage()
1071 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1073 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1077 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1079 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1083 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ in tegra_io_pad_set_voltage()
1085 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1092 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1094 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1099 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1114 return -ENOENT; in tegra_io_pad_get_voltage()
1116 if (pad->voltage == UINT_MAX) in tegra_io_pad_get_voltage()
1117 return -ENOTSUPP; in tegra_io_pad_get_voltage()
1119 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1124 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1132 * tegra_io_rail_power_on() - enable power to I/O rail
1144 * tegra_io_rail_power_off() - disable power to I/O rail
1158 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1166 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1180 rate = clk_get_rate(pmc->clk); in tegra_pmc_enter_suspend_mode()
1190 if (rate != pmc->rate) { in tegra_pmc_enter_suspend_mode()
1193 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1197 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1203 pmc->rate = rate; in tegra_pmc_enter_suspend_mode()
1217 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1221 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1225 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1229 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1233 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1238 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1240 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1241 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1243 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1245 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1246 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1248 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1250 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", in tegra_pmc_parse_dt()
1252 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1254 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1255 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1257 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1258 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1260 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1262 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1263 "nvidia,core-power-req-active-high"); in tegra_pmc_parse_dt()
1265 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1266 "nvidia,sys-clock-req-active-high"); in tegra_pmc_parse_dt()
1268 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1269 "nvidia,combined-power-req"); in tegra_pmc_parse_dt()
1271 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1272 "nvidia,cpu-pwr-good-en"); in tegra_pmc_parse_dt()
1274 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
1276 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1277 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1279 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1280 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1287 if (pmc->soc->init) in tegra_pmc_init()
1288 pmc->soc->init(pmc); in tegra_pmc_init()
1295 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1299 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1302 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1304 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1308 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { in tegra_pmc_init_tsense_reset()
1313 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { in tegra_pmc_init_tsense_reset()
1314 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1318 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { in tegra_pmc_init_tsense_reset()
1319 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1323 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { in tegra_pmc_init_tsense_reset()
1324 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1328 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
1351 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
1361 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
1378 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
1379 return -ENODEV; in tegra_pmc_probe()
1381 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
1387 base = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
1393 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
1394 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
1395 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
1397 pmc->wake = base; in tegra_pmc_probe()
1402 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
1403 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
1404 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
1406 pmc->aotag = base; in tegra_pmc_probe()
1411 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
1412 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
1413 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
1415 pmc->scratch = base; in tegra_pmc_probe()
1418 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); in tegra_pmc_probe()
1419 if (IS_ERR(pmc->clk)) { in tegra_pmc_probe()
1420 err = PTR_ERR(pmc->clk); in tegra_pmc_probe()
1422 if (err != -ENOENT) { in tegra_pmc_probe()
1423 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); in tegra_pmc_probe()
1427 pmc->clk = NULL; in tegra_pmc_probe()
1430 pmc->dev = &pdev->dev; in tegra_pmc_probe()
1444 debugfs_remove(pmc->debugfs); in tegra_pmc_probe()
1445 dev_err(&pdev->dev, "unable to register restart handler, %d\n", in tegra_pmc_probe()
1450 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
1451 iounmap(pmc->base); in tegra_pmc_probe()
1452 pmc->base = base; in tegra_pmc_probe()
1453 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
1506 if (pmc->sysclkreq_high) in tegra20_pmc_init()
1862 index = of_property_match_string(np, "reg-names", "wake"); in tegra186_pmc_setup_irq_polarity()
1904 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc },
1905 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
1906 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1907 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1908 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1909 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1910 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1911 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1917 .name = "tegra-pmc",
1939 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
1944 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_pmc_early_init()
1945 * 64-bit ARM device tree files for Tegra are required to have in tegra_pmc_early_init()
1948 * This is for backwards-compatibility with old device trees in tegra_pmc_early_init()
1964 * nice with multi-platform kernels. in tegra_pmc_early_init()
1976 return -ENXIO; in tegra_pmc_early_init()
1980 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); in tegra_pmc_early_init()
1981 if (!pmc->base) { in tegra_pmc_early_init()
1984 return -ENXIO; in tegra_pmc_early_init()
1988 pmc->soc = match->data; in tegra_pmc_early_init()
1994 * exists and contains the nvidia,invert-interrupt property. in tegra_pmc_early_init()
1996 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); in tegra_pmc_early_init()
1998 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()