Lines Matching +full:first +full:- +full:data +full:- +full:gpios
23 #include <linux/dma-mapping.h>
42 #include "spi-fsl-lib.h"
43 #include "spi-fsl-cpm.h"
44 #include "spi-fsl-spi.h"
64 .data = &of_fsl_spi_fsl_config,
68 .data = &of_fsl_spi_grlib_config,
78 if (dev->of_node) { in fsl_spi_get_type()
79 match = of_match_node(of_fsl_spi_match, dev->of_node); in fsl_spi_get_type()
80 if (match && match->data) in fsl_spi_get_type()
81 return ((struct fsl_spi_match_data *)match->data)->type; in fsl_spi_get_type()
88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); in fsl_spi_change_mode()
89 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_change_mode()
90 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_change_mode()
91 __be32 __iomem *mode = ®_base->mode; in fsl_spi_change_mode()
94 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) in fsl_spi_change_mode()
101 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); in fsl_spi_change_mode()
104 if (mspi->flags & SPI_CPM_MODE) { in fsl_spi_change_mode()
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode); in fsl_spi_change_mode()
113 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_chipselect()
115 bool pol = spi->mode & SPI_CS_HIGH; in fsl_spi_chipselect()
116 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_chipselect()
118 pdata = spi->dev.parent->parent->platform_data; in fsl_spi_chipselect()
121 if (pdata->cs_control) in fsl_spi_chipselect()
122 pdata->cs_control(spi, !pol); in fsl_spi_chipselect()
126 mpc8xxx_spi->rx_shift = cs->rx_shift; in fsl_spi_chipselect()
127 mpc8xxx_spi->tx_shift = cs->tx_shift; in fsl_spi_chipselect()
128 mpc8xxx_spi->get_rx = cs->get_rx; in fsl_spi_chipselect()
129 mpc8xxx_spi->get_tx = cs->get_tx; in fsl_spi_chipselect()
133 if (pdata->cs_control) in fsl_spi_chipselect()
134 pdata->cs_control(spi, pol); in fsl_spi_chipselect()
165 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ in fsl_spi_grlib_set_shifts()
167 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ in fsl_spi_grlib_set_shifts()
177 cs->rx_shift = 0; in mspi_apply_cpu_mode_quirks()
178 cs->tx_shift = 0; in mspi_apply_cpu_mode_quirks()
180 cs->get_rx = mpc8xxx_spi_rx_buf_u8; in mspi_apply_cpu_mode_quirks()
181 cs->get_tx = mpc8xxx_spi_tx_buf_u8; in mspi_apply_cpu_mode_quirks()
183 cs->get_rx = mpc8xxx_spi_rx_buf_u16; in mspi_apply_cpu_mode_quirks()
184 cs->get_tx = mpc8xxx_spi_tx_buf_u16; in mspi_apply_cpu_mode_quirks()
186 cs->get_rx = mpc8xxx_spi_rx_buf_u32; in mspi_apply_cpu_mode_quirks()
187 cs->get_tx = mpc8xxx_spi_tx_buf_u32; in mspi_apply_cpu_mode_quirks()
189 return -EINVAL; in mspi_apply_cpu_mode_quirks()
191 if (mpc8xxx_spi->set_shifts) in mspi_apply_cpu_mode_quirks()
192 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, in mspi_apply_cpu_mode_quirks()
194 !(spi->mode & SPI_LSB_FIRST)); in mspi_apply_cpu_mode_quirks()
196 mpc8xxx_spi->rx_shift = cs->rx_shift; in mspi_apply_cpu_mode_quirks()
197 mpc8xxx_spi->tx_shift = cs->tx_shift; in mspi_apply_cpu_mode_quirks()
198 mpc8xxx_spi->get_rx = cs->get_rx; in mspi_apply_cpu_mode_quirks()
199 mpc8xxx_spi->get_tx = cs->get_tx; in mspi_apply_cpu_mode_quirks()
214 if (spi->mode & SPI_LSB_FIRST && in mspi_apply_qe_mode_quirks()
216 return -EINVAL; in mspi_apply_qe_mode_quirks()
229 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_setup_transfer()
231 mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_setup_transfer()
234 bits_per_word = t->bits_per_word; in fsl_spi_setup_transfer()
235 hz = t->speed_hz; in fsl_spi_setup_transfer()
238 /* spi_transfer level calls that work per-word */ in fsl_spi_setup_transfer()
240 bits_per_word = spi->bits_per_word; in fsl_spi_setup_transfer()
243 hz = spi->max_speed_hz; in fsl_spi_setup_transfer()
245 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) in fsl_spi_setup_transfer()
249 else if (mpc8xxx_spi->flags & SPI_QE) in fsl_spi_setup_transfer()
259 bits_per_word = bits_per_word - 1; in fsl_spi_setup_transfer()
262 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 in fsl_spi_setup_transfer()
265 cs->hw_mode |= SPMODE_LEN(bits_per_word); in fsl_spi_setup_transfer()
267 if ((mpc8xxx_spi->spibrg / hz) > 64) { in fsl_spi_setup_transfer()
268 cs->hw_mode |= SPMODE_DIV16; in fsl_spi_setup_transfer()
269 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; in fsl_spi_setup_transfer()
272 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); in fsl_spi_setup_transfer()
276 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; in fsl_spi_setup_transfer()
279 pm--; in fsl_spi_setup_transfer()
281 cs->hw_mode |= SPMODE_PM(pm); in fsl_spi_setup_transfer()
291 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs()
293 mspi->count = len; in fsl_spi_cpu_bufs()
296 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
299 word = mspi->get_tx(mspi); in fsl_spi_cpu_bufs()
300 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_bufs()
308 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_bufs()
310 unsigned int len = t->len; in fsl_spi_bufs()
314 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
315 bits_per_word = spi->bits_per_word; in fsl_spi_bufs()
316 if (t->bits_per_word) in fsl_spi_bufs()
317 bits_per_word = t->bits_per_word; in fsl_spi_bufs()
322 return -EINVAL; in fsl_spi_bufs()
328 return -EINVAL; in fsl_spi_bufs()
332 mpc8xxx_spi->tx = t->tx_buf; in fsl_spi_bufs()
333 mpc8xxx_spi->rx = t->rx_buf; in fsl_spi_bufs()
335 reinit_completion(&mpc8xxx_spi->done); in fsl_spi_bufs()
337 if (mpc8xxx_spi->flags & SPI_CPM_MODE) in fsl_spi_bufs()
344 wait_for_completion(&mpc8xxx_spi->done); in fsl_spi_bufs()
347 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_bufs()
349 if (mpc8xxx_spi->flags & SPI_CPM_MODE) in fsl_spi_bufs()
352 return mpc8xxx_spi->count; in fsl_spi_bufs()
358 struct spi_device *spi = m->spi; in fsl_spi_do_one_msg()
359 struct spi_transfer *t, *first; in fsl_spi_do_one_msg() local
365 first = list_first_entry(&m->transfers, struct spi_transfer, in fsl_spi_do_one_msg()
367 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_spi_do_one_msg()
368 if ((first->bits_per_word != t->bits_per_word) || in fsl_spi_do_one_msg()
369 (first->speed_hz != t->speed_hz)) { in fsl_spi_do_one_msg()
370 dev_err(&spi->dev, in fsl_spi_do_one_msg()
372 return -EINVAL; in fsl_spi_do_one_msg()
377 status = -EINVAL; in fsl_spi_do_one_msg()
378 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_spi_do_one_msg()
379 if (t->bits_per_word || t->speed_hz) { in fsl_spi_do_one_msg()
390 cs_change = t->cs_change; in fsl_spi_do_one_msg()
391 if (t->len) in fsl_spi_do_one_msg()
392 status = fsl_spi_bufs(spi, t, m->is_dma_mapped); in fsl_spi_do_one_msg()
394 status = -EMSGSIZE; in fsl_spi_do_one_msg()
397 m->actual_length += t->len; in fsl_spi_do_one_msg()
399 if (t->delay_usecs) in fsl_spi_do_one_msg()
400 udelay(t->delay_usecs); in fsl_spi_do_one_msg()
409 m->status = status; in fsl_spi_do_one_msg()
429 if (!spi->max_speed_hz) in fsl_spi_setup()
430 return -EINVAL; in fsl_spi_setup()
435 return -ENOMEM; in fsl_spi_setup()
438 mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_setup()
440 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
442 hw_mode = cs->hw_mode; /* Save original settings */ in fsl_spi_setup()
443 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); in fsl_spi_setup()
445 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH in fsl_spi_setup()
448 if (spi->mode & SPI_CPHA) in fsl_spi_setup()
449 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; in fsl_spi_setup()
450 if (spi->mode & SPI_CPOL) in fsl_spi_setup()
451 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; in fsl_spi_setup()
452 if (!(spi->mode & SPI_LSB_FIRST)) in fsl_spi_setup()
453 cs->hw_mode |= SPMODE_REV; in fsl_spi_setup()
454 if (spi->mode & SPI_LOOP) in fsl_spi_setup()
455 cs->hw_mode |= SPMODE_LOOP; in fsl_spi_setup()
459 cs->hw_mode = hw_mode; /* Restore settings */ in fsl_spi_setup()
463 if (mpc8xxx_spi->type == TYPE_GRLIB) { in fsl_spi_setup()
464 if (gpio_is_valid(spi->cs_gpio)) { in fsl_spi_setup()
467 retval = gpio_request(spi->cs_gpio, in fsl_spi_setup()
468 dev_name(&spi->dev)); in fsl_spi_setup()
472 desel = !(spi->mode & SPI_CS_HIGH); in fsl_spi_setup()
473 retval = gpio_direction_output(spi->cs_gpio, desel); in fsl_spi_setup()
475 gpio_free(spi->cs_gpio); in fsl_spi_setup()
478 } else if (spi->cs_gpio != -ENOENT) { in fsl_spi_setup()
479 if (spi->cs_gpio < 0) in fsl_spi_setup()
480 return spi->cs_gpio; in fsl_spi_setup()
481 return -EINVAL; in fsl_spi_setup()
483 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list in fsl_spi_setup()
489 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ in fsl_spi_setup()
497 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_cleanup()
500 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio)) in fsl_spi_cleanup()
501 gpio_free(spi->cs_gpio); in fsl_spi_cleanup()
509 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_cpu_irq()
511 /* We need handle RX first */ in fsl_spi_cpu_irq()
513 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); in fsl_spi_cpu_irq()
515 if (mspi->rx) in fsl_spi_cpu_irq()
516 mspi->get_rx(rx_data, mspi); in fsl_spi_cpu_irq()
522 mpc8xxx_spi_read_reg(®_base->event)) & in fsl_spi_cpu_irq()
527 mpc8xxx_spi_write_reg(®_base->event, events); in fsl_spi_cpu_irq()
529 mspi->count -= 1; in fsl_spi_cpu_irq()
530 if (mspi->count) { in fsl_spi_cpu_irq()
531 u32 word = mspi->get_tx(mspi); in fsl_spi_cpu_irq()
533 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_irq()
535 complete(&mspi->done); in fsl_spi_cpu_irq()
544 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_irq()
547 events = mpc8xxx_spi_read_reg(®_base->event); in fsl_spi_irq()
551 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); in fsl_spi_irq()
553 if (mspi->flags & SPI_CPM_MODE) in fsl_spi_irq()
563 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); in fsl_spi_grlib_cs_control()
564 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control()
566 u16 cs = spi->chip_select; in fsl_spi_grlib_cs_control()
568 if (gpio_is_valid(spi->cs_gpio)) { in fsl_spi_grlib_cs_control()
569 gpio_set_value(spi->cs_gpio, on); in fsl_spi_grlib_cs_control()
570 } else if (cs < mpc8xxx_spi->native_chipselects) { in fsl_spi_grlib_cs_control()
571 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); in fsl_spi_grlib_cs_control()
573 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); in fsl_spi_grlib_cs_control()
582 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe()
586 capabilities = mpc8xxx_spi_read_reg(®_base->cap); in fsl_spi_grlib_probe()
588 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; in fsl_spi_grlib_probe()
591 mpc8xxx_spi->max_bits_per_word = mbits + 1; in fsl_spi_grlib_probe()
593 mpc8xxx_spi->native_chipselects = 0; in fsl_spi_grlib_probe()
595 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); in fsl_spi_grlib_probe()
596 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); in fsl_spi_grlib_probe()
598 master->num_chipselect = mpc8xxx_spi->native_chipselects; in fsl_spi_grlib_probe()
599 pdata->cs_control = fsl_spi_grlib_cs_control; in fsl_spi_grlib_probe()
614 ret = -ENOMEM; in fsl_spi_probe()
622 master->setup = fsl_spi_setup; in fsl_spi_probe()
623 master->cleanup = fsl_spi_cleanup; in fsl_spi_probe()
624 master->transfer_one_message = fsl_spi_do_one_msg; in fsl_spi_probe()
627 mpc8xxx_spi->max_bits_per_word = 32; in fsl_spi_probe()
628 mpc8xxx_spi->type = fsl_spi_get_type(dev); in fsl_spi_probe()
634 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); in fsl_spi_probe()
635 if (IS_ERR(mpc8xxx_spi->reg_base)) { in fsl_spi_probe()
636 ret = PTR_ERR(mpc8xxx_spi->reg_base); in fsl_spi_probe()
640 if (mpc8xxx_spi->type == TYPE_GRLIB) in fsl_spi_probe()
643 master->bits_per_word_mask = in fsl_spi_probe()
645 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); in fsl_spi_probe()
647 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) in fsl_spi_probe()
648 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; in fsl_spi_probe()
650 if (mpc8xxx_spi->set_shifts) in fsl_spi_probe()
651 /* 8 bits per word and MSB first */ in fsl_spi_probe()
652 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, in fsl_spi_probe()
653 &mpc8xxx_spi->tx_shift, 8, 1); in fsl_spi_probe()
656 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, in fsl_spi_probe()
662 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_probe()
665 mpc8xxx_spi_write_reg(®_base->mode, 0); in fsl_spi_probe()
666 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_probe()
667 mpc8xxx_spi_write_reg(®_base->command, 0); in fsl_spi_probe()
668 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); in fsl_spi_probe()
671 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; in fsl_spi_probe()
672 if (mpc8xxx_spi->max_bits_per_word < 8) { in fsl_spi_probe()
674 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); in fsl_spi_probe()
676 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) in fsl_spi_probe()
679 mpc8xxx_spi_write_reg(®_base->mode, regval); in fsl_spi_probe()
686 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); in fsl_spi_probe()
700 struct device *dev = spi->dev.parent->parent; in fsl_spi_cs_control()
703 u16 cs = spi->chip_select; in fsl_spi_cs_control()
704 int gpio = pinfo->gpios[cs]; in fsl_spi_cs_control()
705 bool alow = pinfo->alow_flags[cs]; in fsl_spi_cs_control()
712 struct device_node *np = dev->of_node; in of_fsl_spi_get_chipselects()
722 * SPI w/o chip-select line. One SPI device is still permitted in of_fsl_spi_get_chipselects()
725 pdata->max_chipselect = 1; in of_fsl_spi_get_chipselects()
729 pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios), in of_fsl_spi_get_chipselects()
731 if (!pinfo->gpios) in of_fsl_spi_get_chipselects()
732 return -ENOMEM; in of_fsl_spi_get_chipselects()
733 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); in of_fsl_spi_get_chipselects()
735 pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags), in of_fsl_spi_get_chipselects()
737 if (!pinfo->alow_flags) { in of_fsl_spi_get_chipselects()
738 ret = -ENOMEM; in of_fsl_spi_get_chipselects()
759 pinfo->gpios[i] = gpio; in of_fsl_spi_get_chipselects()
760 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; in of_fsl_spi_get_chipselects()
762 ret = gpio_direction_output(pinfo->gpios[i], in of_fsl_spi_get_chipselects()
763 pinfo->alow_flags[i]); in of_fsl_spi_get_chipselects()
772 pdata->max_chipselect = ngpios; in of_fsl_spi_get_chipselects()
773 pdata->cs_control = fsl_spi_cs_control; in of_fsl_spi_get_chipselects()
779 if (gpio_is_valid(pinfo->gpios[i])) in of_fsl_spi_get_chipselects()
780 gpio_free(pinfo->gpios[i]); in of_fsl_spi_get_chipselects()
781 i--; in of_fsl_spi_get_chipselects()
784 kfree(pinfo->alow_flags); in of_fsl_spi_get_chipselects()
785 pinfo->alow_flags = NULL; in of_fsl_spi_get_chipselects()
787 kfree(pinfo->gpios); in of_fsl_spi_get_chipselects()
788 pinfo->gpios = NULL; in of_fsl_spi_get_chipselects()
798 if (!pinfo->gpios) in of_fsl_spi_free_chipselects()
801 for (i = 0; i < pdata->max_chipselect; i++) { in of_fsl_spi_free_chipselects()
802 if (gpio_is_valid(pinfo->gpios[i])) in of_fsl_spi_free_chipselects()
803 gpio_free(pinfo->gpios[i]); in of_fsl_spi_free_chipselects()
806 kfree(pinfo->gpios); in of_fsl_spi_free_chipselects()
807 kfree(pinfo->alow_flags); in of_fsl_spi_free_chipselects()
813 struct device *dev = &ofdev->dev; in of_fsl_spi_probe()
814 struct device_node *np = ofdev->dev.of_node; in of_fsl_spi_probe()
818 int ret = -ENOMEM; in of_fsl_spi_probe()
824 type = fsl_spi_get_type(&ofdev->dev); in of_fsl_spi_probe()
861 if (mpc8xxx_spi->type == TYPE_FSL) in of_fsl_spi_remove()
862 of_fsl_spi_free_chipselects(&ofdev->dev); in of_fsl_spi_remove()
878 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
879 * only. The driver should go away soon, since newer MPC8323E-RDB's device
889 if (!dev_get_platdata(&pdev->dev)) in plat_mpc8xxx_spi_probe()
890 return -EINVAL; in plat_mpc8xxx_spi_probe()
894 return -EINVAL; in plat_mpc8xxx_spi_probe()
898 return -EINVAL; in plat_mpc8xxx_spi_probe()
900 master = fsl_spi_probe(&pdev->dev, mem, irq); in plat_mpc8xxx_spi_probe()