Lines Matching +full:post +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/dma-imx.h>
27 #include <linux/platform_data/spi-imx.h>
115 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
120 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
125 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
130 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
136 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
138 if (spi_imx->rx_buf) { \
139 *(type *)spi_imx->rx_buf = val; \
140 spi_imx->rx_buf += sizeof(type); \
143 spi_imx->remainder -= sizeof(type); \
151 if (spi_imx->tx_buf) { \
152 val = *(type *)spi_imx->tx_buf; \
153 spi_imx->tx_buf += sizeof(type); \
156 spi_imx->count -= sizeof(type); \
158 writel(val, spi_imx->base + MXC_CSPITXDATA); \
221 if (!master->dma_rx) in spi_imx_can_dma()
224 if (spi_imx->slave_mode) in spi_imx_can_dma()
227 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); in spi_imx_can_dma()
229 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { in spi_imx_can_dma()
230 if (!(transfer->len % (i * bytes_per_word))) in spi_imx_can_dma()
234 spi_imx->wml = i; in spi_imx_can_dma()
235 spi_imx->dynamic_burst = 0; in spi_imx_can_dma()
281 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32()
286 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap_u32()
288 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_rx_swap_u32()
294 *(u32 *)spi_imx->rx_buf = val; in spi_imx_buf_rx_swap_u32()
295 spi_imx->rx_buf += sizeof(u32); in spi_imx_buf_rx_swap_u32()
298 spi_imx->remainder -= sizeof(u32); in spi_imx_buf_rx_swap_u32()
306 unaligned = spi_imx->remainder % 4; in spi_imx_buf_rx_swap()
313 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_rx_swap()
318 val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap()
320 while (unaligned--) { in spi_imx_buf_rx_swap()
321 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap()
322 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; in spi_imx_buf_rx_swap()
323 spi_imx->rx_buf++; in spi_imx_buf_rx_swap()
325 spi_imx->remainder--; in spi_imx_buf_rx_swap()
336 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap_u32()
337 val = *(u32 *)spi_imx->tx_buf; in spi_imx_buf_tx_swap_u32()
338 spi_imx->tx_buf += sizeof(u32); in spi_imx_buf_tx_swap_u32()
341 spi_imx->count -= sizeof(u32); in spi_imx_buf_tx_swap_u32()
343 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_tx_swap_u32()
350 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap_u32()
358 unaligned = spi_imx->count % 4; in spi_imx_buf_tx_swap()
365 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_tx_swap()
370 while (unaligned--) { in spi_imx_buf_tx_swap()
371 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap()
372 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); in spi_imx_buf_tx_swap()
373 spi_imx->tx_buf++; in spi_imx_buf_tx_swap()
375 spi_imx->count--; in spi_imx_buf_tx_swap()
378 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap()
383 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); in mx53_ecspi_rx_slave()
385 if (spi_imx->rx_buf) { in mx53_ecspi_rx_slave()
386 int n_bytes = spi_imx->slave_burst % sizeof(val); in mx53_ecspi_rx_slave()
391 memcpy(spi_imx->rx_buf, in mx53_ecspi_rx_slave()
392 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); in mx53_ecspi_rx_slave()
394 spi_imx->rx_buf += n_bytes; in mx53_ecspi_rx_slave()
395 spi_imx->slave_burst -= n_bytes; in mx53_ecspi_rx_slave()
398 spi_imx->remainder -= sizeof(u32); in mx53_ecspi_rx_slave()
404 int n_bytes = spi_imx->count % sizeof(val); in mx53_ecspi_tx_slave()
409 if (spi_imx->tx_buf) { in mx53_ecspi_tx_slave()
410 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, in mx53_ecspi_tx_slave()
411 spi_imx->tx_buf, n_bytes); in mx53_ecspi_tx_slave()
413 spi_imx->tx_buf += n_bytes; in mx53_ecspi_tx_slave()
416 spi_imx->count -= n_bytes; in mx53_ecspi_tx_slave()
418 writel(val, spi_imx->base + MXC_CSPITXDATA); in mx53_ecspi_tx_slave()
426 * there are two 4-bit dividers, the pre-divider divides by in mx51_ecspi_clkdiv()
427 * $pre, the post-divider by 2^$post in mx51_ecspi_clkdiv()
429 unsigned int pre, post; in mx51_ecspi_clkdiv() local
430 unsigned int fin = spi_imx->spi_clk; in mx51_ecspi_clkdiv()
435 post = fls(fin) - fls(fspi); in mx51_ecspi_clkdiv()
436 if (fin > fspi << post) in mx51_ecspi_clkdiv()
437 post++; in mx51_ecspi_clkdiv()
439 /* now we have: (fin <= fspi << post) with post being minimal */ in mx51_ecspi_clkdiv()
441 post = max(4U, post) - 4; in mx51_ecspi_clkdiv()
442 if (unlikely(post > 0xf)) { in mx51_ecspi_clkdiv()
443 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", in mx51_ecspi_clkdiv()
448 pre = DIV_ROUND_UP(fin, fspi << post) - 1; in mx51_ecspi_clkdiv()
450 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", in mx51_ecspi_clkdiv()
451 __func__, fin, fspi, post, pre); in mx51_ecspi_clkdiv()
454 *fres = (fin / (pre + 1)) >> post; in mx51_ecspi_clkdiv()
457 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); in mx51_ecspi_clkdiv()
473 writel(val, spi_imx->base + MX51_ECSPI_INT); in mx51_ecspi_intctrl()
480 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
482 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
489 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
491 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
496 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in mx51_ecspi_config()
498 u32 clk = spi_imx->speed_hz, delay, reg; in mx51_ecspi_config() local
499 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_config()
502 if (spi_imx->slave_mode) in mx51_ecspi_config()
510 if (spi->mode & SPI_READY) in mx51_ecspi_config()
511 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); in mx51_ecspi_config()
514 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk); in mx51_ecspi_config()
515 spi_imx->spi_bus_clk = clk; in mx51_ecspi_config()
518 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); in mx51_ecspi_config()
520 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_config()
521 ctrl |= (spi_imx->slave_burst * 8 - 1) in mx51_ecspi_config()
524 ctrl |= (spi_imx->bits_per_word - 1) in mx51_ecspi_config()
532 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_config()
533 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); in mx51_ecspi_config()
535 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); in mx51_ecspi_config()
537 if (spi->mode & SPI_CPHA) in mx51_ecspi_config()
538 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); in mx51_ecspi_config()
540 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); in mx51_ecspi_config()
542 if (spi->mode & SPI_CPOL) { in mx51_ecspi_config()
543 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); in mx51_ecspi_config()
544 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); in mx51_ecspi_config()
546 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); in mx51_ecspi_config()
547 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); in mx51_ecspi_config()
549 if (spi->mode & SPI_CS_HIGH) in mx51_ecspi_config()
550 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); in mx51_ecspi_config()
552 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); in mx51_ecspi_config()
554 if (spi_imx->usedma) in mx51_ecspi_config()
558 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_config()
560 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_config()
561 if (spi->mode & SPI_LOOP) in mx51_ecspi_config()
565 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_config()
567 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_config()
573 * effect of the delay it takes for the hardware to apply changes in mx51_ecspi_config()
580 delay = (2 * 1000000) / clk; in mx51_ecspi_config()
581 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ in mx51_ecspi_config()
582 udelay(delay); in mx51_ecspi_config()
584 usleep_range(delay, delay + 10); in mx51_ecspi_config()
591 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) | in mx51_ecspi_config()
592 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | in mx51_ecspi_config()
593 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | in mx51_ecspi_config()
595 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); in mx51_ecspi_config()
602 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; in mx51_ecspi_rx_available()
609 readl(spi_imx->base + MXC_CSPIRXDATA); in mx51_ecspi_reset()
652 writel(val, spi_imx->base + MXC_CSPIINT); in mx31_intctrl()
659 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
661 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
666 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in mx31_config()
670 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) << in mx31_config()
672 spi_imx->spi_bus_clk = clk; in mx31_config()
675 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; in mx31_config()
678 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; in mx31_config()
681 if (spi->mode & SPI_CPHA) in mx31_config()
683 if (spi->mode & SPI_CPOL) in mx31_config()
685 if (spi->mode & SPI_CS_HIGH) in mx31_config()
687 if (!gpio_is_valid(spi->cs_gpio)) in mx31_config()
688 reg |= (spi->chip_select) << in mx31_config()
692 if (spi_imx->usedma) in mx31_config()
695 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_config()
697 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); in mx31_config()
698 if (spi->mode & SPI_LOOP) in mx31_config()
702 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); in mx31_config()
704 if (spi_imx->usedma) { in mx31_config()
708 spi_imx->base + MX31_CSPI_DMAREG); in mx31_config()
716 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; in mx31_rx_available()
722 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) in mx31_reset()
723 readl(spi_imx->base + MXC_CSPIRXDATA); in mx31_reset()
748 writel(val, spi_imx->base + MXC_CSPIINT); in mx21_intctrl()
755 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
757 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
762 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in mx21_config()
767 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk) in mx21_config()
769 spi_imx->spi_bus_clk = clk; in mx21_config()
771 reg |= spi_imx->bits_per_word - 1; in mx21_config()
773 if (spi->mode & SPI_CPHA) in mx21_config()
775 if (spi->mode & SPI_CPOL) in mx21_config()
777 if (spi->mode & SPI_CS_HIGH) in mx21_config()
779 if (!gpio_is_valid(spi->cs_gpio)) in mx21_config()
780 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; in mx21_config()
782 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_config()
789 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; in mx21_rx_available()
794 writel(1, spi_imx->base + MXC_RESET); in mx21_reset()
817 writel(val, spi_imx->base + MXC_CSPIINT); in mx1_intctrl()
824 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
826 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
831 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in mx1_config()
835 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) << in mx1_config()
837 spi_imx->spi_bus_clk = clk; in mx1_config()
839 reg |= spi_imx->bits_per_word - 1; in mx1_config()
841 if (spi->mode & SPI_CPHA) in mx1_config()
843 if (spi->mode & SPI_CPOL) in mx1_config()
846 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_config()
853 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; in mx1_rx_available()
858 writel(1, spi_imx->base + MXC_RESET); in mx1_reset()
957 .name = "imx1-cspi",
960 .name = "imx21-cspi",
963 .name = "imx27-cspi",
966 .name = "imx31-cspi",
969 .name = "imx35-cspi",
972 .name = "imx51-ecspi",
975 .name = "imx53-ecspi",
983 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
984 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
985 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
986 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
987 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
988 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
989 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
997 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); in spi_imx_chipselect()
999 if (spi->mode & SPI_NO_CS) in spi_imx_chipselect()
1002 if (!gpio_is_valid(spi->cs_gpio)) in spi_imx_chipselect()
1005 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); in spi_imx_chipselect()
1012 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1014 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); in spi_imx_set_burst_len()
1015 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1022 if (spi_imx->dynamic_burst) in spi_imx_push()
1025 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_push()
1031 if (!spi_imx->remainder) { in spi_imx_push()
1032 if (spi_imx->dynamic_burst) { in spi_imx_push()
1035 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; in spi_imx_push()
1042 spi_imx->remainder = burst_len; in spi_imx_push()
1044 spi_imx->remainder = fifo_words; in spi_imx_push()
1048 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { in spi_imx_push()
1049 if (!spi_imx->count) in spi_imx_push()
1051 if (spi_imx->dynamic_burst && in spi_imx_push()
1052 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, in spi_imx_push()
1055 spi_imx->tx(spi_imx); in spi_imx_push()
1056 spi_imx->txfifo++; in spi_imx_push()
1059 if (!spi_imx->slave_mode) in spi_imx_push()
1060 spi_imx->devtype_data->trigger(spi_imx); in spi_imx_push()
1067 while (spi_imx->txfifo && in spi_imx_isr()
1068 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_isr()
1069 spi_imx->rx(spi_imx); in spi_imx_isr()
1070 spi_imx->txfifo--; in spi_imx_isr()
1073 if (spi_imx->count) { in spi_imx_isr()
1078 if (spi_imx->txfifo) { in spi_imx_isr()
1082 spi_imx->devtype_data->intctrl( in spi_imx_isr()
1087 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_isr()
1088 complete(&spi_imx->xfer_done); in spi_imx_isr()
1100 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { in spi_imx_dma_configure()
1111 return -EINVAL; in spi_imx_dma_configure()
1115 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; in spi_imx_dma_configure()
1117 tx.dst_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1118 ret = dmaengine_slave_config(master->dma_tx, &tx); in spi_imx_dma_configure()
1120 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1125 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; in spi_imx_dma_configure()
1127 rx.src_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1128 ret = dmaengine_slave_config(master->dma_rx, &rx); in spi_imx_dma_configure()
1130 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1140 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_setupxfer()
1146 spi_imx->bits_per_word = t->bits_per_word; in spi_imx_setupxfer()
1147 spi_imx->speed_hz = t->speed_hz; in spi_imx_setupxfer()
1150 * Initialize the functions for transfer. To transfer non byte-aligned in spi_imx_setupxfer()
1151 * words, we have to use multiple word-size bursts, we can't use in spi_imx_setupxfer()
1154 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && in spi_imx_setupxfer()
1155 (spi_imx->bits_per_word == 8 || in spi_imx_setupxfer()
1156 spi_imx->bits_per_word == 16 || in spi_imx_setupxfer()
1157 spi_imx->bits_per_word == 32)) { in spi_imx_setupxfer()
1159 spi_imx->rx = spi_imx_buf_rx_swap; in spi_imx_setupxfer()
1160 spi_imx->tx = spi_imx_buf_tx_swap; in spi_imx_setupxfer()
1161 spi_imx->dynamic_burst = 1; in spi_imx_setupxfer()
1164 if (spi_imx->bits_per_word <= 8) { in spi_imx_setupxfer()
1165 spi_imx->rx = spi_imx_buf_rx_u8; in spi_imx_setupxfer()
1166 spi_imx->tx = spi_imx_buf_tx_u8; in spi_imx_setupxfer()
1167 } else if (spi_imx->bits_per_word <= 16) { in spi_imx_setupxfer()
1168 spi_imx->rx = spi_imx_buf_rx_u16; in spi_imx_setupxfer()
1169 spi_imx->tx = spi_imx_buf_tx_u16; in spi_imx_setupxfer()
1171 spi_imx->rx = spi_imx_buf_rx_u32; in spi_imx_setupxfer()
1172 spi_imx->tx = spi_imx_buf_tx_u32; in spi_imx_setupxfer()
1174 spi_imx->dynamic_burst = 0; in spi_imx_setupxfer()
1177 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) in spi_imx_setupxfer()
1178 spi_imx->usedma = 1; in spi_imx_setupxfer()
1180 spi_imx->usedma = 0; in spi_imx_setupxfer()
1182 if (spi_imx->usedma) { in spi_imx_setupxfer()
1183 ret = spi_imx_dma_configure(spi->master); in spi_imx_setupxfer()
1188 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { in spi_imx_setupxfer()
1189 spi_imx->rx = mx53_ecspi_rx_slave; in spi_imx_setupxfer()
1190 spi_imx->tx = mx53_ecspi_tx_slave; in spi_imx_setupxfer()
1191 spi_imx->slave_burst = t->len; in spi_imx_setupxfer()
1194 spi_imx->devtype_data->config(spi); in spi_imx_setupxfer()
1201 struct spi_master *master = spi_imx->bitbang.master; in spi_imx_sdma_exit()
1203 if (master->dma_rx) { in spi_imx_sdma_exit()
1204 dma_release_channel(master->dma_rx); in spi_imx_sdma_exit()
1205 master->dma_rx = NULL; in spi_imx_sdma_exit()
1208 if (master->dma_tx) { in spi_imx_sdma_exit()
1209 dma_release_channel(master->dma_tx); in spi_imx_sdma_exit()
1210 master->dma_tx = NULL; in spi_imx_sdma_exit()
1223 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; in spi_imx_sdma_init()
1226 master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); in spi_imx_sdma_init()
1227 if (IS_ERR(master->dma_tx)) { in spi_imx_sdma_init()
1228 ret = PTR_ERR(master->dma_tx); in spi_imx_sdma_init()
1230 master->dma_tx = NULL; in spi_imx_sdma_init()
1235 master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); in spi_imx_sdma_init()
1236 if (IS_ERR(master->dma_rx)) { in spi_imx_sdma_init()
1237 ret = PTR_ERR(master->dma_rx); in spi_imx_sdma_init()
1239 master->dma_rx = NULL; in spi_imx_sdma_init()
1243 init_completion(&spi_imx->dma_rx_completion); in spi_imx_sdma_init()
1244 init_completion(&spi_imx->dma_tx_completion); in spi_imx_sdma_init()
1245 master->can_dma = spi_imx_can_dma; in spi_imx_sdma_init()
1246 master->max_dma_len = MAX_SDMA_BD_BYTES; in spi_imx_sdma_init()
1247 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | in spi_imx_sdma_init()
1260 complete(&spi_imx->dma_rx_completion); in spi_imx_dma_rx_callback()
1267 complete(&spi_imx->dma_tx_completion); in spi_imx_dma_tx_callback()
1274 /* Time with actual data transfer and CS change delay related to HW */ in spi_imx_calculate_timeout()
1275 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; in spi_imx_calculate_timeout()
1290 struct spi_master *master = spi_imx->bitbang.master; in spi_imx_dma_transfer()
1291 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in spi_imx_dma_transfer()
1297 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, in spi_imx_dma_transfer()
1298 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in spi_imx_dma_transfer()
1301 return -EINVAL; in spi_imx_dma_transfer()
1303 desc_rx->callback = spi_imx_dma_rx_callback; in spi_imx_dma_transfer()
1304 desc_rx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1306 reinit_completion(&spi_imx->dma_rx_completion); in spi_imx_dma_transfer()
1307 dma_async_issue_pending(master->dma_rx); in spi_imx_dma_transfer()
1309 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, in spi_imx_dma_transfer()
1310 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in spi_imx_dma_transfer()
1313 dmaengine_terminate_all(master->dma_tx); in spi_imx_dma_transfer()
1314 return -EINVAL; in spi_imx_dma_transfer()
1317 desc_tx->callback = spi_imx_dma_tx_callback; in spi_imx_dma_transfer()
1318 desc_tx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1320 reinit_completion(&spi_imx->dma_tx_completion); in spi_imx_dma_transfer()
1321 dma_async_issue_pending(master->dma_tx); in spi_imx_dma_transfer()
1323 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_dma_transfer()
1326 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, in spi_imx_dma_transfer()
1329 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); in spi_imx_dma_transfer()
1330 dmaengine_terminate_all(master->dma_tx); in spi_imx_dma_transfer()
1331 dmaengine_terminate_all(master->dma_rx); in spi_imx_dma_transfer()
1332 return -ETIMEDOUT; in spi_imx_dma_transfer()
1335 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, in spi_imx_dma_transfer()
1338 dev_err(&master->dev, "I/O Error in DMA RX\n"); in spi_imx_dma_transfer()
1339 spi_imx->devtype_data->reset(spi_imx); in spi_imx_dma_transfer()
1340 dmaengine_terminate_all(master->dma_rx); in spi_imx_dma_transfer()
1341 return -ETIMEDOUT; in spi_imx_dma_transfer()
1344 return transfer->len; in spi_imx_dma_transfer()
1350 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_pio_transfer()
1354 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer()
1355 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer()
1356 spi_imx->count = transfer->len; in spi_imx_pio_transfer()
1357 spi_imx->txfifo = 0; in spi_imx_pio_transfer()
1358 spi_imx->remainder = 0; in spi_imx_pio_transfer()
1360 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer()
1364 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); in spi_imx_pio_transfer()
1366 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_pio_transfer()
1368 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, in spi_imx_pio_transfer()
1371 dev_err(&spi->dev, "I/O Error in PIO\n"); in spi_imx_pio_transfer()
1372 spi_imx->devtype_data->reset(spi_imx); in spi_imx_pio_transfer()
1373 return -ETIMEDOUT; in spi_imx_pio_transfer()
1376 return transfer->len; in spi_imx_pio_transfer()
1382 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_pio_transfer_slave()
1383 int ret = transfer->len; in spi_imx_pio_transfer_slave()
1386 transfer->len > MX53_MAX_TRANSFER_BYTES) { in spi_imx_pio_transfer_slave()
1387 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", in spi_imx_pio_transfer_slave()
1389 return -EMSGSIZE; in spi_imx_pio_transfer_slave()
1392 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer_slave()
1393 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer_slave()
1394 spi_imx->count = transfer->len; in spi_imx_pio_transfer_slave()
1395 spi_imx->txfifo = 0; in spi_imx_pio_transfer_slave()
1396 spi_imx->remainder = 0; in spi_imx_pio_transfer_slave()
1398 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer_slave()
1399 spi_imx->slave_aborted = false; in spi_imx_pio_transfer_slave()
1403 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); in spi_imx_pio_transfer_slave()
1405 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || in spi_imx_pio_transfer_slave()
1406 spi_imx->slave_aborted) { in spi_imx_pio_transfer_slave()
1407 dev_dbg(&spi->dev, "interrupted\n"); in spi_imx_pio_transfer_slave()
1408 ret = -EINTR; in spi_imx_pio_transfer_slave()
1417 if (spi_imx->devtype_data->disable) in spi_imx_pio_transfer_slave()
1418 spi_imx->devtype_data->disable(spi_imx); in spi_imx_pio_transfer_slave()
1426 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_transfer()
1429 while (spi_imx->devtype_data->rx_available(spi_imx)) in spi_imx_transfer()
1430 readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_transfer()
1432 if (spi_imx->slave_mode) in spi_imx_transfer()
1435 if (spi_imx->usedma) in spi_imx_transfer()
1443 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, in spi_imx_setup()
1444 spi->mode, spi->bits_per_word, spi->max_speed_hz); in spi_imx_setup()
1446 if (spi->mode & SPI_NO_CS) in spi_imx_setup()
1449 if (gpio_is_valid(spi->cs_gpio)) in spi_imx_setup()
1450 gpio_direction_output(spi->cs_gpio, in spi_imx_setup()
1451 spi->mode & SPI_CS_HIGH ? 0 : 1); in spi_imx_setup()
1468 ret = clk_enable(spi_imx->clk_per); in spi_imx_prepare_message()
1472 ret = clk_enable(spi_imx->clk_ipg); in spi_imx_prepare_message()
1474 clk_disable(spi_imx->clk_per); in spi_imx_prepare_message()
1486 clk_disable(spi_imx->clk_ipg); in spi_imx_unprepare_message()
1487 clk_disable(spi_imx->clk_per); in spi_imx_unprepare_message()
1495 spi_imx->slave_aborted = true; in spi_imx_slave_abort()
1496 complete(&spi_imx->xfer_done); in spi_imx_slave_abort()
1503 struct device_node *np = pdev->dev.of_node; in spi_imx_probe()
1505 of_match_device(spi_imx_dt_ids, &pdev->dev); in spi_imx_probe()
1507 dev_get_platdata(&pdev->dev); in spi_imx_probe()
1512 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data : in spi_imx_probe()
1513 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; in spi_imx_probe()
1517 dev_err(&pdev->dev, "can't get the platform data\n"); in spi_imx_probe()
1518 return -EINVAL; in spi_imx_probe()
1521 slave_mode = devtype_data->has_slavemode && in spi_imx_probe()
1522 of_property_read_bool(np, "spi-slave"); in spi_imx_probe()
1524 master = spi_alloc_slave(&pdev->dev, in spi_imx_probe()
1527 master = spi_alloc_master(&pdev->dev, in spi_imx_probe()
1530 return -ENOMEM; in spi_imx_probe()
1532 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); in spi_imx_probe()
1540 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in spi_imx_probe()
1541 master->bus_num = np ? -1 : pdev->id; in spi_imx_probe()
1544 spi_imx->bitbang.master = master; in spi_imx_probe()
1545 spi_imx->dev = &pdev->dev; in spi_imx_probe()
1546 spi_imx->slave_mode = slave_mode; in spi_imx_probe()
1548 spi_imx->devtype_data = devtype_data; in spi_imx_probe()
1552 master->num_chipselect = mxc_platform_info->num_chipselect; in spi_imx_probe()
1553 if (mxc_platform_info->chipselect) { in spi_imx_probe()
1554 master->cs_gpios = devm_kcalloc(&master->dev, in spi_imx_probe()
1555 master->num_chipselect, sizeof(int), in spi_imx_probe()
1557 if (!master->cs_gpios) in spi_imx_probe()
1558 return -ENOMEM; in spi_imx_probe()
1560 for (i = 0; i < master->num_chipselect; i++) in spi_imx_probe()
1561 master->cs_gpios[i] = mxc_platform_info->chipselect[i]; in spi_imx_probe()
1566 if (!of_property_read_u32(np, "num-cs", &num_cs)) in spi_imx_probe()
1567 master->num_chipselect = num_cs; in spi_imx_probe()
1571 spi_imx->bitbang.chipselect = spi_imx_chipselect; in spi_imx_probe()
1572 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; in spi_imx_probe()
1573 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; in spi_imx_probe()
1574 spi_imx->bitbang.master->setup = spi_imx_setup; in spi_imx_probe()
1575 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; in spi_imx_probe()
1576 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; in spi_imx_probe()
1577 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; in spi_imx_probe()
1578 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; in spi_imx_probe()
1579 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ in spi_imx_probe()
1583 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; in spi_imx_probe()
1585 spi_imx->spi_drctl = spi_drctl; in spi_imx_probe()
1587 init_completion(&spi_imx->xfer_done); in spi_imx_probe()
1590 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); in spi_imx_probe()
1591 if (IS_ERR(spi_imx->base)) { in spi_imx_probe()
1592 ret = PTR_ERR(spi_imx->base); in spi_imx_probe()
1595 spi_imx->base_phys = res->start; in spi_imx_probe()
1603 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, in spi_imx_probe()
1604 dev_name(&pdev->dev), spi_imx); in spi_imx_probe()
1606 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in spi_imx_probe()
1610 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in spi_imx_probe()
1611 if (IS_ERR(spi_imx->clk_ipg)) { in spi_imx_probe()
1612 ret = PTR_ERR(spi_imx->clk_ipg); in spi_imx_probe()
1616 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); in spi_imx_probe()
1617 if (IS_ERR(spi_imx->clk_per)) { in spi_imx_probe()
1618 ret = PTR_ERR(spi_imx->clk_per); in spi_imx_probe()
1622 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_probe()
1626 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_probe()
1630 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); in spi_imx_probe()
1635 if (spi_imx->devtype_data->has_dmamode) { in spi_imx_probe()
1636 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); in spi_imx_probe()
1637 if (ret == -EPROBE_DEFER) in spi_imx_probe()
1641 dev_err(&pdev->dev, "dma setup error %d, use pio\n", in spi_imx_probe()
1645 spi_imx->devtype_data->reset(spi_imx); in spi_imx_probe()
1647 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_probe()
1649 master->dev.of_node = pdev->dev.of_node; in spi_imx_probe()
1650 ret = spi_bitbang_start(&spi_imx->bitbang); in spi_imx_probe()
1652 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); in spi_imx_probe()
1657 if (!spi_imx->slave_mode && master->cs_gpios) { in spi_imx_probe()
1658 for (i = 0; i < master->num_chipselect; i++) { in spi_imx_probe()
1659 if (!gpio_is_valid(master->cs_gpios[i])) in spi_imx_probe()
1662 ret = devm_gpio_request(&pdev->dev, in spi_imx_probe()
1663 master->cs_gpios[i], in spi_imx_probe()
1666 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", in spi_imx_probe()
1667 master->cs_gpios[i]); in spi_imx_probe()
1673 dev_info(&pdev->dev, "probed\n"); in spi_imx_probe()
1675 clk_disable(spi_imx->clk_ipg); in spi_imx_probe()
1676 clk_disable(spi_imx->clk_per); in spi_imx_probe()
1680 spi_bitbang_stop(&spi_imx->bitbang); in spi_imx_probe()
1682 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_probe()
1684 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_probe()
1697 spi_bitbang_stop(&spi_imx->bitbang); in spi_imx_remove()
1699 ret = clk_enable(spi_imx->clk_per); in spi_imx_remove()
1703 ret = clk_enable(spi_imx->clk_ipg); in spi_imx_remove()
1705 clk_disable(spi_imx->clk_per); in spi_imx_remove()
1709 writel(0, spi_imx->base + MXC_CSPICTRL); in spi_imx_remove()
1710 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_remove()
1711 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_remove()