Lines Matching +full:rx +full:- +full:ctrl
21 #include <linux/dma-mapping.h>
35 u32 ctrl; member
54 #define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
69 #define CTRL_SMP BIT(9) /* Rx at middle or end of tx */
83 #define STAT_RF_EMPTY BIT(5) /* RX Fifo empty */
96 #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */
97 #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */
113 u32 speed_hz; /* spi-clk rate */
124 const void *rx; member
133 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set); in pic32_spi_enable()
138 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr); in pic32_spi_disable()
148 /* div = (clk_in / 2 * spi_ck) - 1 */ in pic32_spi_set_clk_rate()
149 div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1; in pic32_spi_set_clk_rate()
151 writel(div & BAUD_MASK, &pic32s->regs->baud); in pic32_spi_set_clk_rate()
156 u32 sr = readl(&pic32s->regs->status); in pic32_rx_fifo_level()
163 u32 sr = readl(&pic32s->regs->status); in pic32_tx_fifo_level()
173 tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes; in pic32_tx_max()
174 tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s); in pic32_tx_max()
177 * Another concern is about the tx/rx mismatch, we in pic32_tx_max()
178 * though to use (pic32s->fifo_n_byte - rxfl - txfl) as in pic32_tx_max()
180 * data which is out of tx/rx fifo and inside the in pic32_tx_max()
181 * shift registers. So a ctrl from sw point of in pic32_tx_max()
184 rxtx_gap = ((pic32s->rx_end - pic32s->rx) - in pic32_tx_max()
185 (pic32s->tx_end - pic32s->tx)) / n_bytes; in pic32_tx_max()
186 return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap)); in pic32_tx_max()
189 /* Return the max entries we should read out of rx fifo */
192 u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes; in pic32_rx_max()
202 for (; mx; mx--) { \
203 v = read##__bwl(&pic32s->regs->buf); \
204 if (pic32s->rx_end - pic32s->len) \
205 *(__type *)(pic32s->rx) = v; \
206 pic32s->rx += sizeof(__type); \
214 for (; mx ; mx--) { \
216 if (pic32s->tx_end - pic32s->len) \
217 v = *(__type *)(pic32s->tx); \
218 write##__bwl(v, &pic32s->regs->buf); \
219 pic32s->tx += sizeof(__type); \
230 disable_irq_nosync(pic32s->fault_irq); in pic32_err_stop()
231 disable_irq_nosync(pic32s->rx_irq); in pic32_err_stop()
232 disable_irq_nosync(pic32s->tx_irq); in pic32_err_stop()
235 dev_err(&pic32s->master->dev, "%s\n", msg); in pic32_err_stop()
236 if (pic32s->master->cur_msg) in pic32_err_stop()
237 pic32s->master->cur_msg->status = -EIO; in pic32_err_stop()
238 complete(&pic32s->xfer_done); in pic32_err_stop()
246 status = readl(&pic32s->regs->status); in pic32_spi_fault_irq()
250 writel(STAT_RX_OV, &pic32s->regs->status_clr); in pic32_spi_fault_irq()
251 writel(STAT_TX_UR, &pic32s->regs->status_clr); in pic32_spi_fault_irq()
252 pic32_err_stop(pic32s, "err_irq: fifo ov/ur-run\n"); in pic32_spi_fault_irq()
261 if (!pic32s->master->cur_msg) { in pic32_spi_fault_irq()
273 pic32s->rx_fifo(pic32s); in pic32_spi_rx_irq()
275 /* rx complete ? */ in pic32_spi_rx_irq()
276 if (pic32s->rx_end == pic32s->rx) { in pic32_spi_rx_irq()
278 disable_irq_nosync(pic32s->fault_irq); in pic32_spi_rx_irq()
279 disable_irq_nosync(pic32s->rx_irq); in pic32_spi_rx_irq()
282 complete(&pic32s->xfer_done); in pic32_spi_rx_irq()
292 pic32s->tx_fifo(pic32s); in pic32_spi_tx_irq()
295 if (pic32s->tx_end == pic32s->tx) in pic32_spi_tx_irq()
296 disable_irq_nosync(pic32s->tx_irq); in pic32_spi_tx_irq()
305 complete(&pic32s->xfer_done); in pic32_spi_dma_rx_notify()
311 struct spi_master *master = pic32s->master; in pic32_spi_dma_transfer()
317 if (!master->dma_rx || !master->dma_tx) in pic32_spi_dma_transfer()
318 return -ENODEV; in pic32_spi_dma_transfer()
320 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, in pic32_spi_dma_transfer()
321 xfer->rx_sg.sgl, in pic32_spi_dma_transfer()
322 xfer->rx_sg.nents, in pic32_spi_dma_transfer()
326 ret = -EINVAL; in pic32_spi_dma_transfer()
330 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, in pic32_spi_dma_transfer()
331 xfer->tx_sg.sgl, in pic32_spi_dma_transfer()
332 xfer->tx_sg.nents, in pic32_spi_dma_transfer()
336 ret = -EINVAL; in pic32_spi_dma_transfer()
340 /* Put callback on the RX transfer, that should finish last */ in pic32_spi_dma_transfer()
341 desc_rx->callback = pic32_spi_dma_rx_notify; in pic32_spi_dma_transfer()
342 desc_rx->callback_param = pic32s; in pic32_spi_dma_transfer()
354 dma_async_issue_pending(master->dma_rx); in pic32_spi_dma_transfer()
355 dma_async_issue_pending(master->dma_tx); in pic32_spi_dma_transfer()
360 dmaengine_terminate_all(master->dma_rx); in pic32_spi_dma_transfer()
368 struct spi_master *master = pic32s->master; in pic32_spi_dma_config()
373 cfg.src_addr = pic32s->dma_base + buf_offset; in pic32_spi_dma_config()
374 cfg.dst_addr = pic32s->dma_base + buf_offset; in pic32_spi_dma_config()
375 cfg.src_maxburst = pic32s->fifo_n_elm / 2; /* fill one-half */ in pic32_spi_dma_config()
376 cfg.dst_maxburst = pic32s->fifo_n_elm / 2; /* drain one-half */ in pic32_spi_dma_config()
380 cfg.slave_id = pic32s->tx_irq; in pic32_spi_dma_config()
382 ret = dmaengine_slave_config(master->dma_tx, &cfg); in pic32_spi_dma_config()
384 dev_err(&master->dev, "tx channel setup failed\n"); in pic32_spi_dma_config()
387 /* rx channel */ in pic32_spi_dma_config()
388 cfg.slave_id = pic32s->rx_irq; in pic32_spi_dma_config()
390 ret = dmaengine_slave_config(master->dma_rx, &cfg); in pic32_spi_dma_config()
392 dev_err(&master->dev, "rx channel setup failed\n"); in pic32_spi_dma_config()
404 pic32s->rx_fifo = pic32_spi_rx_byte; in pic32_spi_set_word_size()
405 pic32s->tx_fifo = pic32_spi_tx_byte; in pic32_spi_set_word_size()
410 pic32s->rx_fifo = pic32_spi_rx_word; in pic32_spi_set_word_size()
411 pic32s->tx_fifo = pic32_spi_tx_word; in pic32_spi_set_word_size()
416 pic32s->rx_fifo = pic32_spi_rx_dword; in pic32_spi_set_word_size()
417 pic32s->tx_fifo = pic32_spi_tx_dword; in pic32_spi_set_word_size()
423 return -EINVAL; in pic32_spi_set_word_size()
427 pic32s->fifo_n_elm = DIV_ROUND_UP(pic32s->fifo_n_byte, in pic32_spi_set_word_size()
430 v = readl(&pic32s->regs->ctrl); in pic32_spi_set_word_size()
433 writel(v, &pic32s->regs->ctrl); in pic32_spi_set_word_size()
435 /* re-configure dma width, if required */ in pic32_spi_set_word_size()
436 if (test_bit(PIC32F_DMA_PREP, &pic32s->flags)) in pic32_spi_set_word_size()
455 struct spi_device *spi = msg->spi; in pic32_spi_prepare_message()
459 if (pic32s->bits_per_word != spi->bits_per_word) { in pic32_spi_prepare_message()
460 pic32_spi_set_word_size(pic32s, spi->bits_per_word); in pic32_spi_prepare_message()
461 pic32s->bits_per_word = spi->bits_per_word; in pic32_spi_prepare_message()
465 if (pic32s->speed_hz != spi->max_speed_hz) { in pic32_spi_prepare_message()
466 pic32_spi_set_clk_rate(pic32s, spi->max_speed_hz); in pic32_spi_prepare_message()
467 pic32s->speed_hz = spi->max_speed_hz; in pic32_spi_prepare_message()
471 if (pic32s->mode != spi->mode) { in pic32_spi_prepare_message()
472 val = readl(&pic32s->regs->ctrl); in pic32_spi_prepare_message()
474 if (spi->mode & SPI_CPOL) in pic32_spi_prepare_message()
479 if (spi->mode & SPI_CPHA) in pic32_spi_prepare_message()
484 /* rx at end of tx */ in pic32_spi_prepare_message()
486 writel(val, &pic32s->regs->ctrl); in pic32_spi_prepare_message()
487 pic32s->mode = spi->mode; in pic32_spi_prepare_message()
500 return (xfer->len >= PIC32_DMA_LEN_MIN) && in pic32_spi_can_dma()
501 test_bit(PIC32F_DMA_PREP, &pic32s->flags); in pic32_spi_can_dma()
516 if (transfer->bits_per_word && in pic32_spi_one_transfer()
517 (transfer->bits_per_word != pic32s->bits_per_word)) { in pic32_spi_one_transfer()
518 ret = pic32_spi_set_word_size(pic32s, transfer->bits_per_word); in pic32_spi_one_transfer()
521 pic32s->bits_per_word = transfer->bits_per_word; in pic32_spi_one_transfer()
525 if (transfer->speed_hz && (transfer->speed_hz != pic32s->speed_hz)) { in pic32_spi_one_transfer()
526 pic32_spi_set_clk_rate(pic32s, transfer->speed_hz); in pic32_spi_one_transfer()
527 pic32s->speed_hz = transfer->speed_hz; in pic32_spi_one_transfer()
530 reinit_completion(&pic32s->xfer_done); in pic32_spi_one_transfer()
533 if (transfer->rx_sg.nents && transfer->tx_sg.nents) { in pic32_spi_one_transfer()
536 dev_err(&spi->dev, "dma submit error\n"); in pic32_spi_one_transfer()
544 pic32s->tx = (const void *)transfer->tx_buf; in pic32_spi_one_transfer()
545 pic32s->rx = (const void *)transfer->rx_buf; in pic32_spi_one_transfer()
546 pic32s->tx_end = pic32s->tx + transfer->len; in pic32_spi_one_transfer()
547 pic32s->rx_end = pic32s->rx + transfer->len; in pic32_spi_one_transfer()
548 pic32s->len = transfer->len; in pic32_spi_one_transfer()
551 enable_irq(pic32s->fault_irq); in pic32_spi_one_transfer()
552 enable_irq(pic32s->rx_irq); in pic32_spi_one_transfer()
553 enable_irq(pic32s->tx_irq); in pic32_spi_one_transfer()
557 timeout = wait_for_completion_timeout(&pic32s->xfer_done, 2 * HZ); in pic32_spi_one_transfer()
559 dev_err(&spi->dev, "wait error/timedout\n"); in pic32_spi_one_transfer()
561 dmaengine_terminate_all(master->dma_rx); in pic32_spi_one_transfer()
562 dmaengine_terminate_all(master->dma_rx); in pic32_spi_one_transfer()
564 ret = -ETIMEDOUT; in pic32_spi_one_transfer()
591 if (!spi->max_speed_hz) { in pic32_spi_setup()
592 dev_err(&spi->dev, "No max speed HZ parameter\n"); in pic32_spi_setup()
593 return -EINVAL; in pic32_spi_setup()
597 * on tx fifo fill-level. /CS will stay asserted as long as TX in pic32_spi_setup()
598 * fifo is non-empty, else will be deasserted indicating in pic32_spi_setup()
603 if (!gpio_is_valid(spi->cs_gpio)) in pic32_spi_setup()
604 return -EINVAL; in pic32_spi_setup()
606 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); in pic32_spi_setup()
613 /* de-activate cs-gpio */ in pic32_spi_cleanup()
614 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); in pic32_spi_cleanup()
619 struct spi_master *master = pic32s->master; in pic32_spi_dma_prep()
625 master->dma_rx = dma_request_slave_channel_compat(mask, NULL, NULL, in pic32_spi_dma_prep()
626 dev, "spi-rx"); in pic32_spi_dma_prep()
627 if (!master->dma_rx) { in pic32_spi_dma_prep()
628 dev_warn(dev, "RX channel not found.\n"); in pic32_spi_dma_prep()
632 master->dma_tx = dma_request_slave_channel_compat(mask, NULL, NULL, in pic32_spi_dma_prep()
633 dev, "spi-tx"); in pic32_spi_dma_prep()
634 if (!master->dma_tx) { in pic32_spi_dma_prep()
643 set_bit(PIC32F_DMA_PREP, &pic32s->flags); in pic32_spi_dma_prep()
648 if (master->dma_rx) in pic32_spi_dma_prep()
649 dma_release_channel(master->dma_rx); in pic32_spi_dma_prep()
651 if (master->dma_tx) in pic32_spi_dma_prep()
652 dma_release_channel(master->dma_tx); in pic32_spi_dma_prep()
657 if (!test_bit(PIC32F_DMA_PREP, &pic32s->flags)) in pic32_spi_dma_unprep()
660 clear_bit(PIC32F_DMA_PREP, &pic32s->flags); in pic32_spi_dma_unprep()
661 if (pic32s->master->dma_rx) in pic32_spi_dma_unprep()
662 dma_release_channel(pic32s->master->dma_rx); in pic32_spi_dma_unprep()
664 if (pic32s->master->dma_tx) in pic32_spi_dma_unprep()
665 dma_release_channel(pic32s->master->dma_tx); in pic32_spi_dma_unprep()
670 u32 ctrl; in pic32_spi_hw_init() local
675 ctrl = readl(&pic32s->regs->ctrl); in pic32_spi_hw_init()
677 ctrl |= CTRL_ENHBUF; in pic32_spi_hw_init()
678 pic32s->fifo_n_byte = 16; in pic32_spi_hw_init()
681 ctrl &= ~CTRL_FRMEN; in pic32_spi_hw_init()
684 ctrl |= CTRL_MSTEN; in pic32_spi_hw_init()
687 ctrl &= ~(0x3 << CTRL_TX_INT_SHIFT); in pic32_spi_hw_init()
688 ctrl |= (TX_FIFO_HALF_EMPTY << CTRL_TX_INT_SHIFT); in pic32_spi_hw_init()
690 /* set rx fifo threshold interrupt */ in pic32_spi_hw_init()
691 ctrl &= ~(0x3 << CTRL_RX_INT_SHIFT); in pic32_spi_hw_init()
692 ctrl |= (RX_FIFO_NOT_EMPTY << CTRL_RX_INT_SHIFT); in pic32_spi_hw_init()
695 ctrl &= ~CTRL_MCLKSEL; in pic32_spi_hw_init()
698 ctrl &= ~CTRL_MSSEN; in pic32_spi_hw_init()
700 writel(ctrl, &pic32s->regs->ctrl); in pic32_spi_hw_init()
703 ctrl = CTRL2_TX_UR_EN | CTRL2_RX_OV_EN | CTRL2_FRM_ERR_EN; in pic32_spi_hw_init()
704 writel(ctrl, &pic32s->regs->ctrl2_set); in pic32_spi_hw_init()
714 pic32s->regs = devm_ioremap_resource(&pdev->dev, mem); in pic32_spi_hw_probe()
715 if (IS_ERR(pic32s->regs)) in pic32_spi_hw_probe()
716 return PTR_ERR(pic32s->regs); in pic32_spi_hw_probe()
718 pic32s->dma_base = mem->start; in pic32_spi_hw_probe()
720 /* get irq resources: err-irq, rx-irq, tx-irq */ in pic32_spi_hw_probe()
721 pic32s->fault_irq = platform_get_irq_byname(pdev, "fault"); in pic32_spi_hw_probe()
722 if (pic32s->fault_irq < 0) { in pic32_spi_hw_probe()
723 dev_err(&pdev->dev, "fault-irq not found\n"); in pic32_spi_hw_probe()
724 return pic32s->fault_irq; in pic32_spi_hw_probe()
727 pic32s->rx_irq = platform_get_irq_byname(pdev, "rx"); in pic32_spi_hw_probe()
728 if (pic32s->rx_irq < 0) { in pic32_spi_hw_probe()
729 dev_err(&pdev->dev, "rx-irq not found\n"); in pic32_spi_hw_probe()
730 return pic32s->rx_irq; in pic32_spi_hw_probe()
733 pic32s->tx_irq = platform_get_irq_byname(pdev, "tx"); in pic32_spi_hw_probe()
734 if (pic32s->tx_irq < 0) { in pic32_spi_hw_probe()
735 dev_err(&pdev->dev, "tx-irq not found\n"); in pic32_spi_hw_probe()
736 return pic32s->tx_irq; in pic32_spi_hw_probe()
740 pic32s->clk = devm_clk_get(&pdev->dev, "mck0"); in pic32_spi_hw_probe()
741 if (IS_ERR(pic32s->clk)) { in pic32_spi_hw_probe()
742 dev_err(&pdev->dev, "clk not found\n"); in pic32_spi_hw_probe()
743 ret = PTR_ERR(pic32s->clk); in pic32_spi_hw_probe()
747 ret = clk_prepare_enable(pic32s->clk); in pic32_spi_hw_probe()
756 dev_err(&pdev->dev, "%s failed, err %d\n", __func__, ret); in pic32_spi_hw_probe()
766 master = spi_alloc_master(&pdev->dev, sizeof(*pic32s)); in pic32_spi_probe()
768 return -ENOMEM; in pic32_spi_probe()
771 pic32s->master = master; in pic32_spi_probe()
777 master->dev.of_node = of_node_get(pdev->dev.of_node); in pic32_spi_probe()
778 master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH; in pic32_spi_probe()
779 master->num_chipselect = 1; /* single chip-select */ in pic32_spi_probe()
780 master->max_speed_hz = clk_get_rate(pic32s->clk); in pic32_spi_probe()
781 master->setup = pic32_spi_setup; in pic32_spi_probe()
782 master->cleanup = pic32_spi_cleanup; in pic32_spi_probe()
783 master->flags = SPI_MASTER_MUST_TX | SPI_MASTER_MUST_RX; in pic32_spi_probe()
784 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | in pic32_spi_probe()
786 master->transfer_one = pic32_spi_one_transfer; in pic32_spi_probe()
787 master->prepare_message = pic32_spi_prepare_message; in pic32_spi_probe()
788 master->unprepare_message = pic32_spi_unprepare_message; in pic32_spi_probe()
789 master->prepare_transfer_hardware = pic32_spi_prepare_hardware; in pic32_spi_probe()
790 master->unprepare_transfer_hardware = pic32_spi_unprepare_hardware; in pic32_spi_probe()
793 pic32_spi_dma_prep(pic32s, &pdev->dev); in pic32_spi_probe()
794 if (test_bit(PIC32F_DMA_PREP, &pic32s->flags)) in pic32_spi_probe()
795 master->can_dma = pic32_spi_can_dma; in pic32_spi_probe()
797 init_completion(&pic32s->xfer_done); in pic32_spi_probe()
798 pic32s->mode = -1; in pic32_spi_probe()
800 /* install irq handlers (with irq-disabled) */ in pic32_spi_probe()
801 irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN); in pic32_spi_probe()
802 ret = devm_request_irq(&pdev->dev, pic32s->fault_irq, in pic32_spi_probe()
804 dev_name(&pdev->dev), pic32s); in pic32_spi_probe()
806 dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq); in pic32_spi_probe()
811 irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN); in pic32_spi_probe()
812 ret = devm_request_irq(&pdev->dev, pic32s->rx_irq, in pic32_spi_probe()
814 dev_name(&pdev->dev), pic32s); in pic32_spi_probe()
816 dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq); in pic32_spi_probe()
821 irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN); in pic32_spi_probe()
822 ret = devm_request_irq(&pdev->dev, pic32s->tx_irq, in pic32_spi_probe()
824 dev_name(&pdev->dev), pic32s); in pic32_spi_probe()
826 dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq); in pic32_spi_probe()
831 ret = devm_spi_register_master(&pdev->dev, master); in pic32_spi_probe()
833 dev_err(&master->dev, "failed registering spi master\n"); in pic32_spi_probe()
842 clk_disable_unprepare(pic32s->clk); in pic32_spi_probe()
854 clk_disable_unprepare(pic32s->clk); in pic32_spi_remove()
861 {.compatible = "microchip,pic32mzda-spi",},
868 .name = "spi-pic32",