Lines Matching +full:max +full:- +full:channels +full:- +full:clocked
4 * Copyright (C) 2008-2012 ST-Ericsson AB
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
40 #include <linux/dma-mapping.h>
102 * SSP Control Register 0 - SSP_CR0
120 * SSP Control Register 0 - SSP_CR1
140 * SSP Status Register - SSP_SR
149 * SSP Clock Prescale Register - SSP_CPSR
154 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
162 * SSP Raw Interrupt Status Register - SSP_RIS
174 * SSP Masked Interrupt Status Register - SSP_MIS
186 * SSP Interrupt Clear Register - SSP_ICR
194 * SSP DMA Control Register - SSP_DMACR
202 * SSP Chip Select Control Register - SSP_CSR
208 * SSP Integration Test control Register - SSP_ITCR
214 * SSP Integration Test Input Register - SSP_ITIP
224 * SSP Integration Test output Register - SSP_ITOP
242 * SSP Test Data Register - SSP_TDR
255 #define STATE_ERROR ((void *) -1)
258 * SSP State - Whether Enabled or Disabled
264 * SSP DMA State - Whether DMA Enabled or Disabled
320 * struct vendor_data - vendor-specific config parameters
341 * struct pl022 - This is the private SSP driver data structure
348 * @master_info: controller-specific data from machine setup
380 /* Message per-transfer pump */
409 * struct chip_data - To maintain runtime state of SSP for each client chip
410 * @cr0: Value of control register CR0 of SSP - on later ST variants this
439 * null_cs_control - Dummy chip select function
451 * internal_cs_control - Control chip select signals via SSP_CSR.
463 tmp = readw(SSP_CSR(pl022->virtbase)); in internal_cs_control()
465 tmp &= ~BIT(pl022->cur_cs); in internal_cs_control()
467 tmp |= BIT(pl022->cur_cs); in internal_cs_control()
468 writew(tmp, SSP_CSR(pl022->virtbase)); in internal_cs_control()
473 if (pl022->vendor->internal_cs_ctrl) in pl022_cs_control()
475 else if (gpio_is_valid(pl022->cur_cs)) in pl022_cs_control()
476 gpio_set_value(pl022->cur_cs, command); in pl022_cs_control()
478 pl022->cur_chip->cs_control(command); in pl022_cs_control()
482 * giveback - current spi_message is over, schedule next message and call
484 * set message->status; dma and pio irqs are blocked
490 pl022->next_msg_cs_active = false; in giveback()
492 last_transfer = list_last_entry(&pl022->cur_msg->transfers, in giveback()
496 if (last_transfer->delay_usecs) in giveback()
501 udelay(last_transfer->delay_usecs); in giveback()
503 if (!last_transfer->cs_change) { in giveback()
512 * after calling msg->complete (below) the driver that in giveback()
517 next_msg = spi_get_next_queued_message(pl022->master); in giveback()
523 if (next_msg && next_msg->spi != pl022->cur_msg->spi) in giveback()
525 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) in giveback()
528 pl022->next_msg_cs_active = true; in giveback()
532 pl022->cur_msg = NULL; in giveback()
533 pl022->cur_transfer = NULL; in giveback()
534 pl022->cur_chip = NULL; in giveback()
537 writew((readw(SSP_CR1(pl022->virtbase)) & in giveback()
538 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in giveback()
540 spi_finalize_current_message(pl022->master); in giveback()
544 * flush - flush the FIFO to reach a clean state
551 dev_dbg(&pl022->adev->dev, "flush\n"); in flush()
553 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in flush()
554 readw(SSP_DR(pl022->virtbase)); in flush()
555 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); in flush()
557 pl022->exp_fifo_level = 0; in flush()
563 * restore_state - Load configuration of current chip
568 struct chip_data *chip = pl022->cur_chip; in restore_state()
570 if (pl022->vendor->extended_cr) in restore_state()
571 writel(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
573 writew(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
574 writew(chip->cr1, SSP_CR1(pl022->virtbase)); in restore_state()
575 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); in restore_state()
576 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); in restore_state()
577 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in restore_state()
578 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in restore_state()
653 * load_ssp_default_config - Load default configuration for SSP
658 if (pl022->vendor->pl023) { in load_ssp_default_config()
659 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
660 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
661 } else if (pl022->vendor->extended_cr) { in load_ssp_default_config()
662 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
663 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
665 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
666 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
668 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); in load_ssp_default_config()
669 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); in load_ssp_default_config()
670 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in load_ssp_default_config()
671 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in load_ssp_default_config()
691 dev_dbg(&pl022->adev->dev, in readwriter()
693 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); in readwriter()
696 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
697 && (pl022->rx < pl022->rx_end)) { in readwriter()
698 switch (pl022->read) { in readwriter()
700 readw(SSP_DR(pl022->virtbase)); in readwriter()
703 *(u8 *) (pl022->rx) = in readwriter()
704 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
707 *(u16 *) (pl022->rx) = in readwriter()
708 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
711 *(u32 *) (pl022->rx) = in readwriter()
712 readl(SSP_DR(pl022->virtbase)); in readwriter()
715 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
716 pl022->exp_fifo_level--; in readwriter()
721 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) in readwriter()
722 && (pl022->tx < pl022->tx_end)) { in readwriter()
723 switch (pl022->write) { in readwriter()
725 writew(0x0, SSP_DR(pl022->virtbase)); in readwriter()
728 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
731 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); in readwriter()
734 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
737 pl022->tx += (pl022->cur_chip->n_bytes); in readwriter()
738 pl022->exp_fifo_level++; in readwriter()
743 * and then things are continuously clocked into the RX FIFO. in readwriter()
745 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
746 && (pl022->rx < pl022->rx_end)) { in readwriter()
747 switch (pl022->read) { in readwriter()
749 readw(SSP_DR(pl022->virtbase)); in readwriter()
752 *(u8 *) (pl022->rx) = in readwriter()
753 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
756 *(u16 *) (pl022->rx) = in readwriter()
757 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
760 *(u32 *) (pl022->rx) = in readwriter()
761 readl(SSP_DR(pl022->virtbase)); in readwriter()
764 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
765 pl022->exp_fifo_level--; in readwriter()
775 * next_transfer - Move to the Next transfer in the current spi message
785 struct spi_message *msg = pl022->cur_msg; in next_transfer()
786 struct spi_transfer *trans = pl022->cur_transfer; in next_transfer()
789 if (trans->transfer_list.next != &msg->transfers) { in next_transfer()
790 pl022->cur_transfer = in next_transfer()
791 list_entry(trans->transfer_list.next, in next_transfer()
806 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, in unmap_free_dma_scatter()
807 pl022->sgt_tx.nents, DMA_TO_DEVICE); in unmap_free_dma_scatter()
808 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, in unmap_free_dma_scatter()
809 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in unmap_free_dma_scatter()
810 sg_free_table(&pl022->sgt_rx); in unmap_free_dma_scatter()
811 sg_free_table(&pl022->sgt_tx); in unmap_free_dma_scatter()
817 struct spi_message *msg = pl022->cur_msg; in dma_callback()
819 BUG_ON(!pl022->sgt_rx.sgl); in dma_callback()
832 dma_sync_sg_for_cpu(&pl022->adev->dev, in dma_callback()
833 pl022->sgt_rx.sgl, in dma_callback()
834 pl022->sgt_rx.nents, in dma_callback()
837 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { in dma_callback()
838 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); in dma_callback()
847 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { in dma_callback()
848 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); in dma_callback()
863 msg->actual_length += pl022->cur_transfer->len; in dma_callback()
864 if (pl022->cur_transfer->cs_change) in dma_callback()
868 msg->state = next_transfer(pl022); in dma_callback()
869 tasklet_schedule(&pl022->pump_transfers); in dma_callback()
884 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
891 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) in setup_dma_scatter()
894 mapbytes = PAGE_SIZE - offset_in_page(bufp); in setup_dma_scatter()
898 bytesleft -= mapbytes; in setup_dma_scatter()
899 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
905 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
910 sg_set_page(sg, virt_to_page(pl022->dummypage), in setup_dma_scatter()
912 bytesleft -= mapbytes; in setup_dma_scatter()
913 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
923 * configure_dma - configures the channels for the next transfer
929 .src_addr = SSP_DR(pl022->phybase), in configure_dma()
934 .dst_addr = SSP_DR(pl022->phybase), in configure_dma()
941 struct dma_chan *rxchan = pl022->dma_rx_channel; in configure_dma()
942 struct dma_chan *txchan = pl022->dma_tx_channel; in configure_dma()
946 /* Check that the channels are available */ in configure_dma()
948 return -ENODEV; in configure_dma()
952 * Notice that the DMA engine uses one-to-one mapping. Since we can in configure_dma()
956 switch (pl022->rx_lev_trig) { in configure_dma()
973 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
977 switch (pl022->tx_lev_trig) { in configure_dma()
994 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
998 switch (pl022->read) { in configure_dma()
1014 switch (pl022->write) { in configure_dma()
1041 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); in configure_dma()
1042 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); in configure_dma()
1044 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); in configure_dma()
1048 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); in configure_dma()
1053 setup_dma_scatter(pl022, pl022->rx, in configure_dma()
1054 pl022->cur_transfer->len, &pl022->sgt_rx); in configure_dma()
1055 setup_dma_scatter(pl022, pl022->tx, in configure_dma()
1056 pl022->cur_transfer->len, &pl022->sgt_tx); in configure_dma()
1059 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
1060 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
1064 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
1065 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
1071 pl022->sgt_rx.sgl, in configure_dma()
1079 pl022->sgt_tx.sgl, in configure_dma()
1087 rxdesc->callback = dma_callback; in configure_dma()
1088 rxdesc->callback_param = pl022; in configure_dma()
1095 pl022->dma_running = true; in configure_dma()
1103 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
1104 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
1106 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
1107 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
1109 sg_free_table(&pl022->sgt_tx); in configure_dma()
1111 sg_free_table(&pl022->sgt_rx); in configure_dma()
1113 return -ENOMEM; in configure_dma()
1124 * We need both RX and TX channels to do DMA, else do none in pl022_dma_probe()
1127 pl022->dma_rx_channel = dma_request_channel(mask, in pl022_dma_probe()
1128 pl022->master_info->dma_filter, in pl022_dma_probe()
1129 pl022->master_info->dma_rx_param); in pl022_dma_probe()
1130 if (!pl022->dma_rx_channel) { in pl022_dma_probe()
1131 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); in pl022_dma_probe()
1135 pl022->dma_tx_channel = dma_request_channel(mask, in pl022_dma_probe()
1136 pl022->master_info->dma_filter, in pl022_dma_probe()
1137 pl022->master_info->dma_tx_param); in pl022_dma_probe()
1138 if (!pl022->dma_tx_channel) { in pl022_dma_probe()
1139 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); in pl022_dma_probe()
1143 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_probe()
1144 if (!pl022->dummypage) in pl022_dma_probe()
1147 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", in pl022_dma_probe()
1148 dma_chan_name(pl022->dma_rx_channel), in pl022_dma_probe()
1149 dma_chan_name(pl022->dma_tx_channel)); in pl022_dma_probe()
1154 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_probe()
1156 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_probe()
1157 pl022->dma_rx_channel = NULL; in pl022_dma_probe()
1159 dev_err(&pl022->adev->dev, in pl022_dma_probe()
1161 return -ENODEV; in pl022_dma_probe()
1166 struct device *dev = &pl022->adev->dev; in pl022_dma_autoprobe()
1170 /* automatically configure DMA channels from platform, normally using DT */ in pl022_dma_autoprobe()
1177 pl022->dma_rx_channel = chan; in pl022_dma_autoprobe()
1185 pl022->dma_tx_channel = chan; in pl022_dma_autoprobe()
1187 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_autoprobe()
1188 if (!pl022->dummypage) { in pl022_dma_autoprobe()
1189 err = -ENOMEM; in pl022_dma_autoprobe()
1196 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_autoprobe()
1197 pl022->dma_tx_channel = NULL; in pl022_dma_autoprobe()
1199 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_autoprobe()
1200 pl022->dma_rx_channel = NULL; in pl022_dma_autoprobe()
1207 struct dma_chan *rxchan = pl022->dma_rx_channel; in terminate_dma()
1208 struct dma_chan *txchan = pl022->dma_tx_channel; in terminate_dma()
1213 pl022->dma_running = false; in terminate_dma()
1218 if (pl022->dma_running) in pl022_dma_remove()
1220 if (pl022->dma_tx_channel) in pl022_dma_remove()
1221 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_remove()
1222 if (pl022->dma_rx_channel) in pl022_dma_remove()
1223 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_remove()
1224 kfree(pl022->dummypage); in pl022_dma_remove()
1230 return -ENODEV; in configure_dma()
1249 * pl022_interrupt_handler - Interrupt handler for SSP controller
1262 struct spi_message *msg = pl022->cur_msg; in pl022_interrupt_handler()
1266 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1273 irq_status = readw(SSP_MIS(pl022->virtbase)); in pl022_interrupt_handler()
1285 * Overrun interrupt - bail out since our Data has been in pl022_interrupt_handler()
1288 dev_err(&pl022->adev->dev, "FIFO overrun\n"); in pl022_interrupt_handler()
1289 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) in pl022_interrupt_handler()
1290 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1299 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1300 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1301 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_interrupt_handler()
1302 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_interrupt_handler()
1303 msg->state = STATE_ERROR; in pl022_interrupt_handler()
1306 tasklet_schedule(&pl022->pump_transfers); in pl022_interrupt_handler()
1312 if (pl022->tx == pl022->tx_end) { in pl022_interrupt_handler()
1314 writew((readw(SSP_IMSC(pl022->virtbase)) & in pl022_interrupt_handler()
1316 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1324 if (pl022->rx >= pl022->rx_end) { in pl022_interrupt_handler()
1326 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1327 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1328 if (unlikely(pl022->rx > pl022->rx_end)) { in pl022_interrupt_handler()
1329 dev_warn(&pl022->adev->dev, "read %u surplus " in pl022_interrupt_handler()
1332 (u32) (pl022->rx - pl022->rx_end)); in pl022_interrupt_handler()
1335 msg->actual_length += pl022->cur_transfer->len; in pl022_interrupt_handler()
1336 if (pl022->cur_transfer->cs_change) in pl022_interrupt_handler()
1339 msg->state = next_transfer(pl022); in pl022_interrupt_handler()
1340 tasklet_schedule(&pl022->pump_transfers); in pl022_interrupt_handler()
1357 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; in set_up_next_transfer()
1359 dev_err(&pl022->adev->dev, in set_up_next_transfer()
1362 pl022->cur_transfer->len, in set_up_next_transfer()
1363 pl022->cur_chip->n_bytes); in set_up_next_transfer()
1364 dev_err(&pl022->adev->dev, "skipping this message\n"); in set_up_next_transfer()
1365 return -EIO; in set_up_next_transfer()
1367 pl022->tx = (void *)transfer->tx_buf; in set_up_next_transfer()
1368 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; in set_up_next_transfer()
1369 pl022->rx = (void *)transfer->rx_buf; in set_up_next_transfer()
1370 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; in set_up_next_transfer()
1371 pl022->write = in set_up_next_transfer()
1372 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; in set_up_next_transfer()
1373 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; in set_up_next_transfer()
1378 * pump_transfers - Tasklet function which schedules next transfer
1391 message = pl022->cur_msg; in pump_transfers()
1392 transfer = pl022->cur_transfer; in pump_transfers()
1395 if (message->state == STATE_ERROR) { in pump_transfers()
1396 message->status = -EIO; in pump_transfers()
1402 if (message->state == STATE_DONE) { in pump_transfers()
1403 message->status = 0; in pump_transfers()
1409 if (message->state == STATE_RUNNING) { in pump_transfers()
1410 previous = list_entry(transfer->transfer_list.prev, in pump_transfers()
1413 if (previous->delay_usecs) in pump_transfers()
1418 udelay(previous->delay_usecs); in pump_transfers()
1421 if (previous->cs_change) in pump_transfers()
1425 message->state = STATE_RUNNING; in pump_transfers()
1429 message->state = STATE_ERROR; in pump_transfers()
1430 message->status = -EIO; in pump_transfers()
1437 if (pl022->cur_chip->enable_dma) { in pump_transfers()
1439 dev_dbg(&pl022->adev->dev, in pump_transfers()
1448 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); in pump_transfers()
1454 * Default is to enable all interrupts except RX - in do_interrupt_dma_transfer()
1460 if (!pl022->next_msg_cs_active) in do_interrupt_dma_transfer()
1463 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { in do_interrupt_dma_transfer()
1465 pl022->cur_msg->state = STATE_ERROR; in do_interrupt_dma_transfer()
1466 pl022->cur_msg->status = -EIO; in do_interrupt_dma_transfer()
1471 if (pl022->cur_chip->enable_dma) { in do_interrupt_dma_transfer()
1474 dev_dbg(&pl022->adev->dev, in do_interrupt_dma_transfer()
1483 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_interrupt_dma_transfer()
1484 SSP_CR1(pl022->virtbase)); in do_interrupt_dma_transfer()
1485 writew(irqflags, SSP_IMSC(pl022->virtbase)); in do_interrupt_dma_transfer()
1496 chip = pl022->cur_chip; in do_polling_transfer()
1497 message = pl022->cur_msg; in do_polling_transfer()
1499 while (message->state != STATE_DONE) { in do_polling_transfer()
1501 if (message->state == STATE_ERROR) in do_polling_transfer()
1503 transfer = pl022->cur_transfer; in do_polling_transfer()
1506 if (message->state == STATE_RUNNING) { in do_polling_transfer()
1508 list_entry(transfer->transfer_list.prev, in do_polling_transfer()
1510 if (previous->delay_usecs) in do_polling_transfer()
1511 udelay(previous->delay_usecs); in do_polling_transfer()
1512 if (previous->cs_change) in do_polling_transfer()
1516 message->state = STATE_RUNNING; in do_polling_transfer()
1517 if (!pl022->next_msg_cs_active) in do_polling_transfer()
1524 message->state = STATE_ERROR; in do_polling_transfer()
1529 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_polling_transfer()
1530 SSP_CR1(pl022->virtbase)); in do_polling_transfer()
1532 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); in do_polling_transfer()
1535 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { in do_polling_transfer()
1539 dev_warn(&pl022->adev->dev, in do_polling_transfer()
1541 message->state = STATE_ERROR; in do_polling_transfer()
1548 message->actual_length += pl022->cur_transfer->len; in do_polling_transfer()
1549 if (pl022->cur_transfer->cs_change) in do_polling_transfer()
1552 message->state = next_transfer(pl022); in do_polling_transfer()
1556 if (message->state == STATE_DONE) in do_polling_transfer()
1557 message->status = 0; in do_polling_transfer()
1559 message->status = -EIO; in do_polling_transfer()
1571 pl022->cur_msg = msg; in pl022_transfer_one_message()
1572 msg->state = STATE_START; in pl022_transfer_one_message()
1574 pl022->cur_transfer = list_entry(msg->transfers.next, in pl022_transfer_one_message()
1578 pl022->cur_chip = spi_get_ctldata(msg->spi); in pl022_transfer_one_message()
1579 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; in pl022_transfer_one_message()
1584 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) in pl022_transfer_one_message()
1596 /* nothing more to do - disable spi/ssp and power off */ in pl022_unprepare_transfer_hardware()
1597 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_unprepare_transfer_hardware()
1598 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_unprepare_transfer_hardware()
1606 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) in verify_controller_parameters()
1607 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { in verify_controller_parameters()
1608 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1610 return -EINVAL; in verify_controller_parameters()
1612 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && in verify_controller_parameters()
1613 (!pl022->vendor->unidir)) { in verify_controller_parameters()
1614 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1617 return -EINVAL; in verify_controller_parameters()
1619 if ((chip_info->hierarchy != SSP_MASTER) in verify_controller_parameters()
1620 && (chip_info->hierarchy != SSP_SLAVE)) { in verify_controller_parameters()
1621 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1623 return -EINVAL; in verify_controller_parameters()
1625 if ((chip_info->com_mode != INTERRUPT_TRANSFER) in verify_controller_parameters()
1626 && (chip_info->com_mode != DMA_TRANSFER) in verify_controller_parameters()
1627 && (chip_info->com_mode != POLLING_TRANSFER)) { in verify_controller_parameters()
1628 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1630 return -EINVAL; in verify_controller_parameters()
1632 switch (chip_info->rx_lev_trig) { in verify_controller_parameters()
1639 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1640 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1642 return -EINVAL; in verify_controller_parameters()
1646 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1647 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1649 return -EINVAL; in verify_controller_parameters()
1653 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1655 return -EINVAL; in verify_controller_parameters()
1657 switch (chip_info->tx_lev_trig) { in verify_controller_parameters()
1664 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1665 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1667 return -EINVAL; in verify_controller_parameters()
1671 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1672 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1674 return -EINVAL; in verify_controller_parameters()
1678 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1680 return -EINVAL; in verify_controller_parameters()
1682 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { in verify_controller_parameters()
1683 if ((chip_info->ctrl_len < SSP_BITS_4) in verify_controller_parameters()
1684 || (chip_info->ctrl_len > SSP_BITS_32)) { in verify_controller_parameters()
1685 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1687 return -EINVAL; in verify_controller_parameters()
1689 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) in verify_controller_parameters()
1690 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { in verify_controller_parameters()
1691 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1693 return -EINVAL; in verify_controller_parameters()
1696 if (pl022->vendor->extended_cr) { in verify_controller_parameters()
1697 if ((chip_info->duplex != in verify_controller_parameters()
1699 && (chip_info->duplex != in verify_controller_parameters()
1701 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1703 return -EINVAL; in verify_controller_parameters()
1706 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) in verify_controller_parameters()
1707 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1711 return -EINVAL; in verify_controller_parameters()
1730 rate = clk_get_rate(pl022->clk); in calculate_effective_freq()
1737 dev_warn(&pl022->adev->dev, in calculate_effective_freq()
1738 "Max speed that can be programmed is %d Hz, you requested %d\n", in calculate_effective_freq()
1742 dev_err(&pl022->adev->dev, in calculate_effective_freq()
1745 return -EINVAL; in calculate_effective_freq()
1787 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); in calculate_effective_freq()
1788 clk_freq->scr = (u8) (best_scr & 0xFF); in calculate_effective_freq()
1789 dev_dbg(&pl022->adev->dev, in calculate_effective_freq()
1792 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", in calculate_effective_freq()
1793 clk_freq->cpsdvsr, clk_freq->scr); in calculate_effective_freq()
1816 * pl022_setup - setup function registered to SPI master framework
1834 struct pl022 *pl022 = spi_master_get_devdata(spi->master); in pl022_setup()
1835 unsigned int bits = spi->bits_per_word; in pl022_setup()
1837 struct device_node *np = spi->dev.of_node; in pl022_setup()
1839 if (!spi->max_speed_hz) in pl022_setup()
1840 return -EINVAL; in pl022_setup()
1848 return -ENOMEM; in pl022_setup()
1849 dev_dbg(&spi->dev, in pl022_setup()
1854 chip_info = spi->controller_data; in pl022_setup()
1863 of_property_read_u32(np, "pl022,com-mode", in pl022_setup()
1865 of_property_read_u32(np, "pl022,rx-level-trig", in pl022_setup()
1867 of_property_read_u32(np, "pl022,tx-level-trig", in pl022_setup()
1869 of_property_read_u32(np, "pl022,ctrl-len", in pl022_setup()
1871 of_property_read_u32(np, "pl022,wait-state", in pl022_setup()
1880 dev_dbg(&spi->dev, in pl022_setup()
1884 dev_dbg(&spi->dev, in pl022_setup()
1891 if ((0 == chip_info->clk_freq.cpsdvsr) in pl022_setup()
1892 && (0 == chip_info->clk_freq.scr)) { in pl022_setup()
1894 spi->max_speed_hz, in pl022_setup()
1899 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); in pl022_setup()
1902 clk_freq.cpsdvsr - 1; in pl022_setup()
1906 status = -EINVAL; in pl022_setup()
1907 dev_err(&spi->dev, in pl022_setup()
1914 dev_err(&spi->dev, "controller data is incorrect"); in pl022_setup()
1918 pl022->rx_lev_trig = chip_info->rx_lev_trig; in pl022_setup()
1919 pl022->tx_lev_trig = chip_info->tx_lev_trig; in pl022_setup()
1922 chip->xfer_type = chip_info->com_mode; in pl022_setup()
1923 if (!chip_info->cs_control) { in pl022_setup()
1924 chip->cs_control = null_cs_control; in pl022_setup()
1925 if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) in pl022_setup()
1926 dev_warn(&spi->dev, in pl022_setup()
1929 chip->cs_control = chip_info->cs_control; in pl022_setup()
1932 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { in pl022_setup()
1933 status = -ENOTSUPP; in pl022_setup()
1934 dev_err(&spi->dev, "illegal data size for this controller!\n"); in pl022_setup()
1935 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", in pl022_setup()
1936 pl022->vendor->max_bpw); in pl022_setup()
1939 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); in pl022_setup()
1940 chip->n_bytes = 1; in pl022_setup()
1941 chip->read = READING_U8; in pl022_setup()
1942 chip->write = WRITING_U8; in pl022_setup()
1944 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); in pl022_setup()
1945 chip->n_bytes = 2; in pl022_setup()
1946 chip->read = READING_U16; in pl022_setup()
1947 chip->write = WRITING_U16; in pl022_setup()
1949 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); in pl022_setup()
1950 chip->n_bytes = 4; in pl022_setup()
1951 chip->read = READING_U32; in pl022_setup()
1952 chip->write = WRITING_U32; in pl022_setup()
1956 chip->cr0 = 0; in pl022_setup()
1957 chip->cr1 = 0; in pl022_setup()
1958 chip->dmacr = 0; in pl022_setup()
1959 chip->cpsr = 0; in pl022_setup()
1960 if ((chip_info->com_mode == DMA_TRANSFER) in pl022_setup()
1961 && ((pl022->master_info)->enable_dma)) { in pl022_setup()
1962 chip->enable_dma = true; in pl022_setup()
1963 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); in pl022_setup()
1964 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1966 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1969 chip->enable_dma = false; in pl022_setup()
1970 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); in pl022_setup()
1971 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1973 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1977 chip->cpsr = clk_freq.cpsdvsr; in pl022_setup()
1980 if (pl022->vendor->extended_cr) { in pl022_setup()
1983 if (pl022->vendor->pl023) { in pl022_setup()
1985 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, in pl022_setup()
1989 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, in pl022_setup()
1991 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, in pl022_setup()
1993 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
1995 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, in pl022_setup()
1998 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2001 if (spi->mode & SPI_LSB_FIRST) { in pl022_setup()
2008 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); in pl022_setup()
2009 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); in pl022_setup()
2010 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, in pl022_setup()
2012 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, in pl022_setup()
2015 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2017 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
2022 if (spi->mode & SPI_CPOL) in pl022_setup()
2026 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); in pl022_setup()
2028 if (spi->mode & SPI_CPHA) in pl022_setup()
2032 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); in pl022_setup()
2034 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); in pl022_setup()
2036 if (pl022->vendor->loopback) { in pl022_setup()
2037 if (spi->mode & SPI_LOOP) in pl022_setup()
2041 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); in pl022_setup()
2043 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); in pl022_setup()
2044 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); in pl022_setup()
2045 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, in pl022_setup()
2058 * pl022_cleanup - cleanup function registered to SPI master framework
2075 struct device_node *np = dev->of_node; in pl022_platform_data_dt_get()
2088 pd->bus_id = -1; in pl022_platform_data_dt_get()
2089 pd->enable_dma = 1; in pl022_platform_data_dt_get()
2090 of_property_read_u32(np, "num-cs", &tmp); in pl022_platform_data_dt_get()
2091 pd->num_chipselect = tmp; in pl022_platform_data_dt_get()
2092 of_property_read_u32(np, "pl022,autosuspend-delay", in pl022_platform_data_dt_get()
2093 &pd->autosuspend_delay); in pl022_platform_data_dt_get()
2094 pd->rt = of_property_read_bool(np, "pl022,rt"); in pl022_platform_data_dt_get()
2101 struct device *dev = &adev->dev; in pl022_probe()
2103 dev_get_platdata(&adev->dev); in pl022_probe()
2106 struct device_node *np = adev->dev.of_node; in pl022_probe()
2109 dev_info(&adev->dev, in pl022_probe()
2110 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); in pl022_probe()
2116 return -ENODEV; in pl022_probe()
2119 if (platform_info->num_chipselect) { in pl022_probe()
2120 num_cs = platform_info->num_chipselect; in pl022_probe()
2123 return -ENODEV; in pl022_probe()
2129 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); in pl022_probe()
2130 return -ENOMEM; in pl022_probe()
2134 pl022->master = master; in pl022_probe()
2135 pl022->master_info = platform_info; in pl022_probe()
2136 pl022->adev = adev; in pl022_probe()
2137 pl022->vendor = id->data; in pl022_probe()
2138 pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int), in pl022_probe()
2140 if (!pl022->chipselects) { in pl022_probe()
2141 status = -ENOMEM; in pl022_probe()
2149 master->bus_num = platform_info->bus_id; in pl022_probe()
2150 master->num_chipselect = num_cs; in pl022_probe()
2151 master->cleanup = pl022_cleanup; in pl022_probe()
2152 master->setup = pl022_setup; in pl022_probe()
2153 master->auto_runtime_pm = true; in pl022_probe()
2154 master->transfer_one_message = pl022_transfer_one_message; in pl022_probe()
2155 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; in pl022_probe()
2156 master->rt = platform_info->rt; in pl022_probe()
2157 master->dev.of_node = dev->of_node; in pl022_probe()
2159 if (platform_info->num_chipselect && platform_info->chipselects) { in pl022_probe()
2161 pl022->chipselects[i] = platform_info->chipselects[i]; in pl022_probe()
2162 } else if (pl022->vendor->internal_cs_ctrl) { in pl022_probe()
2164 pl022->chipselects[i] = i; in pl022_probe()
2167 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); in pl022_probe()
2169 if (cs_gpio == -EPROBE_DEFER) { in pl022_probe()
2170 status = -EPROBE_DEFER; in pl022_probe()
2174 pl022->chipselects[i] = cs_gpio; in pl022_probe()
2177 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) in pl022_probe()
2178 dev_err(&adev->dev, in pl022_probe()
2182 dev_err(&adev->dev, in pl022_probe()
2190 * Supports mode 0-3, loopback, and active low CS. Transfers are in pl022_probe()
2193 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pl022_probe()
2194 if (pl022->vendor->extended_cr) in pl022_probe()
2195 master->mode_bits |= SPI_LSB_FIRST; in pl022_probe()
2197 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); in pl022_probe()
2203 pl022->phybase = adev->res.start; in pl022_probe()
2204 pl022->virtbase = devm_ioremap(dev, adev->res.start, in pl022_probe()
2205 resource_size(&adev->res)); in pl022_probe()
2206 if (pl022->virtbase == NULL) { in pl022_probe()
2207 status = -ENOMEM; in pl022_probe()
2210 dev_info(&adev->dev, "mapped registers from %pa to %p\n", in pl022_probe()
2211 &adev->res.start, pl022->virtbase); in pl022_probe()
2213 pl022->clk = devm_clk_get(&adev->dev, NULL); in pl022_probe()
2214 if (IS_ERR(pl022->clk)) { in pl022_probe()
2215 status = PTR_ERR(pl022->clk); in pl022_probe()
2216 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); in pl022_probe()
2220 status = clk_prepare_enable(pl022->clk); in pl022_probe()
2222 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); in pl022_probe()
2227 tasklet_init(&pl022->pump_transfers, pump_transfers, in pl022_probe()
2231 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), in pl022_probe()
2232 SSP_CR1(pl022->virtbase)); in pl022_probe()
2235 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, in pl022_probe()
2238 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); in pl022_probe()
2242 /* Get DMA channels, try autoconfiguration first */ in pl022_probe()
2244 if (status == -EPROBE_DEFER) { in pl022_probe()
2249 /* If that failed, use channels from platform_info */ in pl022_probe()
2251 platform_info->enable_dma = 1; in pl022_probe()
2252 else if (platform_info->enable_dma) { in pl022_probe()
2255 platform_info->enable_dma = 0; in pl022_probe()
2260 status = devm_spi_register_master(&adev->dev, master); in pl022_probe()
2262 dev_err(&adev->dev, in pl022_probe()
2263 "probe - problem registering spi master\n"); in pl022_probe()
2269 if (platform_info->autosuspend_delay > 0) { in pl022_probe()
2270 dev_info(&adev->dev, in pl022_probe()
2272 platform_info->autosuspend_delay); in pl022_probe()
2274 platform_info->autosuspend_delay); in pl022_probe()
2282 if (platform_info->enable_dma) in pl022_probe()
2285 clk_disable_unprepare(pl022->clk); in pl022_probe()
2309 pm_runtime_get_noresume(&adev->dev); in pl022_remove()
2312 if (pl022->master_info->enable_dma) in pl022_remove()
2315 clk_disable_unprepare(pl022->clk); in pl022_remove()
2317 tasklet_disable(&pl022->pump_transfers); in pl022_remove()
2327 ret = spi_master_suspend(pl022->master); in pl022_suspend()
2335 spi_master_resume(pl022->master); in pl022_suspend()
2355 ret = spi_master_resume(pl022->master); in pl022_resume()
2370 clk_disable_unprepare(pl022->clk); in pl022_runtime_suspend()
2381 clk_prepare_enable(pl022->clk); in pl022_runtime_resume()
2453 * ST-Ericsson derivative "PL023" (this is not
2479 .name = "ssp-pl022",