Lines Matching +full:spi +full:- +full:controller
2 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
25 #include <linux/spi/spi.h>
27 #include <linux/dma-mapping.h>
124 #define SPI_MAX_XFER (SZ_64K - 64)
149 int w_size; /* bytes per SPI word */
162 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
164 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
166 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
180 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
182 return controller->n_words * controller->w_size; in spi_qup_len()
185 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
187 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
192 static int spi_qup_set_state(struct spi_qup *controller, u32 state) in spi_qup_set_state() argument
198 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
203 return -EIO; in spi_qup_set_state()
207 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
210 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
217 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
218 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
222 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
226 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
231 return -EIO; in spi_qup_set_state()
237 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_read_from_fifo() argument
239 u8 *rx_buf = controller->rx_buf; in spi_qup_read_from_fifo()
243 for (; num_words; num_words--) { in spi_qup_read_from_fifo()
245 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_read_from_fifo()
247 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_read_from_fifo()
248 controller->rx_bytes, in spi_qup_read_from_fifo()
249 controller->w_size); in spi_qup_read_from_fifo()
252 controller->rx_bytes += num_bytes; in spi_qup_read_from_fifo()
256 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { in spi_qup_read_from_fifo()
258 * The data format depends on bytes per SPI word: in spi_qup_read_from_fifo()
264 shift *= (controller->w_size - i - 1); in spi_qup_read_from_fifo()
265 rx_buf[controller->rx_bytes] = word >> shift; in spi_qup_read_from_fifo()
270 static void spi_qup_read(struct spi_qup *controller, u32 *opflags) in spi_qup_read() argument
273 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_read()
275 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, in spi_qup_read()
276 controller->w_size); in spi_qup_read()
277 words_per_block = controller->in_blk_sz >> 2; in spi_qup_read()
282 controller->base + QUP_OPERATIONAL); in spi_qup_read()
288 if (!spi_qup_is_flag_set(controller, in spi_qup_read()
296 spi_qup_read_from_fifo(controller, num_words); in spi_qup_read()
298 remainder -= num_words; in spi_qup_read()
301 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_read()
313 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_read()
316 controller->base + QUP_OPERATIONAL); in spi_qup_read()
320 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_write_to_fifo() argument
322 const u8 *tx_buf = controller->tx_buf; in spi_qup_write_to_fifo()
326 for (; num_words; num_words--) { in spi_qup_write_to_fifo()
329 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_write_to_fifo()
330 controller->tx_bytes, in spi_qup_write_to_fifo()
331 controller->w_size); in spi_qup_write_to_fifo()
334 data = tx_buf[controller->tx_bytes + i]; in spi_qup_write_to_fifo()
335 word |= data << (BITS_PER_BYTE * (3 - i)); in spi_qup_write_to_fifo()
338 controller->tx_bytes += num_bytes; in spi_qup_write_to_fifo()
340 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_write_to_fifo()
348 complete(&qup->done); in spi_qup_dma_done()
351 static void spi_qup_write(struct spi_qup *controller) in spi_qup_write() argument
353 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_write()
356 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, in spi_qup_write()
357 controller->w_size); in spi_qup_write()
358 words_per_block = controller->out_blk_sz >> 2; in spi_qup_write()
363 controller->base + QUP_OPERATIONAL); in spi_qup_write()
369 if (spi_qup_is_flag_set(controller, in spi_qup_write()
376 spi_qup_write_to_fifo(controller, num_words); in spi_qup_write()
378 remainder -= num_words; in spi_qup_write()
381 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_write()
399 chan = master->dma_tx; in spi_qup_prep_sg()
401 chan = master->dma_rx; in spi_qup_prep_sg()
405 return desc ? PTR_ERR(desc) : -EINVAL; in spi_qup_prep_sg()
407 desc->callback = callback; in spi_qup_prep_sg()
408 desc->callback_param = qup; in spi_qup_prep_sg()
418 if (xfer->tx_buf) in spi_qup_dma_terminate()
419 dmaengine_terminate_all(master->dma_tx); in spi_qup_dma_terminate()
420 if (xfer->rx_buf) in spi_qup_dma_terminate()
421 dmaengine_terminate_all(master->dma_rx); in spi_qup_dma_terminate()
444 static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer, in spi_qup_do_dma() argument
448 struct spi_master *master = spi->master; in spi_qup_do_dma()
453 if (xfer->rx_buf) in spi_qup_do_dma()
455 else if (xfer->tx_buf) in spi_qup_do_dma()
458 rx_sgl = xfer->rx_sg.sgl; in spi_qup_do_dma()
459 tx_sgl = xfer->tx_sg.sgl; in spi_qup_do_dma()
465 qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl, in spi_qup_do_dma()
466 SPI_MAX_XFER, &rx_nents) / qup->w_size; in spi_qup_do_dma()
468 qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl, in spi_qup_do_dma()
469 SPI_MAX_XFER, &tx_nents) / qup->w_size; in spi_qup_do_dma()
470 if (!qup->n_words) in spi_qup_do_dma()
471 return -EIO; in spi_qup_do_dma()
473 ret = spi_qup_io_config(spi, xfer); in spi_qup_do_dma()
480 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_dma()
488 dma_async_issue_pending(master->dma_rx); in spi_qup_do_dma()
497 dma_async_issue_pending(master->dma_tx); in spi_qup_do_dma()
500 if (!wait_for_completion_timeout(&qup->done, timeout)) in spi_qup_do_dma()
501 return -ETIMEDOUT; in spi_qup_do_dma()
503 for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl)) in spi_qup_do_dma()
505 for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl)) in spi_qup_do_dma()
513 static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer, in spi_qup_do_pio() argument
516 struct spi_master *master = spi->master; in spi_qup_do_pio()
520 n_words = qup->n_words; in spi_qup_do_pio()
522 qup->rx_buf = xfer->rx_buf; in spi_qup_do_pio()
523 qup->tx_buf = xfer->tx_buf; in spi_qup_do_pio()
527 qup->n_words = SPI_MAX_XFER; in spi_qup_do_pio()
529 qup->n_words = n_words % SPI_MAX_XFER; in spi_qup_do_pio()
531 if (qup->tx_buf && offset) in spi_qup_do_pio()
532 qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER; in spi_qup_do_pio()
534 if (qup->rx_buf && offset) in spi_qup_do_pio()
535 qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER; in spi_qup_do_pio()
541 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32))) in spi_qup_do_pio()
542 qup->mode = QUP_IO_M_MODE_FIFO; in spi_qup_do_pio()
544 ret = spi_qup_io_config(spi, xfer); in spi_qup_do_pio()
550 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_pio()
556 dev_warn(qup->dev, "cannot set PAUSE state\n"); in spi_qup_do_pio()
560 if (qup->mode == QUP_IO_M_MODE_FIFO) in spi_qup_do_pio()
565 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_pio()
569 if (!wait_for_completion_timeout(&qup->done, timeout)) in spi_qup_do_pio()
570 return -ETIMEDOUT; in spi_qup_do_pio()
573 } while (iterations--); in spi_qup_do_pio()
580 struct spi_qup *controller = dev_id; in spi_qup_qup_irq() local
584 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
585 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
586 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
588 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
589 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
593 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); in spi_qup_qup_irq()
595 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
597 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
599 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); in spi_qup_qup_irq()
601 error = -EIO; in spi_qup_qup_irq()
606 dev_warn(controller->dev, "CLK_OVER_RUN\n"); in spi_qup_qup_irq()
608 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); in spi_qup_qup_irq()
610 error = -EIO; in spi_qup_qup_irq()
613 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
614 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
617 spi_qup_read(controller, &opflags); in spi_qup_qup_irq()
620 spi_qup_write(controller); in spi_qup_qup_irq()
624 complete(&controller->done); in spi_qup_qup_irq()
630 static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer) in spi_qup_io_prep() argument
632 struct spi_qup *controller = spi_master_get_devdata(spi->master); in spi_qup_io_prep() local
635 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { in spi_qup_io_prep()
636 dev_err(controller->dev, "too big size for loopback %d > %d\n", in spi_qup_io_prep()
637 xfer->len, controller->in_fifo_sz); in spi_qup_io_prep()
638 return -EIO; in spi_qup_io_prep()
641 ret = clk_set_rate(controller->cclk, xfer->speed_hz); in spi_qup_io_prep()
643 dev_err(controller->dev, "fail to set frequency %d", in spi_qup_io_prep()
644 xfer->speed_hz); in spi_qup_io_prep()
645 return -EIO; in spi_qup_io_prep()
648 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_io_prep()
649 controller->n_words = xfer->len / controller->w_size; in spi_qup_io_prep()
651 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) in spi_qup_io_prep()
652 controller->mode = QUP_IO_M_MODE_FIFO; in spi_qup_io_prep()
653 else if (spi->master->can_dma && in spi_qup_io_prep()
654 spi->master->can_dma(spi->master, spi, xfer) && in spi_qup_io_prep()
655 spi->master->cur_msg_mapped) in spi_qup_io_prep()
656 controller->mode = QUP_IO_M_MODE_BAM; in spi_qup_io_prep()
658 controller->mode = QUP_IO_M_MODE_BLOCK; in spi_qup_io_prep()
663 /* prep qup for another spi transaction of specific type */
664 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) in spi_qup_io_config() argument
666 struct spi_qup *controller = spi_master_get_devdata(spi->master); in spi_qup_io_config() local
670 spin_lock_irqsave(&controller->lock, flags); in spi_qup_io_config()
671 controller->xfer = xfer; in spi_qup_io_config()
672 controller->error = 0; in spi_qup_io_config()
673 controller->rx_bytes = 0; in spi_qup_io_config()
674 controller->tx_bytes = 0; in spi_qup_io_config()
675 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_io_config()
678 if (spi_qup_set_state(controller, QUP_STATE_RESET)) { in spi_qup_io_config()
679 dev_err(controller->dev, "cannot set RESET state\n"); in spi_qup_io_config()
680 return -EIO; in spi_qup_io_config()
683 switch (controller->mode) { in spi_qup_io_config()
685 writel_relaxed(controller->n_words, in spi_qup_io_config()
686 controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
687 writel_relaxed(controller->n_words, in spi_qup_io_config()
688 controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
690 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
691 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
694 writel_relaxed(controller->n_words, in spi_qup_io_config()
695 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
696 writel_relaxed(controller->n_words, in spi_qup_io_config()
697 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
699 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
700 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
702 if (!controller->qup_v1) { in spi_qup_io_config()
705 input_cnt = controller->base + QUP_MX_INPUT_CNT; in spi_qup_io_config()
709 * That case is a non-balanced transfer when there is in spi_qup_io_config()
712 if (xfer->tx_buf) in spi_qup_io_config()
715 writel_relaxed(controller->n_words, input_cnt); in spi_qup_io_config()
717 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
721 reinit_completion(&controller->done); in spi_qup_io_config()
722 writel_relaxed(controller->n_words, in spi_qup_io_config()
723 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
724 writel_relaxed(controller->n_words, in spi_qup_io_config()
725 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
727 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
728 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
731 dev_err(controller->dev, "unknown mode = %d\n", in spi_qup_io_config()
732 controller->mode); in spi_qup_io_config()
733 return -EIO; in spi_qup_io_config()
736 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
740 if (!spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
745 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
746 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
748 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
750 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
752 if (spi->mode & SPI_CPOL) in spi_qup_io_config()
757 writel_relaxed(control, controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
759 config = readl_relaxed(controller->base + SPI_CONFIG); in spi_qup_io_config()
761 if (spi->mode & SPI_LOOP) in spi_qup_io_config()
766 if (spi->mode & SPI_CPHA) in spi_qup_io_config()
772 * HS_MODE improves signal stability for spi-clk high rates, in spi_qup_io_config()
775 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP)) in spi_qup_io_config()
780 writel_relaxed(config, controller->base + SPI_CONFIG); in spi_qup_io_config()
782 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_io_config()
784 config |= xfer->bits_per_word - 1; in spi_qup_io_config()
787 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_io_config()
788 if (!xfer->tx_buf) in spi_qup_io_config()
790 if (!xfer->rx_buf) in spi_qup_io_config()
794 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_io_config()
797 if (!controller->qup_v1) { in spi_qup_io_config()
805 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
808 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); in spi_qup_io_config()
815 struct spi_device *spi, in spi_qup_transfer_one() argument
818 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_transfer_one() local
820 int ret = -EIO; in spi_qup_transfer_one()
822 ret = spi_qup_io_prep(spi, xfer); in spi_qup_transfer_one()
826 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); in spi_qup_transfer_one()
828 xfer->len) * 8, timeout); in spi_qup_transfer_one()
831 reinit_completion(&controller->done); in spi_qup_transfer_one()
833 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
834 controller->xfer = xfer; in spi_qup_transfer_one()
835 controller->error = 0; in spi_qup_transfer_one()
836 controller->rx_bytes = 0; in spi_qup_transfer_one()
837 controller->tx_bytes = 0; in spi_qup_transfer_one()
838 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
840 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
841 ret = spi_qup_do_dma(spi, xfer, timeout); in spi_qup_transfer_one()
843 ret = spi_qup_do_pio(spi, xfer, timeout); in spi_qup_transfer_one()
849 spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_transfer_one()
850 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
852 ret = controller->error; in spi_qup_transfer_one()
853 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
855 if (ret && spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
861 static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi, in spi_qup_can_dma() argument
868 if (xfer->rx_buf) { in spi_qup_can_dma()
869 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) || in spi_qup_can_dma()
870 IS_ERR_OR_NULL(master->dma_rx)) in spi_qup_can_dma()
872 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz)) in spi_qup_can_dma()
876 if (xfer->tx_buf) { in spi_qup_can_dma()
877 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) || in spi_qup_can_dma()
878 IS_ERR_OR_NULL(master->dma_tx)) in spi_qup_can_dma()
880 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz)) in spi_qup_can_dma()
884 n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_can_dma()
885 if (n_words <= (qup->in_fifo_sz / sizeof(u32))) in spi_qup_can_dma()
893 if (!IS_ERR_OR_NULL(master->dma_rx)) in spi_qup_release_dma()
894 dma_release_channel(master->dma_rx); in spi_qup_release_dma()
895 if (!IS_ERR_OR_NULL(master->dma_tx)) in spi_qup_release_dma()
896 dma_release_channel(master->dma_tx); in spi_qup_release_dma()
901 struct spi_qup *spi = spi_master_get_devdata(master); in spi_qup_init_dma() local
902 struct dma_slave_config *rx_conf = &spi->rx_conf, in spi_qup_init_dma()
903 *tx_conf = &spi->tx_conf; in spi_qup_init_dma()
904 struct device *dev = spi->dev; in spi_qup_init_dma()
908 master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); in spi_qup_init_dma()
909 if (IS_ERR(master->dma_rx)) in spi_qup_init_dma()
910 return PTR_ERR(master->dma_rx); in spi_qup_init_dma()
912 master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); in spi_qup_init_dma()
913 if (IS_ERR(master->dma_tx)) { in spi_qup_init_dma()
914 ret = PTR_ERR(master->dma_tx); in spi_qup_init_dma()
919 rx_conf->direction = DMA_DEV_TO_MEM; in spi_qup_init_dma()
920 rx_conf->device_fc = 1; in spi_qup_init_dma()
921 rx_conf->src_addr = base + QUP_INPUT_FIFO; in spi_qup_init_dma()
922 rx_conf->src_maxburst = spi->in_blk_sz; in spi_qup_init_dma()
924 tx_conf->direction = DMA_MEM_TO_DEV; in spi_qup_init_dma()
925 tx_conf->device_fc = 1; in spi_qup_init_dma()
926 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO; in spi_qup_init_dma()
927 tx_conf->dst_maxburst = spi->out_blk_sz; in spi_qup_init_dma()
929 ret = dmaengine_slave_config(master->dma_rx, rx_conf); in spi_qup_init_dma()
935 ret = dmaengine_slave_config(master->dma_tx, tx_conf); in spi_qup_init_dma()
944 dma_release_channel(master->dma_tx); in spi_qup_init_dma()
946 dma_release_channel(master->dma_rx); in spi_qup_init_dma()
950 static void spi_qup_set_cs(struct spi_device *spi, bool val) in spi_qup_set_cs() argument
952 struct spi_qup *controller; in spi_qup_set_cs() local
956 controller = spi_master_get_devdata(spi->master); in spi_qup_set_cs()
957 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
965 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
972 struct spi_qup *controller; in spi_qup_probe() local
979 dev = &pdev->dev; in spi_qup_probe()
998 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) in spi_qup_probe()
1003 return -ENXIO; in spi_qup_probe()
1024 return -ENOMEM; in spi_qup_probe()
1027 /* use num-cs unless not present or out of range */ in spi_qup_probe()
1028 if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) || in spi_qup_probe()
1030 master->num_chipselect = SPI_NUM_CHIPSELECTS; in spi_qup_probe()
1032 master->num_chipselect = num_cs; in spi_qup_probe()
1034 master->bus_num = pdev->id; in spi_qup_probe()
1035 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in spi_qup_probe()
1036 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_qup_probe()
1037 master->max_speed_hz = max_freq; in spi_qup_probe()
1038 master->transfer_one = spi_qup_transfer_one; in spi_qup_probe()
1039 master->dev.of_node = pdev->dev.of_node; in spi_qup_probe()
1040 master->auto_runtime_pm = true; in spi_qup_probe()
1041 master->dma_alignment = dma_get_cache_alignment(); in spi_qup_probe()
1042 master->max_dma_len = SPI_MAX_XFER; in spi_qup_probe()
1046 controller = spi_master_get_devdata(master); in spi_qup_probe()
1048 controller->dev = dev; in spi_qup_probe()
1049 controller->base = base; in spi_qup_probe()
1050 controller->iclk = iclk; in spi_qup_probe()
1051 controller->cclk = cclk; in spi_qup_probe()
1052 controller->irq = irq; in spi_qup_probe()
1054 ret = spi_qup_init_dma(master, res->start); in spi_qup_probe()
1055 if (ret == -EPROBE_DEFER) in spi_qup_probe()
1058 master->can_dma = spi_qup_can_dma; in spi_qup_probe()
1060 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); in spi_qup_probe()
1062 if (!controller->qup_v1) in spi_qup_probe()
1063 master->set_cs = spi_qup_set_cs; in spi_qup_probe()
1065 spin_lock_init(&controller->lock); in spi_qup_probe()
1066 init_completion(&controller->done); in spi_qup_probe()
1072 controller->out_blk_sz = size * 16; in spi_qup_probe()
1074 controller->out_blk_sz = 4; in spi_qup_probe()
1078 controller->in_blk_sz = size * 16; in spi_qup_probe()
1080 controller->in_blk_sz = 4; in spi_qup_probe()
1083 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); in spi_qup_probe()
1086 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); in spi_qup_probe()
1089 controller->in_blk_sz, controller->in_fifo_sz, in spi_qup_probe()
1090 controller->out_blk_sz, controller->out_fifo_sz); in spi_qup_probe()
1094 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_probe()
1103 if (!controller->qup_v1) in spi_qup_probe()
1110 if (controller->qup_v1) in spi_qup_probe()
1119 IRQF_TRIGGER_HIGH, pdev->name, controller); in spi_qup_probe()
1135 pm_runtime_disable(&pdev->dev); in spi_qup_probe()
1149 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_pm_suspend_runtime() local
1153 config = readl(controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1155 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1157 clk_disable_unprepare(controller->cclk); in spi_qup_pm_suspend_runtime()
1158 clk_disable_unprepare(controller->iclk); in spi_qup_pm_suspend_runtime()
1166 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_pm_resume_runtime() local
1170 ret = clk_prepare_enable(controller->iclk); in spi_qup_pm_resume_runtime()
1174 ret = clk_prepare_enable(controller->cclk); in spi_qup_pm_resume_runtime()
1179 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1181 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1190 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_suspend() local
1202 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_suspend()
1206 clk_disable_unprepare(controller->cclk); in spi_qup_suspend()
1207 clk_disable_unprepare(controller->iclk); in spi_qup_suspend()
1214 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_resume() local
1217 ret = clk_prepare_enable(controller->iclk); in spi_qup_resume()
1221 ret = clk_prepare_enable(controller->cclk); in spi_qup_resume()
1225 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_resume()
1235 struct spi_master *master = dev_get_drvdata(&pdev->dev); in spi_qup_remove()
1236 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_remove() local
1239 ret = pm_runtime_get_sync(&pdev->dev); in spi_qup_remove()
1243 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_remove()
1249 clk_disable_unprepare(controller->cclk); in spi_qup_remove()
1250 clk_disable_unprepare(controller->iclk); in spi_qup_remove()
1252 pm_runtime_put_noidle(&pdev->dev); in spi_qup_remove()
1253 pm_runtime_disable(&pdev->dev); in spi_qup_remove()
1259 { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
1260 { .compatible = "qcom,spi-qup-v2.1.1", },
1261 { .compatible = "qcom,spi-qup-v2.2.1", },