Lines Matching +full:enable +full:- +full:ssc
2 * Copyright (c) 2008-2014 STMicroelectronics Limited
28 /* SSC registers */
36 /* SSC Control */
51 /* SSC Interrupt Enable */
57 /* SSC SPI Controller */
62 /* SSC SPI current transaction */
77 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
80 count = spi_st->words_remaining; in ssc_write_tx_fifo()
83 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
84 if (spi_st->bytes_per_word == 1) { in ssc_write_tx_fifo()
85 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
87 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
88 word = *spi_st->tx_ptr++ | (word << 8); in ssc_write_tx_fifo()
91 writel_relaxed(word, spi_st->base + SSC_TBUF); in ssc_write_tx_fifo()
101 if (spi_st->words_remaining > FIFO_SIZE) in ssc_read_rx_fifo()
104 count = spi_st->words_remaining; in ssc_read_rx_fifo()
107 word = readl_relaxed(spi_st->base + SSC_RBUF); in ssc_read_rx_fifo()
109 if (spi_st->rx_ptr) { in ssc_read_rx_fifo()
110 if (spi_st->bytes_per_word == 1) { in ssc_read_rx_fifo()
111 *spi_st->rx_ptr++ = (uint8_t)word; in ssc_read_rx_fifo()
113 *spi_st->rx_ptr++ = (word >> 8); in ssc_read_rx_fifo()
114 *spi_st->rx_ptr++ = word & 0xff; in ssc_read_rx_fifo()
118 spi_st->words_remaining -= count; in ssc_read_rx_fifo()
128 spi_st->tx_ptr = t->tx_buf; in spi_st_transfer_one()
129 spi_st->rx_ptr = t->rx_buf; in spi_st_transfer_one()
131 if (spi->bits_per_word > 8) { in spi_st_transfer_one()
133 * Anything greater than 8 bits-per-word requires 2 in spi_st_transfer_one()
134 * bytes-per-word in the RX/TX buffers in spi_st_transfer_one()
136 spi_st->bytes_per_word = 2; in spi_st_transfer_one()
137 spi_st->words_remaining = t->len / 2; in spi_st_transfer_one()
139 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) { in spi_st_transfer_one()
141 * If transfer is even-length, and 8 bits-per-word, then in spi_st_transfer_one()
142 * implement as half-length 16 bits-per-word transfer in spi_st_transfer_one()
144 spi_st->bytes_per_word = 2; in spi_st_transfer_one()
145 spi_st->words_remaining = t->len / 2; in spi_st_transfer_one()
147 /* Set SSC_CTL to 16 bits-per-word */ in spi_st_transfer_one()
148 ctl = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_transfer_one()
149 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL); in spi_st_transfer_one()
151 readl_relaxed(spi_st->base + SSC_RBUF); in spi_st_transfer_one()
154 spi_st->bytes_per_word = 1; in spi_st_transfer_one()
155 spi_st->words_remaining = t->len; in spi_st_transfer_one()
158 reinit_completion(&spi_st->done); in spi_st_transfer_one()
162 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN); in spi_st_transfer_one()
165 wait_for_completion(&spi_st->done); in spi_st_transfer_one()
169 writel_relaxed(ctl, spi_st->base + SSC_CTL); in spi_st_transfer_one()
171 spi_finalize_current_transfer(spi->master); in spi_st_transfer_one()
173 return t->len; in spi_st_transfer_one()
178 gpio_free(spi->cs_gpio); in spi_st_cleanup()
181 /* the spi->mode bits understood by this driver: */
185 struct spi_st *spi_st = spi_master_get_devdata(spi->master); in spi_st_setup()
187 u32 hz = spi->max_speed_hz; in spi_st_setup()
188 int cs = spi->cs_gpio; in spi_st_setup()
192 dev_err(&spi->dev, "max_speed_hz unspecified\n"); in spi_st_setup()
193 return -EINVAL; in spi_st_setup()
197 dev_err(&spi->dev, "%d is not a valid gpio\n", cs); in spi_st_setup()
198 return -EINVAL; in spi_st_setup()
201 ret = gpio_request(cs, dev_name(&spi->dev)); in spi_st_setup()
203 dev_err(&spi->dev, "could not request gpio:%d\n", cs); in spi_st_setup()
207 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); in spi_st_setup()
211 spi_st_clk = clk_get_rate(spi_st->clk); in spi_st_setup()
216 dev_err(&spi->dev, in spi_st_setup()
218 ret = -EINVAL; in spi_st_setup()
222 spi_st->baud = spi_st_clk / (2 * sscbrg); in spi_st_setup()
223 if (sscbrg == BIT(16)) /* 16-bit counter wraps */ in spi_st_setup()
226 writel_relaxed(sscbrg, spi_st->base + SSC_BRG); in spi_st_setup()
228 dev_dbg(&spi->dev, in spi_st_setup()
230 hz, spi_st->baud, sscbrg); in spi_st_setup()
232 /* Set SSC_CTL and enable SSC */ in spi_st_setup()
233 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_setup()
236 if (spi->mode & SPI_CPOL) in spi_st_setup()
241 if (spi->mode & SPI_CPHA) in spi_st_setup()
246 if ((spi->mode & SPI_LSB_FIRST) == 0) in spi_st_setup()
251 if (spi->mode & SPI_LOOP) in spi_st_setup()
257 var |= (spi->bits_per_word - 1); in spi_st_setup()
262 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_setup()
265 readl_relaxed(spi_st->base + SSC_RBUF); in spi_st_setup()
283 if (spi_st->words_remaining) { in spi_st_irq()
287 writel_relaxed(0x0, spi_st->base + SSC_IEN); in spi_st_irq()
290 * before re-enabling interrupt in spi_st_irq()
292 readl(spi_st->base + SSC_IEN); in spi_st_irq()
293 complete(&spi_st->done); in spi_st_irq()
301 struct device_node *np = pdev->dev.of_node; in spi_st_probe()
308 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st)); in spi_st_probe()
310 return -ENOMEM; in spi_st_probe()
312 master->dev.of_node = np; in spi_st_probe()
313 master->mode_bits = MODEBITS; in spi_st_probe()
314 master->setup = spi_st_setup; in spi_st_probe()
315 master->cleanup = spi_st_cleanup; in spi_st_probe()
316 master->transfer_one = spi_st_transfer_one; in spi_st_probe()
317 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); in spi_st_probe()
318 master->auto_runtime_pm = true; in spi_st_probe()
319 master->bus_num = pdev->id; in spi_st_probe()
322 spi_st->clk = devm_clk_get(&pdev->dev, "ssc"); in spi_st_probe()
323 if (IS_ERR(spi_st->clk)) { in spi_st_probe()
324 dev_err(&pdev->dev, "Unable to request clock\n"); in spi_st_probe()
325 ret = PTR_ERR(spi_st->clk); in spi_st_probe()
329 ret = clk_prepare_enable(spi_st->clk); in spi_st_probe()
333 init_completion(&spi_st->done); in spi_st_probe()
337 spi_st->base = devm_ioremap_resource(&pdev->dev, res); in spi_st_probe()
338 if (IS_ERR(spi_st->base)) { in spi_st_probe()
339 ret = PTR_ERR(spi_st->base); in spi_st_probe()
343 /* Disable I2C and Reset SSC */ in spi_st_probe()
344 writel_relaxed(0x0, spi_st->base + SSC_I2C); in spi_st_probe()
345 var = readw_relaxed(spi_st->base + SSC_CTL); in spi_st_probe()
347 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_probe()
350 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_probe()
352 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_probe()
354 /* Set SSC into slave mode before reconfiguring PIO pins */ in spi_st_probe()
355 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_probe()
357 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_probe()
361 dev_err(&pdev->dev, "IRQ missing or invalid\n"); in spi_st_probe()
362 ret = -EINVAL; in spi_st_probe()
366 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0, in spi_st_probe()
367 pdev->name, spi_st); in spi_st_probe()
369 dev_err(&pdev->dev, "Failed to request irq %d\n", irq); in spi_st_probe()
374 pm_runtime_set_active(&pdev->dev); in spi_st_probe()
375 pm_runtime_enable(&pdev->dev); in spi_st_probe()
379 ret = devm_spi_register_master(&pdev->dev, master); in spi_st_probe()
381 dev_err(&pdev->dev, "Failed to register master\n"); in spi_st_probe()
388 pm_runtime_disable(&pdev->dev); in spi_st_probe()
389 clk_disable_unprepare(spi_st->clk); in spi_st_probe()
400 pm_runtime_disable(&pdev->dev); in spi_st_remove()
402 clk_disable_unprepare(spi_st->clk); in spi_st_remove()
404 pinctrl_pm_select_sleep_state(&pdev->dev); in spi_st_remove()
415 writel_relaxed(0, spi_st->base + SSC_IEN); in spi_st_runtime_suspend()
418 clk_disable_unprepare(spi_st->clk); in spi_st_runtime_suspend()
429 ret = clk_prepare_enable(spi_st->clk); in spi_st_runtime_resume()
468 { .compatible = "st,comms-ssc4-spi", },
475 .name = "spi-st",
485 MODULE_DESCRIPTION("STM SSC SPI driver");