Lines Matching full:spi
2 * STMicroelectronics STM32 SPI Controller driver (master mode only)
32 #include <linux/spi/spi.h>
36 /* STM32 SPI registers */
113 /* SPI Master Baud Rate min/max divisor */
117 /* SPI Communication mode */
126 * struct stm32_spi - private data of the SPI controller
130 * @clk: hw kernel clock feeding the SPI clock generator
131 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
132 * @rst: SPI controller reset line
134 * @irq: SPI controller interrupt line
138 * @cur_bpw: number of bits in a single SPI data frame
140 * @cur_comm: SPI communication mode
149 * @phys_addr: SPI registers physical base address
179 static inline void stm32_spi_set_bits(struct stm32_spi *spi, in stm32_spi_set_bits() argument
182 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
183 spi->base + offset); in stm32_spi_set_bits()
186 static inline void stm32_spi_clr_bits(struct stm32_spi *spi, in stm32_spi_clr_bits() argument
189 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
190 spi->base + offset); in stm32_spi_clr_bits()
195 * @spi: pointer to the spi controller data structure
197 static int stm32_spi_get_fifo_size(struct stm32_spi *spi) in stm32_spi_get_fifo_size() argument
202 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_get_fifo_size()
204 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); in stm32_spi_get_fifo_size()
206 while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP) in stm32_spi_get_fifo_size()
207 writeb_relaxed(++count, spi->base + STM32_SPI_TXDR); in stm32_spi_get_fifo_size()
209 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); in stm32_spi_get_fifo_size()
211 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_get_fifo_size()
213 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32_spi_get_fifo_size()
220 * @spi: pointer to the spi controller data structure
222 static int stm32_spi_get_bpw_mask(struct stm32_spi *spi) in stm32_spi_get_bpw_mask() argument
227 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_get_bpw_mask()
233 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE); in stm32_spi_get_bpw_mask()
235 cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1); in stm32_spi_get_bpw_mask()
239 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_get_bpw_mask()
241 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32_spi_get_bpw_mask()
248 * @spi: pointer to the spi controller data structure
253 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz) in stm32_spi_prepare_mbr() argument
257 /* Ensure spi->clk_rate is even */ in stm32_spi_prepare_mbr()
258 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
261 * SPI framework set xfer->speed_hz to master->max_speed_hz if in stm32_spi_prepare_mbr()
277 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
284 * @spi: pointer to the spi controller data structure
286 static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi) in stm32_spi_prepare_fthlv() argument
291 half_fifo = (spi->fifo_size / 2); in stm32_spi_prepare_fthlv()
293 if (spi->cur_bpw <= 8) in stm32_spi_prepare_fthlv()
295 else if (spi->cur_bpw <= 16) in stm32_spi_prepare_fthlv()
301 if (spi->cur_bpw > 8) in stm32_spi_prepare_fthlv()
311 * @spi: pointer to the spi controller data structure
316 static void stm32_spi_write_txfifo(struct stm32_spi *spi) in stm32_spi_write_txfifo() argument
318 while ((spi->tx_len > 0) && in stm32_spi_write_txfifo()
319 (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) { in stm32_spi_write_txfifo()
320 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32_spi_write_txfifo()
322 if (spi->tx_len >= sizeof(u32)) { in stm32_spi_write_txfifo()
323 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32_spi_write_txfifo()
325 writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR); in stm32_spi_write_txfifo()
326 spi->tx_len -= sizeof(u32); in stm32_spi_write_txfifo()
327 } else if (spi->tx_len >= sizeof(u16)) { in stm32_spi_write_txfifo()
328 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32_spi_write_txfifo()
330 writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR); in stm32_spi_write_txfifo()
331 spi->tx_len -= sizeof(u16); in stm32_spi_write_txfifo()
333 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32_spi_write_txfifo()
335 writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR); in stm32_spi_write_txfifo()
336 spi->tx_len -= sizeof(u8); in stm32_spi_write_txfifo()
340 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32_spi_write_txfifo()
345 * @spi: pointer to the spi controller data structure
350 static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush) in stm32_spi_read_rxfifo() argument
352 u32 sr = readl_relaxed(spi->base + STM32_SPI_SR); in stm32_spi_read_rxfifo()
355 while ((spi->rx_len > 0) && in stm32_spi_read_rxfifo()
358 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32_spi_read_rxfifo()
360 if ((spi->rx_len >= sizeof(u32)) || in stm32_spi_read_rxfifo()
362 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32_spi_read_rxfifo()
364 *rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR); in stm32_spi_read_rxfifo()
365 spi->rx_len -= sizeof(u32); in stm32_spi_read_rxfifo()
366 } else if ((spi->rx_len >= sizeof(u16)) || in stm32_spi_read_rxfifo()
367 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32_spi_read_rxfifo()
368 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32_spi_read_rxfifo()
370 *rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR); in stm32_spi_read_rxfifo()
371 spi->rx_len -= sizeof(u16); in stm32_spi_read_rxfifo()
373 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32_spi_read_rxfifo()
375 *rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR); in stm32_spi_read_rxfifo()
376 spi->rx_len -= sizeof(u8); in stm32_spi_read_rxfifo()
379 sr = readl_relaxed(spi->base + STM32_SPI_SR); in stm32_spi_read_rxfifo()
383 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, in stm32_spi_read_rxfifo()
384 flush ? "(flush)" : "", spi->rx_len); in stm32_spi_read_rxfifo()
388 * stm32_spi_enable - Enable SPI controller
389 * @spi: pointer to the spi controller data structure
391 * SPI data transfer is enabled but spi_ker_ck is idle.
394 static void stm32_spi_enable(struct stm32_spi *spi) in stm32_spi_enable() argument
396 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
398 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); in stm32_spi_enable()
402 * stm32_spi_disable - Disable SPI controller
403 * @spi: pointer to the spi controller data structure
405 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
409 static void stm32_spi_disable(struct stm32_spi *spi) in stm32_spi_disable() argument
414 dev_dbg(spi->dev, "disable controller\n"); in stm32_spi_disable()
416 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_disable()
418 cr1 = readl_relaxed(spi->base + STM32_SPI_CR1); in stm32_spi_disable()
421 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_disable()
426 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR, in stm32_spi_disable()
431 spi->base + STM32_SPI_CR1); in stm32_spi_disable()
433 spi->base + STM32_SPI_SR, in stm32_spi_disable()
436 dev_warn(spi->dev, in stm32_spi_disable()
441 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) in stm32_spi_disable()
442 stm32_spi_read_rxfifo(spi, true); in stm32_spi_disable()
444 if (spi->cur_usedma && spi->tx_buf) in stm32_spi_disable()
445 dmaengine_terminate_all(spi->dma_tx); in stm32_spi_disable()
446 if (spi->cur_usedma && spi->rx_buf) in stm32_spi_disable()
447 dmaengine_terminate_all(spi->dma_rx); in stm32_spi_disable()
449 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); in stm32_spi_disable()
451 stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN | in stm32_spi_disable()
455 writel_relaxed(0, spi->base + STM32_SPI_IER); in stm32_spi_disable()
456 writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR); in stm32_spi_disable()
458 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_disable()
470 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_can_dma() local
472 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
473 (transfer->len > spi->fifo_size) ? "true" : "false"); in stm32_spi_can_dma()
475 return (transfer->len > spi->fifo_size); in stm32_spi_can_dma()
479 * stm32_spi_irq - Interrupt handler for SPI controller events
481 * @dev_id: SPI controller master interface
486 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_irq() local
491 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_irq()
493 sr = readl_relaxed(spi->base + STM32_SPI_SR); in stm32_spi_irq()
494 ier = readl_relaxed(spi->base + STM32_SPI_IER); in stm32_spi_irq()
502 * data, before disabling SPI. in stm32_spi_irq()
504 if (spi->rx_buf && !spi->cur_usedma) in stm32_spi_irq()
508 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32_spi_irq()
510 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_irq()
515 dev_warn(spi->dev, "Communication suspended\n"); in stm32_spi_irq()
516 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32_spi_irq()
517 stm32_spi_read_rxfifo(spi, false); in stm32_spi_irq()
522 if (spi->cur_usedma) in stm32_spi_irq()
527 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32_spi_irq()
532 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32_spi_irq()
533 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32_spi_irq()
534 stm32_spi_read_rxfifo(spi, false); in stm32_spi_irq()
539 if (spi->cur_usedma) in stm32_spi_irq()
544 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32_spi_irq()
545 stm32_spi_read_rxfifo(spi, true); in stm32_spi_irq()
550 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32_spi_irq()
551 stm32_spi_write_txfifo(spi); in stm32_spi_irq()
554 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32_spi_irq()
555 stm32_spi_read_rxfifo(spi, false); in stm32_spi_irq()
557 writel_relaxed(mask, spi->base + STM32_SPI_IFCR); in stm32_spi_irq()
559 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_irq()
563 stm32_spi_disable(spi); in stm32_spi_irq()
598 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_prepare_msg() local
599 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
604 /* SPI slave device may need time between data frames */ in stm32_spi_prepare_msg()
605 spi->cur_midi = 0; in stm32_spi_prepare_msg()
606 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
607 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
624 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
630 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
634 (readl_relaxed(spi->base + STM32_SPI_CFG2) & in stm32_spi_prepare_msg()
636 spi->base + STM32_SPI_CFG2); in stm32_spi_prepare_msg()
638 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
651 struct stm32_spi *spi = data; in stm32_spi_dma_cb() local
655 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_dma_cb()
657 sr = readl_relaxed(spi->base + STM32_SPI_SR); in stm32_spi_dma_cb()
659 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_dma_cb()
662 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); in stm32_spi_dma_cb()
671 static void stm32_spi_dma_config(struct stm32_spi *spi, in stm32_spi_dma_config() argument
678 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
680 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
686 if (spi->cur_fthlv == 2) in stm32_spi_dma_config()
689 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
694 dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR; in stm32_spi_dma_config()
698 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
701 dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR; in stm32_spi_dma_config()
705 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
717 static int stm32_spi_transfer_one_irq(struct stm32_spi *spi) in stm32_spi_transfer_one_irq() argument
723 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32_spi_transfer_one_irq()
725 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32_spi_transfer_one_irq()
727 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32_spi_transfer_one_irq()
733 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_irq()
735 stm32_spi_enable(spi); in stm32_spi_transfer_one_irq()
738 if (spi->tx_buf) in stm32_spi_transfer_one_irq()
739 stm32_spi_write_txfifo(spi); in stm32_spi_transfer_one_irq()
741 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART); in stm32_spi_transfer_one_irq()
743 writel_relaxed(ier, spi->base + STM32_SPI_IER); in stm32_spi_transfer_one_irq()
745 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_irq()
756 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, in stm32_spi_transfer_one_dma() argument
764 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
767 if (spi->rx_buf) { in stm32_spi_transfer_one_dma()
768 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); in stm32_spi_transfer_one_dma()
769 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
772 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN); in stm32_spi_transfer_one_dma()
775 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
782 if (spi->tx_buf) { in stm32_spi_transfer_one_dma()
783 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); in stm32_spi_transfer_one_dma()
784 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
787 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
793 if ((spi->tx_buf && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
794 (spi->rx_buf && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
799 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
802 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
806 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
810 if (spi->cur_comm == SPI_SIMPLEX_TX) { in stm32_spi_transfer_one_dma()
812 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
816 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
820 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
823 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN); in stm32_spi_transfer_one_dma()
828 writel_relaxed(ier, spi->base + STM32_SPI_IER); in stm32_spi_transfer_one_dma()
830 stm32_spi_enable(spi); in stm32_spi_transfer_one_dma()
832 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART); in stm32_spi_transfer_one_dma()
834 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
839 if (spi->rx_buf) in stm32_spi_transfer_one_dma()
840 dmaengine_terminate_all(spi->dma_rx); in stm32_spi_transfer_one_dma()
843 stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN); in stm32_spi_transfer_one_dma()
845 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
847 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
849 return stm32_spi_transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
857 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, in stm32_spi_transfer_one_setup() argument
866 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
868 if (spi->cur_bpw != transfer->bits_per_word) { in stm32_spi_transfer_one_setup()
871 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
872 bpw = spi->cur_bpw - 1; in stm32_spi_transfer_one_setup()
877 spi->cur_fthlv = stm32_spi_prepare_fthlv(spi); in stm32_spi_transfer_one_setup()
878 fthlv = spi->cur_fthlv - 1; in stm32_spi_transfer_one_setup()
884 if (spi->cur_speed != transfer->speed_hz) { in stm32_spi_transfer_one_setup()
887 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
888 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz); in stm32_spi_transfer_one_setup()
894 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
901 writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) & in stm32_spi_transfer_one_setup()
903 spi->base + STM32_SPI_CFG1); in stm32_spi_transfer_one_setup()
909 * is forbidden und unvalidated by SPI subsystem so depending in stm32_spi_transfer_one_setup()
915 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR); in stm32_spi_transfer_one_setup()
917 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR); in stm32_spi_transfer_one_setup()
924 if (spi->cur_comm != mode) { in stm32_spi_transfer_one_setup()
925 spi->cur_comm = mode; in stm32_spi_transfer_one_setup()
932 if ((transfer->len > 1) && (spi->cur_midi > 0)) { in stm32_spi_transfer_one_setup()
933 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); in stm32_spi_transfer_one_setup()
934 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32_spi_transfer_one_setup()
937 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32_spi_transfer_one_setup()
944 writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) & in stm32_spi_transfer_one_setup()
946 spi->base + STM32_SPI_CFG2); in stm32_spi_transfer_one_setup()
948 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
950 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
957 writel_relaxed(nb_words, spi->base + STM32_SPI_CR2); in stm32_spi_transfer_one_setup()
963 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
965 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
966 spi->cur_comm); in stm32_spi_transfer_one_setup()
967 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
969 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
970 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
971 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
972 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
973 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
974 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
977 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
992 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_transfer_one() local
995 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
996 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
997 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
998 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1000 spi->cur_usedma = (master->can_dma && in stm32_spi_transfer_one()
1003 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); in stm32_spi_transfer_one()
1005 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1009 if (spi->cur_usedma) in stm32_spi_transfer_one()
1010 return stm32_spi_transfer_one_dma(spi, transfer); in stm32_spi_transfer_one()
1012 return stm32_spi_transfer_one_irq(spi); in stm32_spi_transfer_one()
1026 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_unprepare_msg() local
1028 stm32_spi_disable(spi); in stm32_spi_unprepare_msg()
1034 * stm32_spi_config - Configure SPI controller as SPI master
1036 static int stm32_spi_config(struct stm32_spi *spi) in stm32_spi_config() argument
1040 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_config()
1043 stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD); in stm32_spi_config()
1050 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI | in stm32_spi_config()
1060 stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER | in stm32_spi_config()
1064 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_config()
1070 { .compatible = "st,stm32h7-spi", },
1078 struct stm32_spi *spi; in stm32_spi_probe() local
1084 dev_err(&pdev->dev, "spi master allocation failed\n"); in stm32_spi_probe()
1089 spi = spi_master_get_devdata(master); in stm32_spi_probe()
1090 spi->dev = &pdev->dev; in stm32_spi_probe()
1091 spi->master = master; in stm32_spi_probe()
1092 spin_lock_init(&spi->lock); in stm32_spi_probe()
1095 spi->base = devm_ioremap_resource(&pdev->dev, res); in stm32_spi_probe()
1096 if (IS_ERR(spi->base)) { in stm32_spi_probe()
1097 ret = PTR_ERR(spi->base); in stm32_spi_probe()
1100 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
1102 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
1103 if (spi->irq <= 0) { in stm32_spi_probe()
1104 dev_err(&pdev->dev, "no irq: %d\n", spi->irq); in stm32_spi_probe()
1108 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL, in stm32_spi_probe()
1112 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
1117 spi->clk = devm_clk_get(&pdev->dev, 0); in stm32_spi_probe()
1118 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
1119 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
1124 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
1129 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
1130 if (!spi->clk_rate) { in stm32_spi_probe()
1136 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in stm32_spi_probe()
1137 if (!IS_ERR(spi->rst)) { in stm32_spi_probe()
1138 reset_control_assert(spi->rst); in stm32_spi_probe()
1140 reset_control_deassert(spi->rst); in stm32_spi_probe()
1143 spi->fifo_size = stm32_spi_get_fifo_size(spi); in stm32_spi_probe()
1145 ret = stm32_spi_config(spi); in stm32_spi_probe()
1157 master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi); in stm32_spi_probe()
1158 master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN; in stm32_spi_probe()
1159 master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX; in stm32_spi_probe()
1165 spi->dma_tx = dma_request_slave_channel(spi->dev, "tx"); in stm32_spi_probe()
1166 if (!spi->dma_tx) in stm32_spi_probe()
1169 master->dma_tx = spi->dma_tx; in stm32_spi_probe()
1171 spi->dma_rx = dma_request_slave_channel(spi->dev, "rx"); in stm32_spi_probe()
1172 if (!spi->dma_rx) in stm32_spi_probe()
1175 master->dma_rx = spi->dma_rx; in stm32_spi_probe()
1177 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
1185 dev_err(&pdev->dev, "spi master registration failed: %d\n", in stm32_spi_probe()
1218 if (spi->dma_tx) in stm32_spi_probe()
1219 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
1220 if (spi->dma_rx) in stm32_spi_probe()
1221 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
1225 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
1235 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_remove() local
1237 stm32_spi_disable(spi); in stm32_spi_remove()
1244 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
1255 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_suspend() local
1257 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
1265 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_resume() local
1267 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
1287 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_resume() local
1296 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
1321 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");