Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:spi
2 * Copyright (C) 2012 - 2014 Allwinner Tech
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
23 #include <linux/spi/spi.h>
96 return readl(sspi->base_addr + reg); in sun4i_spi_read()
101 writel(value, sspi->base_addr + reg); in sun4i_spi_write()
142 while (len--) { in sun4i_spi_drain_fifo()
143 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); in sun4i_spi_drain_fifo()
144 if (sspi->rx_buf) in sun4i_spi_drain_fifo()
145 *sspi->rx_buf++ = byte; in sun4i_spi_drain_fifo()
155 cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi); in sun4i_spi_fill_fifo()
157 len = min3(len, (int)cnt, sspi->len); in sun4i_spi_fill_fifo()
159 while (len--) { in sun4i_spi_fill_fifo()
160 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; in sun4i_spi_fill_fifo()
161 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG); in sun4i_spi_fill_fifo()
162 sspi->len--; in sun4i_spi_fill_fifo()
166 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) in sun4i_spi_set_cs() argument
168 struct sun4i_spi *sspi = spi_master_get_devdata(spi->master); in sun4i_spi_set_cs()
174 reg |= SUN4I_CTL_CS(spi->chip_select); in sun4i_spi_set_cs()
195 if (spi->mode & SPI_CS_HIGH) in sun4i_spi_set_cs()
203 static size_t sun4i_spi_max_transfer_size(struct spi_device *spi) in sun4i_spi_max_transfer_size() argument
205 return SUN4I_FIFO_DEPTH - 1; in sun4i_spi_max_transfer_size()
209 struct spi_device *spi, in sun4i_spi_transfer_one() argument
220 if (tfr->len > SUN4I_MAX_XFER_SIZE) in sun4i_spi_transfer_one()
221 return -EMSGSIZE; in sun4i_spi_transfer_one()
223 if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE) in sun4i_spi_transfer_one()
224 return -EMSGSIZE; in sun4i_spi_transfer_one()
226 reinit_completion(&sspi->done); in sun4i_spi_transfer_one()
227 sspi->tx_buf = tfr->tx_buf; in sun4i_spi_transfer_one()
228 sspi->rx_buf = tfr->rx_buf; in sun4i_spi_transfer_one()
229 sspi->len = tfr->len; in sun4i_spi_transfer_one()
245 if (spi->mode & SPI_CPOL) in sun4i_spi_transfer_one()
250 if (spi->mode & SPI_CPHA) in sun4i_spi_transfer_one()
255 if (spi->mode & SPI_LSB_FIRST) in sun4i_spi_transfer_one()
265 if (sspi->rx_buf) in sun4i_spi_transfer_one()
273 mclk_rate = clk_get_rate(sspi->mclk); in sun4i_spi_transfer_one()
274 if (mclk_rate < (2 * tfr->speed_hz)) { in sun4i_spi_transfer_one()
275 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun4i_spi_transfer_one()
276 mclk_rate = clk_get_rate(sspi->mclk); in sun4i_spi_transfer_one()
293 div = mclk_rate / (2 * tfr->speed_hz); in sun4i_spi_transfer_one()
296 div--; in sun4i_spi_transfer_one()
300 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); in sun4i_spi_transfer_one()
307 if (sspi->tx_buf) in sun4i_spi_transfer_one()
308 tx_len = tfr->len; in sun4i_spi_transfer_one()
311 sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len)); in sun4i_spi_transfer_one()
319 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1); in sun4i_spi_transfer_one()
332 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); in sun4i_spi_transfer_one()
334 timeout = wait_for_completion_timeout(&sspi->done, in sun4i_spi_transfer_one()
338 dev_warn(&master->dev, in sun4i_spi_transfer_one()
340 dev_name(&spi->dev), tfr->len, tfr->speed_hz, in sun4i_spi_transfer_one()
341 jiffies_to_msecs(end - start), tx_time); in sun4i_spi_transfer_one()
342 ret = -ETIMEDOUT; in sun4i_spi_transfer_one()
362 complete(&sspi->done); in sun4i_spi_handler()
378 if (!sspi->len) in sun4i_spi_handler()
382 /* Only clear the interrupt _after_ re-seeding the FIFO */ in sun4i_spi_handler()
397 ret = clk_prepare_enable(sspi->hclk); in sun4i_spi_runtime_resume()
403 ret = clk_prepare_enable(sspi->mclk); in sun4i_spi_runtime_resume()
415 clk_disable_unprepare(sspi->hclk); in sun4i_spi_runtime_resume()
425 clk_disable_unprepare(sspi->mclk); in sun4i_spi_runtime_suspend()
426 clk_disable_unprepare(sspi->hclk); in sun4i_spi_runtime_suspend()
438 master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi)); in sun4i_spi_probe()
440 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in sun4i_spi_probe()
441 return -ENOMEM; in sun4i_spi_probe()
448 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); in sun4i_spi_probe()
449 if (IS_ERR(sspi->base_addr)) { in sun4i_spi_probe()
450 ret = PTR_ERR(sspi->base_addr); in sun4i_spi_probe()
456 dev_err(&pdev->dev, "No spi IRQ specified\n"); in sun4i_spi_probe()
457 ret = -ENXIO; in sun4i_spi_probe()
461 ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler, in sun4i_spi_probe()
462 0, "sun4i-spi", sspi); in sun4i_spi_probe()
464 dev_err(&pdev->dev, "Cannot request IRQ\n"); in sun4i_spi_probe()
468 sspi->master = master; in sun4i_spi_probe()
469 master->max_speed_hz = 100 * 1000 * 1000; in sun4i_spi_probe()
470 master->min_speed_hz = 3 * 1000; in sun4i_spi_probe()
471 master->set_cs = sun4i_spi_set_cs; in sun4i_spi_probe()
472 master->transfer_one = sun4i_spi_transfer_one; in sun4i_spi_probe()
473 master->num_chipselect = 4; in sun4i_spi_probe()
474 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; in sun4i_spi_probe()
475 master->bits_per_word_mask = SPI_BPW_MASK(8); in sun4i_spi_probe()
476 master->dev.of_node = pdev->dev.of_node; in sun4i_spi_probe()
477 master->auto_runtime_pm = true; in sun4i_spi_probe()
478 master->max_transfer_size = sun4i_spi_max_transfer_size; in sun4i_spi_probe()
480 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); in sun4i_spi_probe()
481 if (IS_ERR(sspi->hclk)) { in sun4i_spi_probe()
482 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); in sun4i_spi_probe()
483 ret = PTR_ERR(sspi->hclk); in sun4i_spi_probe()
487 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun4i_spi_probe()
488 if (IS_ERR(sspi->mclk)) { in sun4i_spi_probe()
489 dev_err(&pdev->dev, "Unable to acquire module clock\n"); in sun4i_spi_probe()
490 ret = PTR_ERR(sspi->mclk); in sun4i_spi_probe()
494 init_completion(&sspi->done); in sun4i_spi_probe()
497 * This wake-up/shutdown pattern is to be able to have the in sun4i_spi_probe()
500 ret = sun4i_spi_runtime_resume(&pdev->dev); in sun4i_spi_probe()
502 dev_err(&pdev->dev, "Couldn't resume the device\n"); in sun4i_spi_probe()
506 pm_runtime_set_active(&pdev->dev); in sun4i_spi_probe()
507 pm_runtime_enable(&pdev->dev); in sun4i_spi_probe()
508 pm_runtime_idle(&pdev->dev); in sun4i_spi_probe()
510 ret = devm_spi_register_master(&pdev->dev, master); in sun4i_spi_probe()
512 dev_err(&pdev->dev, "cannot register SPI master\n"); in sun4i_spi_probe()
519 pm_runtime_disable(&pdev->dev); in sun4i_spi_probe()
520 sun4i_spi_runtime_suspend(&pdev->dev); in sun4i_spi_probe()
528 pm_runtime_force_suspend(&pdev->dev); in sun4i_spi_remove()
534 { .compatible = "allwinner,sun4i-a10-spi", },
548 .name = "sun4i-spi",
556 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
557 MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");