Lines Matching +full:soc +full:- +full:level
31 #include <dt-bindings/thermal/tegra124-soctherm.h>
155 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
158 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
161 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
187 static const int min_low_temp = -127000;
236 struct tegra_soctherm_soc *soc; member
244 * ccroc_writel() - writes a value to a CCROC register
253 writel(value, (ts->ccroc_regs + reg)); in ccroc_writel()
257 * ccroc_readl() - reads specified register from CCROC IP block
265 return readl(ts->ccroc_regs + reg); in ccroc_readl()
270 const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i]; in enable_tsensor()
271 void __iomem *base = tegra->regs + sensor->base; in enable_tsensor()
274 val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT; in enable_tsensor()
277 val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT; in enable_tsensor()
278 val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT; in enable_tsensor()
279 val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT; in enable_tsensor()
283 writel(tegra->calib[i], base + SENSOR_CONFIG2); in enable_tsensor()
302 t *= -1; in translate_temp()
312 val = readl(zone->reg); in tegra_thermctl_get_temp()
313 val = REG_GET_MASK(val, zone->sg->sensor_temp_mask); in tegra_thermctl_get_temp()
320 * enforce_temp_range() - check and enforce temperature range [min, max]
341 * thermtrip_program() - Configures the hardware to shut down the
354 * Return: 0 upon success, or %-EINVAL upon failure.
364 if (!sg || !sg->thermtrip_threshold_mask) in thermtrip_program()
365 return -EINVAL; in thermtrip_program()
367 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; in thermtrip_program()
369 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); in thermtrip_program()
370 r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp); in thermtrip_program()
371 r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1); in thermtrip_program()
372 r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0); in thermtrip_program()
373 writel(r, ts->regs + THERMCTL_THERMTRIP_CTL); in thermtrip_program()
379 * throttrip_program() - Configures the hardware to throttle the
393 * Return: 0 upon success, or %-EINVAL upon failure.
405 if (!sg || !stc || !stc->init) in throttrip_program()
406 return -EINVAL; in throttrip_program()
408 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; in throttrip_program()
411 throt = stc->id; in throttrip_program()
412 reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1); in throttrip_program()
422 "invalid throt id %d - assuming HEAVY", in throttrip_program()
426 r = readl(ts->regs + reg_off); in throttrip_program()
427 r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp); in throttrip_program()
428 r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp); in throttrip_program()
432 writel(r, ts->regs + reg_off); in throttrip_program()
442 for (i = 0; ts->throt_cfgs[i].name; i++) in find_throttle_cfg_by_name()
443 if (!strcmp(ts->throt_cfgs[i].name, name)) in find_throttle_cfg_by_name()
444 return &ts->throt_cfgs[i]; in find_throttle_cfg_by_name()
452 struct thermal_zone_device *tz = zone->tz; in tegra_thermctl_set_trip_temp()
453 struct tegra_soctherm *ts = zone->ts; in tegra_thermctl_set_trip_temp()
454 const struct tegra_tsensor_group *sg = zone->sg; in tegra_thermctl_set_trip_temp()
455 struct device *dev = zone->dev; in tegra_thermctl_set_trip_temp()
460 return -EINVAL; in tegra_thermctl_set_trip_temp()
462 ret = tz->ops->get_trip_type(tz, trip, &type); in tegra_thermctl_set_trip_temp()
475 if (!ts->throt_cfgs[i].init) in tegra_thermctl_set_trip_temp()
478 cdev = ts->throt_cfgs[i].cdev; in tegra_thermctl_set_trip_temp()
480 stc = find_throttle_cfg_by_name(ts, cdev->type); in tegra_thermctl_set_trip_temp()
503 return -EINVAL; in get_hot_temp()
506 ret = tz->ops->get_trip_type(tz, i, &type); in get_hot_temp()
508 return -EINVAL; in get_hot_temp()
510 ret = tz->ops->get_trip_temp(tz, i, temp); in get_hot_temp()
518 return -EINVAL; in get_hot_temp()
522 * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
529 * action when the configured SoC thermal sensor group reaches a
551 ret = tz->ops->get_crit_temp(tz, &temperature); in tegra_soctherm_set_hwtrips()
554 sg->name); in tegra_soctherm_set_hwtrips()
561 sg->name); in tegra_soctherm_set_hwtrips()
567 sg->name, temperature); in tegra_soctherm_set_hwtrips()
573 sg->name); in tegra_soctherm_set_hwtrips()
580 if (!ts->throt_cfgs[i].init) in tegra_soctherm_set_hwtrips()
583 cdev = ts->throt_cfgs[i].cdev; in tegra_soctherm_set_hwtrips()
585 stc = find_throttle_cfg_by_name(ts, cdev->type); in tegra_soctherm_set_hwtrips()
592 sg->name); in tegra_soctherm_set_hwtrips()
598 sg->name, temperature); in tegra_soctherm_set_hwtrips()
604 sg->name); in tegra_soctherm_set_hwtrips()
612 struct platform_device *pdev = s->private; in regs_show()
614 const struct tegra_tsensor *tsensors = ts->soc->tsensors; in regs_show()
615 const struct tegra_tsensor_group **ttgs = ts->soc->ttgs; in regs_show()
617 int i, level; in regs_show() local
619 seq_puts(s, "-----TSENSE (convert HW)-----\n"); in regs_show()
621 for (i = 0; i < ts->soc->num_tsensors; i++) { in regs_show()
622 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1); in regs_show()
640 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1); in regs_show()
646 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0); in regs_show()
652 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0); in regs_show()
664 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2); in regs_show()
671 r = readl(ts->regs + SENSOR_PDIV); in regs_show()
674 r = readl(ts->regs + SENSOR_HOTSPOT_OFF); in regs_show()
678 seq_puts(s, "-----SOC_THERM-----\n"); in regs_show()
680 r = readl(ts->regs + SENSOR_TEMP1); in regs_show()
685 r = readl(ts->regs + SENSOR_TEMP2); in regs_show()
691 for (i = 0; i < ts->soc->num_ttgs; i++) { in regs_show()
692 seq_printf(s, "%s:\n", ttgs[i]->name); in regs_show()
693 for (level = 0; level < 4; level++) { in regs_show()
696 u16 off = ttgs[i]->thermctl_lvl0_offset; in regs_show()
698 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
700 mask = ttgs[i]->thermctl_lvl0_up_thresh_mask; in regs_show()
702 v = sign_extend32(state, ts->soc->bptt - 1); in regs_show()
703 v *= ts->soc->thresh_grain; in regs_show()
704 seq_printf(s, " %d: Up/Dn(%d /", level, v); in regs_show()
706 mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask; in regs_show()
708 v = sign_extend32(state, ts->soc->bptt - 1); in regs_show()
709 v *= ts->soc->thresh_grain; in regs_show()
749 r = readl(ts->regs + THERMCTL_STATS_CTL); in regs_show()
751 r & STATS_CTL_EN_UP ? "En" : "--", in regs_show()
752 r & STATS_CTL_EN_DN ? "En" : "--"); in regs_show()
754 for (level = 0; level < 4; level++) { in regs_show()
758 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
759 seq_printf(s, " Level_%d Up(%d) ", level, r); in regs_show()
762 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
766 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); in regs_show()
767 state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask); in regs_show()
769 for (i = 0; i < ts->soc->num_ttgs; i++) { in regs_show()
770 state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask); in regs_show()
771 seq_printf(s, " %s En(%d) ", ttgs[i]->name, state); in regs_show()
772 state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask); in regs_show()
773 state *= ts->soc->thresh_grain; in regs_show()
777 r = readl(ts->regs + THROT_GLOBAL_CFG); in regs_show()
781 seq_puts(s, "---------------------------------------------------\n"); in regs_show()
782 r = readl(ts->regs + THROT_STATUS); in regs_show()
790 r = readl(ts->regs + CPU_PSKIP_STATUS); in regs_show()
791 if (ts->soc->use_ccroc) { in regs_show()
808 return single_open(file, regs_show, inode->i_private); in regs_open()
825 dev_err(&pdev->dev, "failed to create debugfs directory\n"); in soctherm_debug_init()
829 tegra->debugfs_dir = root; in soctherm_debug_init()
834 dev_err(&pdev->dev, "failed to create debugfs file\n"); in soctherm_debug_init()
835 debugfs_remove_recursive(tegra->debugfs_dir); in soctherm_debug_init()
836 tegra->debugfs_dir = NULL; in soctherm_debug_init()
848 if (!tegra->clock_soctherm || !tegra->clock_tsensor) in soctherm_clk_enable()
849 return -EINVAL; in soctherm_clk_enable()
851 reset_control_assert(tegra->reset); in soctherm_clk_enable()
854 err = clk_prepare_enable(tegra->clock_soctherm); in soctherm_clk_enable()
856 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
860 err = clk_prepare_enable(tegra->clock_tsensor); in soctherm_clk_enable()
862 clk_disable_unprepare(tegra->clock_soctherm); in soctherm_clk_enable()
863 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
867 clk_disable_unprepare(tegra->clock_tsensor); in soctherm_clk_enable()
868 clk_disable_unprepare(tegra->clock_soctherm); in soctherm_clk_enable()
871 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
886 struct tegra_soctherm *ts = cdev->devdata; in throt_get_cdev_cur_state()
889 r = readl(ts->regs + THROT_STATUS); in throt_get_cdev_cur_state()
911 * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
916 struct device *dev = &pdev->dev; in soctherm_init_hw_throt_cdev()
924 ts->throt_cfgs[i].name = throt_names[i]; in soctherm_init_hw_throt_cdev()
925 ts->throt_cfgs[i].id = i; in soctherm_init_hw_throt_cdev()
926 ts->throt_cfgs[i].init = false; in soctherm_init_hw_throt_cdev()
929 np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs"); in soctherm_init_hw_throt_cdev()
932 "throttle-cfg: no throttle-cfgs - not enabling\n"); in soctherm_init_hw_throt_cdev()
940 name = np_stcc->name; in soctherm_init_hw_throt_cdev()
944 "throttle-cfg: could not find %s\n", name); in soctherm_init_hw_throt_cdev()
951 "throttle-cfg: %s: missing priority\n", name); in soctherm_init_hw_throt_cdev()
954 stc->priority = val; in soctherm_init_hw_throt_cdev()
956 if (ts->soc->use_ccroc) { in soctherm_init_hw_throt_cdev()
958 "nvidia,cpu-throt-level", in soctherm_init_hw_throt_cdev()
962 "throttle-cfg: %s: missing cpu-throt-level\n", in soctherm_init_hw_throt_cdev()
966 stc->cpu_throt_level = val; in soctherm_init_hw_throt_cdev()
969 "nvidia,cpu-throt-percent", in soctherm_init_hw_throt_cdev()
973 "throttle-cfg: %s: missing cpu-throt-percent\n", in soctherm_init_hw_throt_cdev()
977 stc->cpu_throt_depth = val; in soctherm_init_hw_throt_cdev()
986 "throttle-cfg: %s: failed to register cooling device\n", in soctherm_init_hw_throt_cdev()
991 stc->cdev = tcd; in soctherm_init_hw_throt_cdev()
992 stc->init = true; in soctherm_init_hw_throt_cdev()
999 * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
1000 * @level: describing the level LOW/MED/HIGH of throttling
1002 * It's necessary to set up the CPU-local CCROC NV_THERM instance with
1003 * the M/N values desired for each level. This function does this.
1005 * This function pre-programs the CCROC NV_THERM levels in terms of
1006 * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
1009 static void throttlectl_cpu_level_cfg(struct tegra_soctherm *ts, int level) in throttlectl_cpu_level_cfg() argument
1014 switch (level) { in throttlectl_cpu_level_cfg()
1033 r = ccroc_readl(ts, CCROC_THROT_PSKIP_RAMP_CPU_REG(level)); in throttlectl_cpu_level_cfg()
1036 ccroc_writel(ts, r, CCROC_THROT_PSKIP_RAMP_CPU_REG(level)); in throttlectl_cpu_level_cfg()
1038 r = ccroc_readl(ts, CCROC_THROT_PSKIP_CTRL_CPU_REG(level)); in throttlectl_cpu_level_cfg()
1042 ccroc_writel(ts, r, CCROC_THROT_PSKIP_CTRL_CPU_REG(level)); in throttlectl_cpu_level_cfg()
1046 * throttlectl_cpu_level_select() - program CPU pulse skipper config
1051 * data. This function is used on SoCs which have CPU-local pulse
1062 switch (ts->throt_cfgs[throt].cpu_throt_level) { in throttlectl_cpu_level_select()
1077 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1081 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1085 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1089 * throttlectl_cpu_mn() - program CPU pulse skipper configuration
1106 depth = ts->throt_cfgs[throt].cpu_throt_depth; in throttlectl_cpu_mn()
1109 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1113 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1115 r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1118 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1122 * soctherm_throttle_program() - programs pulse skippers' configuration
1132 struct soctherm_throt_cfg stc = ts->throt_cfgs[throt]; in soctherm_throttle_program()
1138 if (ts->soc->use_ccroc) in soctherm_throttle_program()
1144 writel(r, ts->regs + THROT_PRIORITY_CTRL(throt)); in soctherm_throttle_program()
1147 writel(r, ts->regs + THROT_DELAY_CTRL(throt)); in soctherm_throttle_program()
1149 r = readl(ts->regs + THROT_PRIORITY_LOCK); in soctherm_throttle_program()
1155 writel(r, ts->regs + THROT_PRIORITY_LOCK); in soctherm_throttle_program()
1165 if (ts->soc->use_ccroc) { in tegra_soctherm_throttle()
1176 if (ts->soc->use_ccroc) { in tegra_soctherm_throttle()
1183 writel(v, ts->regs + THROT_GLOBAL_CFG); in tegra_soctherm_throttle()
1185 v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
1187 writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
1193 writel(v, ts->regs + THERMCTL_STATS_CTL); in tegra_soctherm_throttle()
1199 const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs; in soctherm_init()
1204 for (i = 0; i < tegra->soc->num_tsensors; ++i) in soctherm_init()
1208 pdiv = readl(tegra->regs + SENSOR_PDIV); in soctherm_init()
1209 hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF); in soctherm_init()
1210 for (i = 0; i < tegra->soc->num_ttgs; ++i) { in soctherm_init()
1211 pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask, in soctherm_init()
1212 ttgs[i]->pdiv); in soctherm_init()
1214 if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX) in soctherm_init()
1217 ttgs[i]->pllx_hotspot_mask, in soctherm_init()
1218 ttgs[i]->pllx_hotspot_diff); in soctherm_init()
1220 writel(pdiv, tegra->regs + SENSOR_PDIV); in soctherm_init()
1221 writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF); in soctherm_init()
1224 tegra_soctherm_throttle(&pdev->dev); in soctherm_init()
1230 .compatible = "nvidia,tegra124-soctherm",
1236 .compatible = "nvidia,tegra132-soctherm",
1242 .compatible = "nvidia,tegra210-soctherm",
1257 struct tegra_soctherm_soc *soc; in tegra_soctherm_probe() local
1261 match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node); in tegra_soctherm_probe()
1263 return -ENODEV; in tegra_soctherm_probe()
1265 soc = (struct tegra_soctherm_soc *)match->data; in tegra_soctherm_probe()
1266 if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM) in tegra_soctherm_probe()
1267 return -EINVAL; in tegra_soctherm_probe()
1269 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); in tegra_soctherm_probe()
1271 return -ENOMEM; in tegra_soctherm_probe()
1273 dev_set_drvdata(&pdev->dev, tegra); in tegra_soctherm_probe()
1275 tegra->soc = soc; in tegra_soctherm_probe()
1278 "soctherm-reg"); in tegra_soctherm_probe()
1279 tegra->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_soctherm_probe()
1280 if (IS_ERR(tegra->regs)) { in tegra_soctherm_probe()
1281 dev_err(&pdev->dev, "can't get soctherm registers"); in tegra_soctherm_probe()
1282 return PTR_ERR(tegra->regs); in tegra_soctherm_probe()
1285 if (!tegra->soc->use_ccroc) { in tegra_soctherm_probe()
1287 "car-reg"); in tegra_soctherm_probe()
1288 tegra->clk_regs = devm_ioremap_resource(&pdev->dev, res); in tegra_soctherm_probe()
1289 if (IS_ERR(tegra->clk_regs)) { in tegra_soctherm_probe()
1290 dev_err(&pdev->dev, "can't get car clk registers"); in tegra_soctherm_probe()
1291 return PTR_ERR(tegra->clk_regs); in tegra_soctherm_probe()
1295 "ccroc-reg"); in tegra_soctherm_probe()
1296 tegra->ccroc_regs = devm_ioremap_resource(&pdev->dev, res); in tegra_soctherm_probe()
1297 if (IS_ERR(tegra->ccroc_regs)) { in tegra_soctherm_probe()
1298 dev_err(&pdev->dev, "can't get ccroc registers"); in tegra_soctherm_probe()
1299 return PTR_ERR(tegra->ccroc_regs); in tegra_soctherm_probe()
1303 tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm"); in tegra_soctherm_probe()
1304 if (IS_ERR(tegra->reset)) { in tegra_soctherm_probe()
1305 dev_err(&pdev->dev, "can't get soctherm reset\n"); in tegra_soctherm_probe()
1306 return PTR_ERR(tegra->reset); in tegra_soctherm_probe()
1309 tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor"); in tegra_soctherm_probe()
1310 if (IS_ERR(tegra->clock_tsensor)) { in tegra_soctherm_probe()
1311 dev_err(&pdev->dev, "can't get tsensor clock\n"); in tegra_soctherm_probe()
1312 return PTR_ERR(tegra->clock_tsensor); in tegra_soctherm_probe()
1315 tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm"); in tegra_soctherm_probe()
1316 if (IS_ERR(tegra->clock_soctherm)) { in tegra_soctherm_probe()
1317 dev_err(&pdev->dev, "can't get soctherm clock\n"); in tegra_soctherm_probe()
1318 return PTR_ERR(tegra->clock_soctherm); in tegra_soctherm_probe()
1321 tegra->calib = devm_kcalloc(&pdev->dev, in tegra_soctherm_probe()
1322 soc->num_tsensors, sizeof(u32), in tegra_soctherm_probe()
1324 if (!tegra->calib) in tegra_soctherm_probe()
1325 return -ENOMEM; in tegra_soctherm_probe()
1328 err = tegra_calc_shared_calib(soc->tfuse, &shared_calib); in tegra_soctherm_probe()
1333 for (i = 0; i < soc->num_tsensors; ++i) { in tegra_soctherm_probe()
1334 err = tegra_calc_tsensor_calib(&soc->tsensors[i], in tegra_soctherm_probe()
1336 &tegra->calib[i]); in tegra_soctherm_probe()
1341 tegra->thermctl_tzs = devm_kcalloc(&pdev->dev, in tegra_soctherm_probe()
1342 soc->num_ttgs, sizeof(*z), in tegra_soctherm_probe()
1344 if (!tegra->thermctl_tzs) in tegra_soctherm_probe()
1345 return -ENOMEM; in tegra_soctherm_probe()
1355 for (i = 0; i < soc->num_ttgs; ++i) { in tegra_soctherm_probe()
1357 devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL); in tegra_soctherm_probe()
1359 err = -ENOMEM; in tegra_soctherm_probe()
1363 zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset; in tegra_soctherm_probe()
1364 zone->dev = &pdev->dev; in tegra_soctherm_probe()
1365 zone->sg = soc->ttgs[i]; in tegra_soctherm_probe()
1366 zone->ts = tegra; in tegra_soctherm_probe()
1368 z = devm_thermal_zone_of_sensor_register(&pdev->dev, in tegra_soctherm_probe()
1369 soc->ttgs[i]->id, zone, in tegra_soctherm_probe()
1373 dev_err(&pdev->dev, "failed to register sensor: %d\n", in tegra_soctherm_probe()
1378 zone->tz = z; in tegra_soctherm_probe()
1379 tegra->thermctl_tzs[soc->ttgs[i]->id] = z; in tegra_soctherm_probe()
1382 err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z); in tegra_soctherm_probe()
1401 debugfs_remove_recursive(tegra->debugfs_dir); in tegra_soctherm_remove()
1421 struct tegra_soctherm_soc *soc = tegra->soc; in soctherm_resume() local
1426 dev_err(&pdev->dev, in soctherm_resume()
1433 for (i = 0; i < soc->num_ttgs; ++i) { in soctherm_resume()
1436 tz = tegra->thermctl_tzs[soc->ttgs[i]->id]; in soctherm_resume()
1437 err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz); in soctherm_resume()
1439 dev_err(&pdev->dev, in soctherm_resume()