51  * struct tb_dma_port - DMA control port
52  * @sw: Switch the DMA port belongs to
58 	struct tb_switch *sw;  member
65  * When the switch is in safe mode it supports very little functionality
71 	u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63);  in dma_port_match()
73 	if (pkg->frame.eof == TB_CFG_PKG_ERROR)  in dma_port_match()
75 	if (pkg->frame.eof != req->response_type)  in dma_port_match()
77 	if (route != tb_cfg_get_route(req->request))  in dma_port_match()
79 	if (pkg->frame.size != req->response_size)  in dma_port_match()
87 	memcpy(req->response, pkg->buffer, req->response_size);  in dma_port_copy()
110 		return -ENOMEM;  in dma_port_read()
112 	req->match = dma_port_match;  in dma_port_read()
113 	req->copy = dma_port_copy;  in dma_port_read()
114 	req->request = &request;  in dma_port_read()
115 	req->request_size = sizeof(request);  in dma_port_read()
116 	req->request_type = TB_CFG_PKG_READ;  in dma_port_read()
117 	req->response = &reply;  in dma_port_read()
118 	req->response_size = 12 + 4 * length;  in dma_port_read()
119 	req->response_type = TB_CFG_PKG_READ;  in dma_port_read()
153 		return -ENOMEM;  in dma_port_write()
155 	req->match = dma_port_match;  in dma_port_write()
156 	req->copy = dma_port_copy;  in dma_port_write()
157 	req->request = &request;  in dma_port_write()
158 	req->request_size = 12 + 4 * length;  in dma_port_write()
159 	req->request_type = TB_CFG_PKG_WRITE;  in dma_port_write()
160 	req->response = &reply;  in dma_port_write()
161 	req->response_size = sizeof(reply);  in dma_port_write()
162 	req->response_type = TB_CFG_PKG_WRITE;  in dma_port_write()
171 static int dma_find_port(struct tb_switch *sw)  in dma_find_port()  argument
184 		ret = dma_port_read(sw->tb->ctl, &type, tb_route(sw), ports[i],  in dma_find_port()
190 	return -ENODEV;  in dma_find_port()
194  * dma_port_alloc() - Finds DMA control port from a switch pointed by route
195  * @sw: Switch from where find the DMA port
202  * mode.
204 struct tb_dma_port *dma_port_alloc(struct tb_switch *sw)  in dma_port_alloc()  argument
209 	port = dma_find_port(sw);  in dma_port_alloc()
217 	dma->buf = kmalloc_array(MAIL_DATA_DWORDS, sizeof(u32), GFP_KERNEL);  in dma_port_alloc()
218 	if (!dma->buf) {  in dma_port_alloc()
223 	dma->sw = sw;  in dma_port_alloc()
224 	dma->port = port;  in dma_port_alloc()
225 	dma->base = DMA_PORT_CAP;  in dma_port_alloc()
231  * dma_port_free() - Release DMA control port structure
237 		kfree(dma->buf);  in dma_port_free()
246 	struct tb_switch *sw = dma->sw;  in dma_port_wait_for_completion()  local
252 		ret = dma_port_read(sw->tb->ctl, &in, tb_route(sw), dma->port,  in dma_port_wait_for_completion()
253 				    dma->base + MAIL_IN, 1, 50);  in dma_port_wait_for_completion()
255 			if (ret != -ETIMEDOUT)  in dma_port_wait_for_completion()
264 	return -ETIMEDOUT;  in dma_port_wait_for_completion()
273 		return -EINVAL;  in status_to_errno()
275 		return -EACCES;  in status_to_errno()
278 	return -EIO;  in status_to_errno()
284 	struct tb_switch *sw = dma->sw;  in dma_port_request()  local
288 	ret = dma_port_write(sw->tb->ctl, &in, tb_route(sw), dma->port,  in dma_port_request()
289 			     dma->base + MAIL_IN, 1, DMA_PORT_TIMEOUT);  in dma_port_request()
297 	ret = dma_port_read(sw->tb->ctl, &out, tb_route(sw), dma->port,  in dma_port_request()
298 			    dma->base + MAIL_OUT, 1, DMA_PORT_TIMEOUT);  in dma_port_request()
308 	struct tb_switch *sw = dma->sw;  in dma_port_flash_read_block()  local
325 	return dma_port_read(sw->tb->ctl, buf, tb_route(sw), dma->port,  in dma_port_flash_read_block()
326 			     dma->base + MAIL_DATA, dwords, DMA_PORT_TIMEOUT);  in dma_port_flash_read_block()
332 	struct tb_switch *sw = dma->sw;  in dma_port_flash_write_block()  local
339 	ret = dma_port_write(sw->tb->ctl, buf, tb_route(sw), dma->port,  in dma_port_flash_write_block()
340 			    dma->base + MAIL_DATA, dwords, DMA_PORT_TIMEOUT);  in dma_port_flash_write_block()
352 	in |= ((dwords - 1) << MAIL_IN_DWORDS_SHIFT) & MAIL_IN_DWORDS_MASK;  in dma_port_flash_write_block()
360  * dma_port_flash_read() - Read from active flash region
379 		ret = dma_port_flash_read_block(dma, address, dma->buf,  in dma_port_flash_read()
382 			if (ret == -ETIMEDOUT) {  in dma_port_flash_read()
383 				if (retries--)  in dma_port_flash_read()
385 				ret = -EIO;  in dma_port_flash_read()
390 		memcpy(buf, dma->buf + offset, nbytes);  in dma_port_flash_read()
392 		size -= nbytes;  in dma_port_flash_read()
401  * dma_port_flash_write() - Write to non-active flash region
403  * @address: Address relative to the start of non-active region
407  * Writes block of data to the non-active flash region of the switch. If
420 			return -E2BIG;  in dma_port_flash_write()
430 		memcpy(dma->buf + offset, buf, nbytes);  in dma_port_flash_write()
434 			if (ret == -ETIMEDOUT) {  in dma_port_flash_write()
435 				if (retries--)  in dma_port_flash_write()
437 				ret = -EIO;  in dma_port_flash_write()
442 		size -= nbytes;  in dma_port_flash_write()
451  * dma_port_flash_update_auth() - Starts flash authenticate cycle
455  * non-active area was valid, the switch starts upgrade process where
456  * active and non-active area get swapped in the end. Caller should call
472  * dma_port_flash_update_auth_status() - Reads status of update auth command
486 	struct tb_switch *sw = dma->sw;  in dma_port_flash_update_auth_status()  local
490 	ret = dma_port_read(sw->tb->ctl, &out, tb_route(sw), dma->port,  in dma_port_flash_update_auth_status()
491 			    dma->base + MAIL_OUT, 1, DMA_PORT_TIMEOUT);  in dma_port_flash_update_auth_status()
509  * dma_port_power_cycle() - Power cycles the switch