Lines Matching +full:rx +full:- +full:int +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0+
32 #include <linux/dma-mapping.h>
35 #include <linux/platform_data/serial-imx.h>
36 #include <linux/platform_data/dma-imx.h>
127 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
156 #define UTS_LOOP (1<<12) /* Loop tx and rx */
163 /* We've been assigned a range on the "Low-density serial ports" major */
176 #define DRIVER_NAME "IMX-uart"
197 unsigned int old_status;
198 unsigned int have_rtscts:1;
199 unsigned int have_rtsgpio:1;
200 unsigned int dte_mode:1;
205 struct mctrl_gpios *gpios; member
208 unsigned int ucr1;
209 unsigned int ucr2;
210 unsigned int ucr3;
211 unsigned int ucr4;
212 unsigned int ufcr;
215 unsigned int dma_is_enabled:1;
216 unsigned int dma_is_rxing:1;
217 unsigned int dma_is_txing:1;
222 unsigned int rx_periods;
224 unsigned int tx_bytes;
225 unsigned int dma_tx_nents;
226 unsigned int saved_reg[10];
231 unsigned int ucr1;
232 unsigned int ucr2;
233 unsigned int ucr3;
257 .name = "imx1-uart",
260 .name = "imx21-uart",
263 .name = "imx53-uart",
266 .name = "imx6q-uart",
275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
276 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
287 sport->ucr1 = val; in imx_uart_writel()
290 sport->ucr2 = val; in imx_uart_writel()
293 sport->ucr3 = val; in imx_uart_writel()
296 sport->ucr4 = val; in imx_uart_writel()
299 sport->ufcr = val; in imx_uart_writel()
304 writel(val, sport->port.membase + offset); in imx_uart_writel()
311 return sport->ucr1; in imx_uart_readl()
320 if (!(sport->ucr2 & UCR2_SRST)) in imx_uart_readl()
321 sport->ucr2 = readl(sport->port.membase + offset); in imx_uart_readl()
322 return sport->ucr2; in imx_uart_readl()
325 return sport->ucr3; in imx_uart_readl()
328 return sport->ucr4; in imx_uart_readl()
331 return sport->ufcr; in imx_uart_readl()
334 return readl(sport->port.membase + offset); in imx_uart_readl()
340 return sport->devdata->uts_reg; in imx_uart_uts_reg()
343 static inline int imx_uart_is_imx1(struct imx_port *sport) in imx_uart_is_imx1()
345 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
348 static inline int imx_uart_is_imx21(struct imx_port *sport) in imx_uart_is_imx21()
350 return sport->devdata->devtype == IMX21_UART; in imx_uart_is_imx21()
353 static inline int imx_uart_is_imx53(struct imx_port *sport) in imx_uart_is_imx53()
355 return sport->devdata->devtype == IMX53_UART; in imx_uart_is_imx53()
358 static inline int imx_uart_is_imx6q(struct imx_port *sport) in imx_uart_is_imx6q()
360 return sport->devdata->devtype == IMX6Q_UART; in imx_uart_is_imx6q()
370 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
371 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
372 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
379 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
380 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
381 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
390 sport->port.mctrl |= TIOCM_RTS; in imx_uart_rts_active()
391 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_active()
400 sport->port.mctrl &= ~TIOCM_RTS; in imx_uart_rts_inactive()
401 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_inactive()
414 unsigned int ucr1, ucr2; in imx_uart_start_rx()
421 if (sport->dma_is_enabled) { in imx_uart_start_rx()
443 if (sport->dma_is_txing) in imx_uart_stop_tx()
450 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_stop_tx()
453 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
476 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
493 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
495 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
503 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
505 if (sport->port.x_char) { in imx_uart_transmit_buffer()
507 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
508 sport->port.icount.tx++; in imx_uart_transmit_buffer()
509 sport->port.x_char = 0; in imx_uart_transmit_buffer()
513 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
514 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
518 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
521 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
526 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
539 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
541 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
542 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in imx_uart_transmit_buffer()
543 sport->port.icount.tx++; in imx_uart_transmit_buffer()
547 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
550 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
556 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
557 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
561 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
563 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
570 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); in imx_uart_dma_tx_callback()
571 sport->port.icount.tx += sport->tx_bytes; in imx_uart_dma_tx_callback()
573 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
575 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
578 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
580 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
582 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
588 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
594 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
595 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
597 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
598 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
600 int ret; in imx_uart_dma_tx()
602 if (sport->dma_is_txing) in imx_uart_dma_tx()
609 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
611 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
612 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
613 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
615 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
617 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
618 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
619 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
622 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
630 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
635 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
636 desc->callback_param = sport; in imx_uart_dma_tx()
646 sport->dma_is_txing = 1; in imx_uart_dma_tx()
658 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
661 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
665 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
671 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in imx_uart_start_tx()
676 * In the DMA case this is done in the tx-callback. in imx_uart_start_tx()
678 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
685 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
690 if (sport->dma_is_enabled) { in imx_uart_start_tx()
691 if (sport->port.x_char) { in imx_uart_start_tx()
692 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
693 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
701 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
708 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) in imx_uart_rtsint()
714 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_rtsint()
718 uart_handle_cts_change(&sport->port, !!usr1); in imx_uart_rtsint()
719 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_rtsint()
721 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_rtsint()
725 static irqreturn_t imx_uart_txint(int irq, void *dev_id) in imx_uart_txint()
730 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_txint()
732 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_txint()
736 static irqreturn_t imx_uart_rxint(int irq, void *dev_id) in imx_uart_rxint()
739 unsigned int rx, flg, ignored = 0; in imx_uart_rxint() local
740 struct tty_port *port = &sport->port.state->port; in imx_uart_rxint()
743 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_rxint()
749 sport->port.icount.rx++; in imx_uart_rxint()
751 rx = imx_uart_readl(sport, URXD0); in imx_uart_rxint()
756 if (uart_handle_break(&sport->port)) in imx_uart_rxint()
760 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in imx_uart_rxint()
763 if (unlikely(rx & URXD_ERR)) { in imx_uart_rxint()
764 if (rx & URXD_BRK) in imx_uart_rxint()
765 sport->port.icount.brk++; in imx_uart_rxint()
766 else if (rx & URXD_PRERR) in imx_uart_rxint()
767 sport->port.icount.parity++; in imx_uart_rxint()
768 else if (rx & URXD_FRMERR) in imx_uart_rxint()
769 sport->port.icount.frame++; in imx_uart_rxint()
770 if (rx & URXD_OVRRUN) in imx_uart_rxint()
771 sport->port.icount.overrun++; in imx_uart_rxint()
773 if (rx & sport->port.ignore_status_mask) { in imx_uart_rxint()
779 rx &= (sport->port.read_status_mask | 0xFF); in imx_uart_rxint()
781 if (rx & URXD_BRK) in imx_uart_rxint()
783 else if (rx & URXD_PRERR) in imx_uart_rxint()
785 else if (rx & URXD_FRMERR) in imx_uart_rxint()
787 if (rx & URXD_OVRRUN) in imx_uart_rxint()
791 sport->port.sysrq = 0; in imx_uart_rxint()
795 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in imx_uart_rxint()
798 if (tty_insert_flip_char(port, rx, flg) == 0) in imx_uart_rxint()
799 sport->port.icount.buf_overrun++; in imx_uart_rxint()
803 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_rxint()
813 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) in imx_uart_get_hwmctrl()
815 unsigned int tmp = TIOCM_DSR; in imx_uart_get_hwmctrl()
826 if (sport->dte_mode) in imx_uart_get_hwmctrl()
838 unsigned int status, changed; in imx_uart_mctrl_check()
841 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
846 sport->old_status = status; in imx_uart_mctrl_check()
849 sport->port.icount.rng++; in imx_uart_mctrl_check()
851 sport->port.icount.dsr++; in imx_uart_mctrl_check()
853 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
855 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
857 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
860 static irqreturn_t imx_uart_int(int irq, void *dev_id) in imx_uart_int()
863 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; in imx_uart_int()
876 * actions, for example if a character that sits in the RX FIFO and that in imx_uart_int()
913 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_int()
915 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_int()
931 sport->port.icount.overrun++; in imx_uart_int()
942 static unsigned int imx_uart_tx_empty(struct uart_port *port) in imx_uart_tx_empty()
945 unsigned int ret; in imx_uart_tx_empty()
950 if (sport->dma_is_txing) in imx_uart_tx_empty()
957 static unsigned int imx_uart_get_mctrl(struct uart_port *port) in imx_uart_get_mctrl()
960 unsigned int ret = imx_uart_get_hwmctrl(sport); in imx_uart_get_mctrl()
962 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
968 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) in imx_uart_set_mctrl()
973 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
993 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
999 static void imx_uart_break_ctl(struct uart_port *port, int break_state) in imx_uart_break_ctl()
1005 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1014 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1018 * This is our per-port timeout handler, for checking the
1026 if (sport->port.state) { in imx_uart_timeout()
1027 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1029 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1031 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1038 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1039 * [1] the RX DMA buffer is full.
1048 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1049 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1050 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1052 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1054 unsigned int w_bytes = 0; in imx_uart_dma_rx_callback()
1055 unsigned int r_bytes; in imx_uart_dma_rx_callback()
1056 unsigned int bd_size; in imx_uart_dma_rx_callback()
1058 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1065 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1068 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1071 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1073 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1079 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1082 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1083 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1085 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1086 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1089 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1091 /* CPU claims ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1092 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1096 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1098 /* UART retrieves ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1099 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1103 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1105 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1107 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1108 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1114 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1118 /* RX DMA buffer periods */
1121 static int imx_uart_start_rx_dma(struct imx_port *sport) in imx_uart_start_rx_dma()
1123 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1124 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1125 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1127 int ret; in imx_uart_start_rx_dma()
1129 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1130 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1131 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_start_rx_dma()
1133 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); in imx_uart_start_rx_dma()
1136 dev_err(dev, "DMA mapping error for RX.\n"); in imx_uart_start_rx_dma()
1137 return -EINVAL; in imx_uart_start_rx_dma()
1141 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1146 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); in imx_uart_start_rx_dma()
1147 return -EINVAL; in imx_uart_start_rx_dma()
1149 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1150 desc->callback_param = sport; in imx_uart_start_rx_dma()
1152 dev_dbg(dev, "RX: prepare for the DMA.\n"); in imx_uart_start_rx_dma()
1153 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1154 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1161 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1168 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1170 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1172 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1175 dev_err(sport->port.dev, "DMA transaction error.\n"); in imx_uart_clear_rx_errors()
1177 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1180 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1186 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1200 unsigned int val; in imx_uart_setup_ufcr()
1210 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1211 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1212 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1213 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1214 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1215 kfree(sport->rx_buf); in imx_uart_dma_exit()
1216 sport->rx_buf = NULL; in imx_uart_dma_exit()
1219 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1220 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1221 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1222 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1226 static int imx_uart_dma_init(struct imx_port *sport) in imx_uart_dma_init()
1229 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1230 int ret; in imx_uart_dma_init()
1232 /* Prepare for RX : */ in imx_uart_dma_init()
1233 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1234 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1236 ret = -EINVAL; in imx_uart_dma_init()
1241 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1244 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1245 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1247 dev_err(dev, "error in RX dma configuration.\n"); in imx_uart_dma_init()
1251 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); in imx_uart_dma_init()
1252 if (!sport->rx_buf) { in imx_uart_dma_init()
1253 ret = -ENOMEM; in imx_uart_dma_init()
1256 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1259 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1260 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1262 ret = -EINVAL; in imx_uart_dma_init()
1267 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1270 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1293 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1307 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1310 /* half the RX buffer size */
1313 static int imx_uart_startup(struct uart_port *port) in imx_uart_startup()
1316 int retval, i; in imx_uart_startup()
1318 int dma_is_inited = 0; in imx_uart_startup()
1321 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1324 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1326 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1347 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1355 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_startup()
1366 if (sport->have_rtscts) in imx_uart_startup()
1372 if (!sport->dma_is_enabled) in imx_uart_startup()
1378 if (!sport->have_rtscts) in imx_uart_startup()
1381 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1395 if (sport->dte_mode) in imx_uart_startup()
1405 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1420 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1431 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1432 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1433 if (sport->dma_is_txing) { in imx_uart_shutdown()
1434 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1435 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1436 sport->dma_is_txing = 0; in imx_uart_shutdown()
1438 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1439 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1440 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1442 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1445 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1449 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1453 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1455 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1463 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1468 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1474 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1479 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1481 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1482 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1489 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1491 int i = 100, ubir, ubmr, uts; in imx_uart_flush_buffer()
1493 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1496 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1497 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1498 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1501 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1506 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1514 * and UTS[6-3]". in imx_uart_flush_buffer()
1528 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_flush_buffer()
1544 unsigned int baud, quot; in imx_uart_set_termios()
1545 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1553 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1554 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1555 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1556 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1560 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1565 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1568 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1570 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1575 if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1576 if (sport->have_rtscts) { in imx_uart_set_termios()
1579 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1585 if (port->rs485.flags & in imx_uart_set_termios()
1594 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1596 } else if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1598 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1605 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1607 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1609 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1613 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1614 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1615 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1616 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1617 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1622 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1623 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1624 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1625 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1626 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1631 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1632 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1635 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1636 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1639 * Update the per-port timeout. in imx_uart_set_termios()
1641 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1660 /* custom-baudrate handling */ in imx_uart_set_termios()
1661 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1663 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1665 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1671 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1674 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1680 num -= 1; in imx_uart_set_termios()
1681 denom -= 1; in imx_uart_set_termios()
1691 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1699 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1700 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1702 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1709 return sport->port.type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1715 static void imx_uart_config_port(struct uart_port *port, int flags) in imx_uart_config_port()
1720 sport->port.type = PORT_IMX; in imx_uart_config_port()
1728 static int
1732 int ret = 0; in imx_uart_verify_port()
1734 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1735 ret = -EINVAL; in imx_uart_verify_port()
1736 if (sport->port.irq != ser->irq) in imx_uart_verify_port()
1737 ret = -EINVAL; in imx_uart_verify_port()
1738 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1739 ret = -EINVAL; in imx_uart_verify_port()
1740 if (sport->port.uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1741 ret = -EINVAL; in imx_uart_verify_port()
1742 if (sport->port.mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1743 ret = -EINVAL; in imx_uart_verify_port()
1744 if (sport->port.iobase != ser->port) in imx_uart_verify_port()
1745 ret = -EINVAL; in imx_uart_verify_port()
1746 if (ser->hub6 != 0) in imx_uart_verify_port()
1747 ret = -EINVAL; in imx_uart_verify_port()
1753 static int imx_uart_poll_init(struct uart_port *port) in imx_uart_poll_init()
1758 int retval; in imx_uart_poll_init()
1760 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1763 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1765 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1769 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1774 * This prevents that a character that already sits in the RX fifo is in imx_uart_poll_init()
1797 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1802 static int imx_uart_poll_get_char(struct uart_port *port) in imx_uart_poll_get_char()
1814 unsigned int status; in imx_uart_poll_put_char()
1832 static int imx_uart_rs485_config(struct uart_port *port, in imx_uart_rs485_config()
1839 rs485conf->delay_rts_before_send = 0; in imx_uart_rs485_config()
1840 rs485conf->delay_rts_after_send = 0; in imx_uart_rs485_config()
1843 if (!sport->have_rtscts && !sport->have_rtsgpio) in imx_uart_rs485_config()
1844 rs485conf->flags &= ~SER_RS485_ENABLED; in imx_uart_rs485_config()
1846 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1847 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1848 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1849 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1850 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1854 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1861 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1862 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1863 rs485conf->flags & SER_RS485_RX_DURING_TX) in imx_uart_rs485_config()
1866 port->rs485 = *rs485conf; in imx_uart_rs485_config()
1897 static void imx_uart_console_putchar(struct uart_port *port, int ch) in imx_uart_console_putchar()
1911 imx_uart_console_write(struct console *co, const char *s, unsigned int count) in imx_uart_console_write()
1913 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
1915 unsigned int ucr1; in imx_uart_console_write()
1917 int locked = 1; in imx_uart_console_write()
1918 int retval; in imx_uart_console_write()
1920 retval = clk_enable(sport->clk_per); in imx_uart_console_write()
1923 retval = clk_enable(sport->clk_ipg); in imx_uart_console_write()
1925 clk_disable(sport->clk_per); in imx_uart_console_write()
1929 if (sport->port.sysrq) in imx_uart_console_write()
1932 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
1934 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
1951 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
1962 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
1964 clk_disable(sport->clk_ipg); in imx_uart_console_write()
1965 clk_disable(sport->clk_per); in imx_uart_console_write()
1973 imx_uart_console_get_options(struct imx_port *sport, int *baud, in imx_uart_console_get_options()
1974 int *parity, int *bits) in imx_uart_console_get_options()
1979 unsigned int ucr2, ubir, ubmr, uartclk; in imx_uart_console_get_options()
1980 unsigned int baud_raw; in imx_uart_console_get_options()
1981 unsigned int ucfr_rfdiv; in imx_uart_console_get_options()
2005 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2007 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2016 unsigned int mul = ubir + 1; in imx_uart_console_get_options()
2017 unsigned int div = 16 * (ubmr + 1); in imx_uart_console_get_options()
2018 unsigned int rem = uartclk % div; in imx_uart_console_get_options()
2031 static int __init
2035 int baud = 9600; in imx_uart_console_setup()
2036 int bits = 8; in imx_uart_console_setup()
2037 int parity = 'n'; in imx_uart_console_setup()
2038 int flow = 'n'; in imx_uart_console_setup()
2039 int retval; in imx_uart_console_setup()
2046 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2047 co->index = 0; in imx_uart_console_setup()
2048 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2050 return -ENODEV; in imx_uart_console_setup()
2053 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2064 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2066 clk_disable(sport->clk_ipg); in imx_uart_console_setup()
2068 clk_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2072 retval = clk_prepare(sport->clk_per); in imx_uart_console_setup()
2074 clk_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2087 .index = -1,
2094 static void imx_uart_console_early_putchar(struct uart_port *port, int ch) in imx_uart_console_early_putchar()
2107 struct earlycon_device *dev = con->data; in imx_uart_console_early_write()
2109 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); in imx_uart_console_early_write()
2112 static int __init
2115 if (!dev->port.membase) in imx_console_early_setup()
2116 return -ENODEV; in imx_console_early_setup()
2118 dev->con->write = imx_uart_console_early_write; in imx_console_early_setup()
2122 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2123 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2145 static int imx_uart_probe_dt(struct imx_port *sport, in imx_uart_probe_dt()
2148 struct device_node *np = pdev->dev.of_node; in imx_uart_probe_dt()
2149 int ret; in imx_uart_probe_dt()
2151 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe_dt()
2152 if (!sport->devdata) in imx_uart_probe_dt()
2158 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe_dt()
2161 sport->port.line = ret; in imx_uart_probe_dt()
2163 if (of_get_property(np, "uart-has-rtscts", NULL) || in imx_uart_probe_dt()
2164 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) in imx_uart_probe_dt()
2165 sport->have_rtscts = 1; in imx_uart_probe_dt()
2167 if (of_get_property(np, "fsl,dte-mode", NULL)) in imx_uart_probe_dt()
2168 sport->dte_mode = 1; in imx_uart_probe_dt()
2170 if (of_get_property(np, "rts-gpios", NULL)) in imx_uart_probe_dt()
2171 sport->have_rtsgpio = 1; in imx_uart_probe_dt()
2176 static inline int imx_uart_probe_dt(struct imx_port *sport, in imx_uart_probe_dt()
2186 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); in imx_uart_probe_pdata()
2188 sport->port.line = pdev->id; in imx_uart_probe_pdata()
2189 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; in imx_uart_probe_pdata()
2194 if (pdata->flags & IMXUART_HAVE_RTSCTS) in imx_uart_probe_pdata()
2195 sport->have_rtscts = 1; in imx_uart_probe_pdata()
2198 static int imx_uart_probe(struct platform_device *pdev) in imx_uart_probe()
2202 int ret = 0; in imx_uart_probe()
2205 int txirq, rxirq, rtsirq; in imx_uart_probe()
2207 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2209 return -ENOMEM; in imx_uart_probe()
2217 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2218 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2219 sport->port.line); in imx_uart_probe()
2220 return -EINVAL; in imx_uart_probe()
2224 base = devm_ioremap_resource(&pdev->dev, res); in imx_uart_probe()
2232 sport->port.dev = &pdev->dev; in imx_uart_probe()
2233 sport->port.mapbase = res->start; in imx_uart_probe()
2234 sport->port.membase = base; in imx_uart_probe()
2235 sport->port.type = PORT_IMX, in imx_uart_probe()
2236 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2237 sport->port.irq = rxirq; in imx_uart_probe()
2238 sport->port.fifosize = 32; in imx_uart_probe()
2239 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2240 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2241 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2242 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2244 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2245 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2246 return PTR_ERR(sport->gpios); in imx_uart_probe()
2248 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2249 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2250 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2251 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2255 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2256 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2257 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2258 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2262 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2265 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2267 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); in imx_uart_probe()
2272 sport->ucr1 = readl(sport->port.membase + UCR1); in imx_uart_probe()
2273 sport->ucr2 = readl(sport->port.membase + UCR2); in imx_uart_probe()
2274 sport->ucr3 = readl(sport->port.membase + UCR3); in imx_uart_probe()
2275 sport->ucr4 = readl(sport->port.membase + UCR4); in imx_uart_probe()
2276 sport->ufcr = readl(sport->port.membase + UFCR); in imx_uart_probe()
2278 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); in imx_uart_probe()
2280 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2281 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2282 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); in imx_uart_probe()
2289 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2290 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2291 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2292 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2293 dev_err(&pdev->dev, in imx_uart_probe()
2294 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2296 imx_uart_rs485_config(&sport->port, &sport->port.rs485); in imx_uart_probe()
2304 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2335 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2342 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2343 dev_name(&pdev->dev), sport); in imx_uart_probe()
2345 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2350 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2351 dev_name(&pdev->dev), sport); in imx_uart_probe()
2353 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2358 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2359 dev_name(&pdev->dev), sport); in imx_uart_probe()
2361 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2366 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2367 dev_name(&pdev->dev), sport); in imx_uart_probe()
2369 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2374 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2378 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2381 static int imx_uart_remove(struct platform_device *pdev) in imx_uart_remove()
2385 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2390 if (!sport->context_saved) in imx_uart_restore_context()
2393 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2394 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2395 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2396 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2397 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2398 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2399 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2400 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2401 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2402 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2403 sport->context_saved = false; in imx_uart_restore_context()
2409 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2410 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2411 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2412 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2413 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2414 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2415 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2416 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2417 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2418 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2419 sport->context_saved = true; in imx_uart_save_context()
2435 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2445 static int imx_uart_suspend_noirq(struct device *dev) in imx_uart_suspend_noirq()
2451 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2456 static int imx_uart_resume_noirq(struct device *dev) in imx_uart_resume_noirq()
2459 int ret; in imx_uart_resume_noirq()
2461 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2470 static int imx_uart_suspend(struct device *dev) in imx_uart_suspend()
2473 int ret; in imx_uart_suspend()
2475 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2476 disable_irq(sport->port.irq); in imx_uart_suspend()
2478 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2488 static int imx_uart_resume(struct device *dev) in imx_uart_resume()
2495 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2496 enable_irq(sport->port.irq); in imx_uart_resume()
2498 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2503 static int imx_uart_freeze(struct device *dev) in imx_uart_freeze()
2507 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2509 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2512 static int imx_uart_thaw(struct device *dev) in imx_uart_thaw()
2516 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2518 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2541 .name = "imx-uart",
2547 static int __init imx_uart_init(void) in imx_uart_init()
2549 int ret = uart_register_driver(&imx_uart_uart_driver); in imx_uart_init()
2573 MODULE_ALIAS("platform:imx-uart");