Lines Matching full:pi
315 static void mpsc_start_rx(struct mpsc_port_info *pi);
316 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
325 static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) in mpsc_brg_init() argument
329 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_init()
332 if (pi->brg_can_tune) in mpsc_brg_init()
335 if (pi->mirror_regs) in mpsc_brg_init()
336 pi->BRG_BCR_m = v; in mpsc_brg_init()
337 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_init()
339 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, in mpsc_brg_init()
340 pi->brg_base + BRG_BTR); in mpsc_brg_init()
343 static void mpsc_brg_enable(struct mpsc_port_info *pi) in mpsc_brg_enable() argument
347 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_enable()
350 if (pi->mirror_regs) in mpsc_brg_enable()
351 pi->BRG_BCR_m = v; in mpsc_brg_enable()
352 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_enable()
355 static void mpsc_brg_disable(struct mpsc_port_info *pi) in mpsc_brg_disable() argument
359 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_disable()
362 if (pi->mirror_regs) in mpsc_brg_disable()
363 pi->BRG_BCR_m = v; in mpsc_brg_disable()
364 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_disable()
376 static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) in mpsc_set_baudrate() argument
378 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; in mpsc_set_baudrate()
381 mpsc_brg_disable(pi); in mpsc_set_baudrate()
382 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_set_baudrate()
385 if (pi->mirror_regs) in mpsc_set_baudrate()
386 pi->BRG_BCR_m = v; in mpsc_set_baudrate()
387 writel(v, pi->brg_base + BRG_BCR); in mpsc_set_baudrate()
388 mpsc_brg_enable(pi); in mpsc_set_baudrate()
399 static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size) in mpsc_sdma_burstsize() argument
404 pi->port.line, burst_size); in mpsc_sdma_burstsize()
417 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), in mpsc_sdma_burstsize()
418 pi->sdma_base + SDMA_SDC); in mpsc_sdma_burstsize()
421 static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size) in mpsc_sdma_init() argument
423 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, in mpsc_sdma_init()
426 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, in mpsc_sdma_init()
427 pi->sdma_base + SDMA_SDC); in mpsc_sdma_init()
428 mpsc_sdma_burstsize(pi, burst_size); in mpsc_sdma_init()
431 static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask) in mpsc_sdma_intr_mask() argument
435 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask); in mpsc_sdma_intr_mask()
437 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : in mpsc_sdma_intr_mask()
438 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_mask()
441 if (pi->port.line) in mpsc_sdma_intr_mask()
445 if (pi->mirror_regs) in mpsc_sdma_intr_mask()
446 pi->shared_regs->SDMA_INTR_MASK_m = v; in mpsc_sdma_intr_mask()
447 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_mask()
449 if (pi->port.line) in mpsc_sdma_intr_mask()
454 static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask) in mpsc_sdma_intr_unmask() argument
458 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); in mpsc_sdma_intr_unmask()
460 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m in mpsc_sdma_intr_unmask()
461 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_unmask()
464 if (pi->port.line) in mpsc_sdma_intr_unmask()
468 if (pi->mirror_regs) in mpsc_sdma_intr_unmask()
469 pi->shared_regs->SDMA_INTR_MASK_m = v; in mpsc_sdma_intr_unmask()
470 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_unmask()
473 static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi) in mpsc_sdma_intr_ack() argument
475 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); in mpsc_sdma_intr_ack()
477 if (pi->mirror_regs) in mpsc_sdma_intr_ack()
478 pi->shared_regs->SDMA_INTR_CAUSE_m = 0; in mpsc_sdma_intr_ack()
479 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE in mpsc_sdma_intr_ack()
480 + pi->port.line); in mpsc_sdma_intr_ack()
483 static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, in mpsc_sdma_set_rx_ring() argument
487 pi->port.line, (u32)rxre_p); in mpsc_sdma_set_rx_ring()
489 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); in mpsc_sdma_set_rx_ring()
492 static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, in mpsc_sdma_set_tx_ring() argument
495 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); in mpsc_sdma_set_tx_ring()
496 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); in mpsc_sdma_set_tx_ring()
499 static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val) in mpsc_sdma_cmd() argument
503 v = readl(pi->sdma_base + SDMA_SDCM); in mpsc_sdma_cmd()
509 writel(v, pi->sdma_base + SDMA_SDCM); in mpsc_sdma_cmd()
513 static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi) in mpsc_sdma_tx_active() argument
515 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; in mpsc_sdma_tx_active()
518 static void mpsc_sdma_start_tx(struct mpsc_port_info *pi) in mpsc_sdma_start_tx() argument
523 if (!mpsc_sdma_tx_active(pi)) { in mpsc_sdma_start_tx()
524 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_sdma_start_tx()
525 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_sdma_start_tx()
526 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_sdma_start_tx()
529 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_sdma_start_tx()
536 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_sdma_start_tx()
538 mpsc_sdma_set_tx_ring(pi, txre_p); in mpsc_sdma_start_tx()
539 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); in mpsc_sdma_start_tx()
544 static void mpsc_sdma_stop(struct mpsc_port_info *pi) in mpsc_sdma_stop() argument
546 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); in mpsc_sdma_stop()
549 mpsc_sdma_cmd(pi, 0); in mpsc_sdma_stop()
550 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT); in mpsc_sdma_stop()
553 mpsc_sdma_set_tx_ring(pi, NULL); in mpsc_sdma_stop()
554 mpsc_sdma_set_rx_ring(pi, NULL); in mpsc_sdma_stop()
557 mpsc_sdma_intr_mask(pi, 0xf); in mpsc_sdma_stop()
558 mpsc_sdma_intr_ack(pi); in mpsc_sdma_stop()
569 static void mpsc_hw_init(struct mpsc_port_info *pi) in mpsc_hw_init() argument
573 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line); in mpsc_hw_init()
576 if (pi->mirror_regs) { in mpsc_hw_init()
577 v = pi->shared_regs->MPSC_MRR_m; in mpsc_hw_init()
579 pi->shared_regs->MPSC_MRR_m = v; in mpsc_hw_init()
580 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
582 v = pi->shared_regs->MPSC_RCRR_m; in mpsc_hw_init()
584 pi->shared_regs->MPSC_RCRR_m = v; in mpsc_hw_init()
585 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
587 v = pi->shared_regs->MPSC_TCRR_m; in mpsc_hw_init()
589 pi->shared_regs->MPSC_TCRR_m = v; in mpsc_hw_init()
590 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
592 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
594 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
596 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
598 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
600 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
602 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
606 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL); in mpsc_hw_init()
609 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH); in mpsc_hw_init()
610 mpsc_set_baudrate(pi, pi->default_baud); in mpsc_hw_init()
612 if (pi->mirror_regs) { in mpsc_hw_init()
613 pi->MPSC_CHR_1_m = 0; in mpsc_hw_init()
614 pi->MPSC_CHR_2_m = 0; in mpsc_hw_init()
616 writel(0, pi->mpsc_base + MPSC_CHR_1); in mpsc_hw_init()
617 writel(0, pi->mpsc_base + MPSC_CHR_2); in mpsc_hw_init()
618 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3); in mpsc_hw_init()
619 writel(0, pi->mpsc_base + MPSC_CHR_4); in mpsc_hw_init()
620 writel(0, pi->mpsc_base + MPSC_CHR_5); in mpsc_hw_init()
621 writel(0, pi->mpsc_base + MPSC_CHR_6); in mpsc_hw_init()
622 writel(0, pi->mpsc_base + MPSC_CHR_7); in mpsc_hw_init()
623 writel(0, pi->mpsc_base + MPSC_CHR_8); in mpsc_hw_init()
624 writel(0, pi->mpsc_base + MPSC_CHR_9); in mpsc_hw_init()
625 writel(0, pi->mpsc_base + MPSC_CHR_10); in mpsc_hw_init()
628 static void mpsc_enter_hunt(struct mpsc_port_info *pi) in mpsc_enter_hunt() argument
630 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); in mpsc_enter_hunt()
632 if (pi->mirror_regs) { in mpsc_enter_hunt()
633 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH, in mpsc_enter_hunt()
634 pi->mpsc_base + MPSC_CHR_2); in mpsc_enter_hunt()
638 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, in mpsc_enter_hunt()
639 pi->mpsc_base + MPSC_CHR_2); in mpsc_enter_hunt()
641 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) in mpsc_enter_hunt()
646 static void mpsc_freeze(struct mpsc_port_info *pi) in mpsc_freeze() argument
650 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line); in mpsc_freeze()
652 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_freeze()
653 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_freeze()
656 if (pi->mirror_regs) in mpsc_freeze()
657 pi->MPSC_MPCR_m = v; in mpsc_freeze()
658 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_freeze()
661 static void mpsc_unfreeze(struct mpsc_port_info *pi) in mpsc_unfreeze() argument
665 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_unfreeze()
666 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_unfreeze()
669 if (pi->mirror_regs) in mpsc_unfreeze()
670 pi->MPSC_MPCR_m = v; in mpsc_unfreeze()
671 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_unfreeze()
673 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); in mpsc_unfreeze()
676 static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len) in mpsc_set_char_length() argument
680 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len); in mpsc_set_char_length()
682 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_set_char_length()
683 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_set_char_length()
686 if (pi->mirror_regs) in mpsc_set_char_length()
687 pi->MPSC_MPCR_m = v; in mpsc_set_char_length()
688 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_set_char_length()
691 static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len) in mpsc_set_stop_bit_length() argument
696 pi->port.line, len); in mpsc_set_stop_bit_length()
698 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_set_stop_bit_length()
699 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_set_stop_bit_length()
703 if (pi->mirror_regs) in mpsc_set_stop_bit_length()
704 pi->MPSC_MPCR_m = v; in mpsc_set_stop_bit_length()
705 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_set_stop_bit_length()
708 static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p) in mpsc_set_parity() argument
712 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p); in mpsc_set_parity()
714 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m : in mpsc_set_parity()
715 readl(pi->mpsc_base + MPSC_CHR_2); in mpsc_set_parity()
720 if (pi->mirror_regs) in mpsc_set_parity()
721 pi->MPSC_CHR_2_m = v; in mpsc_set_parity()
722 writel(v, pi->mpsc_base + MPSC_CHR_2); in mpsc_set_parity()
733 static void mpsc_init_hw(struct mpsc_port_info *pi) in mpsc_init_hw() argument
735 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); in mpsc_init_hw()
737 mpsc_brg_init(pi, pi->brg_clk_src); in mpsc_init_hw()
738 mpsc_brg_enable(pi); in mpsc_init_hw()
739 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ in mpsc_init_hw()
740 mpsc_sdma_stop(pi); in mpsc_init_hw()
741 mpsc_hw_init(pi); in mpsc_init_hw()
744 static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi) in mpsc_alloc_ring_mem() argument
749 pi->port.line); in mpsc_alloc_ring_mem()
751 if (!pi->dma_region) { in mpsc_alloc_ring_mem()
752 if (!dma_set_mask(pi->port.dev, 0xffffffff)) { in mpsc_alloc_ring_mem()
755 } else if ((pi->dma_region = dma_alloc_attrs(pi->port.dev, in mpsc_alloc_ring_mem()
757 &pi->dma_region_p, GFP_KERNEL, in mpsc_alloc_ring_mem()
768 static void mpsc_free_ring_mem(struct mpsc_port_info *pi) in mpsc_free_ring_mem() argument
770 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); in mpsc_free_ring_mem()
772 if (pi->dma_region) { in mpsc_free_ring_mem()
773 dma_free_attrs(pi->port.dev, MPSC_DMA_ALLOC_SIZE, in mpsc_free_ring_mem()
774 pi->dma_region, pi->dma_region_p, in mpsc_free_ring_mem()
776 pi->dma_region = NULL; in mpsc_free_ring_mem()
777 pi->dma_region_p = (dma_addr_t)NULL; in mpsc_free_ring_mem()
781 static void mpsc_init_rings(struct mpsc_port_info *pi) in mpsc_init_rings() argument
789 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line); in mpsc_init_rings()
791 BUG_ON(pi->dma_region == NULL); in mpsc_init_rings()
793 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE); in mpsc_init_rings()
799 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment()); in mpsc_init_rings()
800 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment()); in mpsc_init_rings()
806 pi->rxr = dp; in mpsc_init_rings()
807 pi->rxr_p = dp_p; in mpsc_init_rings()
811 pi->rxb = (u8 *)dp; in mpsc_init_rings()
812 pi->rxb_p = (u8 *)dp_p; in mpsc_init_rings()
816 pi->rxr_posn = 0; in mpsc_init_rings()
818 pi->txr = dp; in mpsc_init_rings()
819 pi->txr_p = dp_p; in mpsc_init_rings()
823 pi->txb = (u8 *)dp; in mpsc_init_rings()
824 pi->txb_p = (u8 *)dp_p; in mpsc_init_rings()
826 pi->txr_head = 0; in mpsc_init_rings()
827 pi->txr_tail = 0; in mpsc_init_rings()
830 dp = pi->rxr; in mpsc_init_rings()
831 dp_p = pi->rxr_p; in mpsc_init_rings()
832 bp = pi->rxb; in mpsc_init_rings()
833 bp_p = pi->rxb_p; in mpsc_init_rings()
851 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */ in mpsc_init_rings()
854 dp = pi->txr; in mpsc_init_rings()
855 dp_p = pi->txr_p; in mpsc_init_rings()
856 bp = pi->txb; in mpsc_init_rings()
857 bp_p = pi->txb_p; in mpsc_init_rings()
870 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ in mpsc_init_rings()
872 dma_cache_sync(pi->port.dev, (void *)pi->dma_region, in mpsc_init_rings()
875 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_init_rings()
876 flush_dcache_range((ulong)pi->dma_region, in mpsc_init_rings()
877 (ulong)pi->dma_region in mpsc_init_rings()
884 static void mpsc_uninit_rings(struct mpsc_port_info *pi) in mpsc_uninit_rings() argument
886 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); in mpsc_uninit_rings()
888 BUG_ON(pi->dma_region == NULL); in mpsc_uninit_rings()
890 pi->rxr = 0; in mpsc_uninit_rings()
891 pi->rxr_p = 0; in mpsc_uninit_rings()
892 pi->rxb = NULL; in mpsc_uninit_rings()
893 pi->rxb_p = NULL; in mpsc_uninit_rings()
894 pi->rxr_posn = 0; in mpsc_uninit_rings()
896 pi->txr = 0; in mpsc_uninit_rings()
897 pi->txr_p = 0; in mpsc_uninit_rings()
898 pi->txb = NULL; in mpsc_uninit_rings()
899 pi->txb_p = NULL; in mpsc_uninit_rings()
900 pi->txr_head = 0; in mpsc_uninit_rings()
901 pi->txr_tail = 0; in mpsc_uninit_rings()
904 static int mpsc_make_ready(struct mpsc_port_info *pi) in mpsc_make_ready() argument
908 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line); in mpsc_make_ready()
910 if (!pi->ready) { in mpsc_make_ready()
911 mpsc_init_hw(pi); in mpsc_make_ready()
912 rc = mpsc_alloc_ring_mem(pi); in mpsc_make_ready()
915 mpsc_init_rings(pi); in mpsc_make_ready()
916 pi->ready = 1; in mpsc_make_ready()
934 static int mpsc_rx_intr(struct mpsc_port_info *pi, unsigned long *flags) in mpsc_rx_intr() argument
937 struct tty_port *port = &pi->port.state->port; in mpsc_rx_intr()
943 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); in mpsc_rx_intr()
945 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); in mpsc_rx_intr()
947 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
950 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
970 spin_unlock_irqrestore(&pi->port.lock, *flags); in mpsc_rx_intr()
972 spin_lock_irqsave(&pi->port.lock, *flags); in mpsc_rx_intr()
980 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); in mpsc_rx_intr()
981 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE, in mpsc_rx_intr()
984 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1001 pi->port.icount.rx++; in mpsc_rx_intr()
1004 pi->port.icount.brk++; in mpsc_rx_intr()
1006 if (uart_handle_break(&pi->port)) in mpsc_rx_intr()
1009 pi->port.icount.frame++; in mpsc_rx_intr()
1011 pi->port.icount.overrun++; in mpsc_rx_intr()
1014 cmdstat &= pi->port.read_status_mask; in mpsc_rx_intr()
1026 if (uart_handle_sysrq_char(&pi->port, *bp)) { in mpsc_rx_intr()
1041 && !(cmdstat & pi->port.ignore_status_mask)) { in mpsc_rx_intr()
1047 pi->port.icount.rx += bytes_in; in mpsc_rx_intr()
1057 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
1060 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1066 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); in mpsc_rx_intr()
1068 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE)); in mpsc_rx_intr()
1069 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
1072 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1080 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) in mpsc_rx_intr()
1081 mpsc_start_rx(pi); in mpsc_rx_intr()
1083 spin_unlock_irqrestore(&pi->port.lock, *flags); in mpsc_rx_intr()
1085 spin_lock_irqsave(&pi->port.lock, *flags); in mpsc_rx_intr()
1089 static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr) in mpsc_setup_tx_desc() argument
1093 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_setup_tx_desc()
1094 + (pi->txr_head * MPSC_TXRE_SIZE)); in mpsc_setup_tx_desc()
1103 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_setup_tx_desc()
1106 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_setup_tx_desc()
1112 static void mpsc_copy_tx_data(struct mpsc_port_info *pi) in mpsc_copy_tx_data() argument
1114 struct circ_buf *xmit = &pi->port.state->xmit; in mpsc_copy_tx_data()
1119 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) in mpsc_copy_tx_data()
1121 if (pi->port.x_char) { in mpsc_copy_tx_data()
1130 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_copy_tx_data()
1131 *bp = pi->port.x_char; in mpsc_copy_tx_data()
1132 pi->port.x_char = 0; in mpsc_copy_tx_data()
1135 && !uart_tx_stopped(&pi->port)) { in mpsc_copy_tx_data()
1140 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_copy_tx_data()
1145 uart_write_wakeup(&pi->port); in mpsc_copy_tx_data()
1150 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE, in mpsc_copy_tx_data()
1153 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_copy_tx_data()
1157 mpsc_setup_tx_desc(pi, i, 1); in mpsc_copy_tx_data()
1160 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_copy_tx_data()
1164 static int mpsc_tx_intr(struct mpsc_port_info *pi) in mpsc_tx_intr() argument
1170 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_tx_intr()
1172 if (!mpsc_sdma_tx_active(pi)) { in mpsc_tx_intr()
1173 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_tx_intr()
1174 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_tx_intr()
1176 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_tx_intr()
1179 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_tx_intr()
1186 pi->port.icount.tx += be16_to_cpu(txre->bytecnt); in mpsc_tx_intr()
1187 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1); in mpsc_tx_intr()
1190 if (pi->txr_head == pi->txr_tail) in mpsc_tx_intr()
1193 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_tx_intr()
1194 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_tx_intr()
1195 dma_cache_sync(pi->port.dev, (void *)txre, in mpsc_tx_intr()
1198 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_tx_intr()
1204 mpsc_copy_tx_data(pi); in mpsc_tx_intr()
1205 mpsc_sdma_start_tx(pi); /* start next desc if ready */ in mpsc_tx_intr()
1208 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_tx_intr()
1219 struct mpsc_port_info *pi = dev_id; in mpsc_sdma_intr() local
1223 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line); in mpsc_sdma_intr()
1225 spin_lock_irqsave(&pi->port.lock, iflags); in mpsc_sdma_intr()
1226 mpsc_sdma_intr_ack(pi); in mpsc_sdma_intr()
1227 if (mpsc_rx_intr(pi, &iflags)) in mpsc_sdma_intr()
1229 if (mpsc_tx_intr(pi)) in mpsc_sdma_intr()
1231 spin_unlock_irqrestore(&pi->port.lock, iflags); in mpsc_sdma_intr()
1233 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line); in mpsc_sdma_intr()
1246 struct mpsc_port_info *pi = in mpsc_tx_empty() local
1251 spin_lock_irqsave(&pi->port.lock, iflags); in mpsc_tx_empty()
1252 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT; in mpsc_tx_empty()
1253 spin_unlock_irqrestore(&pi->port.lock, iflags); in mpsc_tx_empty()
1265 struct mpsc_port_info *pi = in mpsc_get_mctrl() local
1269 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m in mpsc_get_mctrl()
1270 : readl(pi->mpsc_base + MPSC_CHR_10); in mpsc_get_mctrl()
1283 struct mpsc_port_info *pi = in mpsc_stop_tx() local
1288 mpsc_freeze(pi); in mpsc_stop_tx()
1293 struct mpsc_port_info *pi = in mpsc_start_tx() local
1297 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_start_tx()
1299 mpsc_unfreeze(pi); in mpsc_start_tx()
1300 mpsc_copy_tx_data(pi); in mpsc_start_tx()
1301 mpsc_sdma_start_tx(pi); in mpsc_start_tx()
1303 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_start_tx()
1308 static void mpsc_start_rx(struct mpsc_port_info *pi) in mpsc_start_rx() argument
1310 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); in mpsc_start_rx()
1312 if (pi->rcv_data) { in mpsc_start_rx()
1313 mpsc_enter_hunt(pi); in mpsc_start_rx()
1314 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); in mpsc_start_rx()
1320 struct mpsc_port_info *pi = in mpsc_stop_rx() local
1325 if (pi->mirror_regs) { in mpsc_stop_rx()
1326 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA, in mpsc_stop_rx()
1327 pi->mpsc_base + MPSC_CHR_2); in mpsc_stop_rx()
1331 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA, in mpsc_stop_rx()
1332 pi->mpsc_base + MPSC_CHR_2); in mpsc_stop_rx()
1334 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA) in mpsc_stop_rx()
1338 mpsc_sdma_cmd(pi, SDMA_SDCM_AR); in mpsc_stop_rx()
1343 struct mpsc_port_info *pi = in mpsc_break_ctl() local
1350 spin_lock_irqsave(&pi->port.lock, flags); in mpsc_break_ctl()
1351 if (pi->mirror_regs) in mpsc_break_ctl()
1352 pi->MPSC_CHR_1_m = v; in mpsc_break_ctl()
1353 writel(v, pi->mpsc_base + MPSC_CHR_1); in mpsc_break_ctl()
1354 spin_unlock_irqrestore(&pi->port.lock, flags); in mpsc_break_ctl()
1359 struct mpsc_port_info *pi = in mpsc_startup() local
1365 port->line, pi->port.irq); in mpsc_startup()
1367 if ((rc = mpsc_make_ready(pi)) == 0) { in mpsc_startup()
1369 mpsc_sdma_intr_ack(pi); in mpsc_startup()
1375 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, in mpsc_startup()
1376 "mpsc-sdma", pi)) in mpsc_startup()
1378 pi->port.irq); in mpsc_startup()
1380 mpsc_sdma_intr_unmask(pi, 0xf); in mpsc_startup()
1381 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p in mpsc_startup()
1382 + (pi->rxr_posn * MPSC_RXRE_SIZE))); in mpsc_startup()
1390 struct mpsc_port_info *pi = in mpsc_shutdown() local
1395 mpsc_sdma_stop(pi); in mpsc_shutdown()
1396 free_irq(pi->port.irq, pi); in mpsc_shutdown()
1402 struct mpsc_port_info *pi = in mpsc_set_termios() local
1444 spin_lock_irqsave(&pi->port.lock, flags); in mpsc_set_termios()
1448 mpsc_set_char_length(pi, chr_bits); in mpsc_set_termios()
1449 mpsc_set_stop_bit_length(pi, stop_bits); in mpsc_set_termios()
1450 mpsc_set_parity(pi, par); in mpsc_set_termios()
1451 mpsc_set_baudrate(pi, baud); in mpsc_set_termios()
1454 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; in mpsc_set_termios()
1457 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE in mpsc_set_termios()
1461 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; in mpsc_set_termios()
1464 pi->port.ignore_status_mask = 0; in mpsc_set_termios()
1467 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE in mpsc_set_termios()
1471 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; in mpsc_set_termios()
1474 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR; in mpsc_set_termios()
1478 if (!pi->rcv_data) { in mpsc_set_termios()
1479 pi->rcv_data = 1; in mpsc_set_termios()
1480 mpsc_start_rx(pi); in mpsc_set_termios()
1482 } else if (pi->rcv_data) { in mpsc_set_termios()
1484 pi->rcv_data = 0; in mpsc_set_termios()
1487 spin_unlock_irqrestore(&pi->port.lock, flags); in mpsc_set_termios()
1504 struct mpsc_port_info *pi = in mpsc_release_port() local
1507 if (pi->ready) { in mpsc_release_port()
1508 mpsc_uninit_rings(pi); in mpsc_release_port()
1509 mpsc_free_ring_mem(pi); in mpsc_release_port()
1510 pi->ready = 0; in mpsc_release_port()
1520 struct mpsc_port_info *pi = in mpsc_verify_port() local
1524 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line); in mpsc_verify_port()
1528 else if (pi->port.irq != ser->irq) in mpsc_verify_port()
1532 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */ in mpsc_verify_port()
1534 else if ((void *)pi->port.mapbase != ser->iomem_base) in mpsc_verify_port()
1536 else if (pi->port.iobase != ser->port) in mpsc_verify_port()
1556 struct mpsc_port_info *pi = in mpsc_get_poll_char() local
1565 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); in mpsc_get_poll_char()
1575 rxre = (struct mpsc_rx_desc *)(pi->rxr + in mpsc_get_poll_char()
1576 (pi->rxr_posn*MPSC_RXRE_SIZE)); in mpsc_get_poll_char()
1577 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1580 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1592 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); in mpsc_get_poll_char()
1593 dma_cache_sync(pi->port.dev, (void *) bp, in mpsc_get_poll_char()
1596 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1602 !(cmdstat & pi->port.ignore_status_mask)) { in mpsc_get_poll_char()
1610 pi->port.icount.rx += bytes_in; in mpsc_get_poll_char()
1619 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1622 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1628 pi->rxr_posn = (pi->rxr_posn + 1) & in mpsc_get_poll_char()
1630 rxre = (struct mpsc_rx_desc *)(pi->rxr + in mpsc_get_poll_char()
1631 (pi->rxr_posn * MPSC_RXRE_SIZE)); in mpsc_get_poll_char()
1632 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1635 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1642 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) in mpsc_get_poll_char()
1643 mpsc_start_rx(pi); in mpsc_get_poll_char()
1657 struct mpsc_port_info *pi = in mpsc_put_poll_char() local
1661 data = readl(pi->mpsc_base + MPSC_MPCR); in mpsc_put_poll_char()
1662 writeb(c, pi->mpsc_base + MPSC_CHR_1); in mpsc_put_poll_char()
1664 data = readl(pi->mpsc_base + MPSC_CHR_2); in mpsc_put_poll_char()
1666 writel(data, pi->mpsc_base + MPSC_CHR_2); in mpsc_put_poll_char()
1669 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS); in mpsc_put_poll_char()
1706 struct mpsc_port_info *pi = &mpsc_ports[co->index]; in mpsc_console_write() local
1711 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_console_write()
1713 while (pi->txr_head != pi->txr_tail) { in mpsc_console_write()
1714 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1716 mpsc_sdma_intr_ack(pi); in mpsc_console_write()
1717 mpsc_tx_intr(pi); in mpsc_console_write()
1720 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1724 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_console_write()
1745 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE, in mpsc_console_write()
1748 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_console_write()
1752 mpsc_setup_tx_desc(pi, i, 0); in mpsc_console_write()
1753 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_console_write()
1754 mpsc_sdma_start_tx(pi); in mpsc_console_write()
1756 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1759 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_console_write()
1762 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_console_write()
1767 struct mpsc_port_info *pi; in mpsc_console_setup() local
1775 pi = &mpsc_ports[co->index]; in mpsc_console_setup()
1777 baud = pi->default_baud; in mpsc_console_setup()
1778 bits = pi->default_bits; in mpsc_console_setup()
1779 parity = pi->default_parity; in mpsc_console_setup()
1780 flow = pi->default_flow; in mpsc_console_setup()
1782 if (!pi->port.ops) in mpsc_console_setup()
1785 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */ in mpsc_console_setup()
1790 return uart_set_options(&pi->port, co, baud, parity, bits, flow); in mpsc_console_setup()
1949 static int mpsc_drv_map_regs(struct mpsc_port_info *pi, in mpsc_drv_map_regs() argument
1957 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1958 pi->mpsc_base_p = r->start; in mpsc_drv_map_regs()
1968 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1969 pi->sdma_base_p = r->start; in mpsc_drv_map_regs()
1978 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1979 pi->brg_base_p = r->start; in mpsc_drv_map_regs()
1987 if (pi->sdma_base) { in mpsc_drv_map_regs()
1988 iounmap(pi->sdma_base); in mpsc_drv_map_regs()
1989 pi->sdma_base = NULL; in mpsc_drv_map_regs()
1991 if (pi->mpsc_base) { in mpsc_drv_map_regs()
1992 iounmap(pi->mpsc_base); in mpsc_drv_map_regs()
1993 pi->mpsc_base = NULL; in mpsc_drv_map_regs()
1998 static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi) in mpsc_drv_unmap_regs() argument
2000 if (pi->mpsc_base) { in mpsc_drv_unmap_regs()
2001 iounmap(pi->mpsc_base); in mpsc_drv_unmap_regs()
2002 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2004 if (pi->sdma_base) { in mpsc_drv_unmap_regs()
2005 iounmap(pi->sdma_base); in mpsc_drv_unmap_regs()
2006 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2008 if (pi->brg_base) { in mpsc_drv_unmap_regs()
2009 iounmap(pi->brg_base); in mpsc_drv_unmap_regs()
2010 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2013 pi->mpsc_base = NULL; in mpsc_drv_unmap_regs()
2014 pi->sdma_base = NULL; in mpsc_drv_unmap_regs()
2015 pi->brg_base = NULL; in mpsc_drv_unmap_regs()
2017 pi->mpsc_base_p = 0; in mpsc_drv_unmap_regs()
2018 pi->sdma_base_p = 0; in mpsc_drv_unmap_regs()
2019 pi->brg_base_p = 0; in mpsc_drv_unmap_regs()
2022 static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi, in mpsc_drv_get_platform_data() argument
2029 pi->port.uartclk = pdata->brg_clk_freq; in mpsc_drv_get_platform_data()
2030 pi->port.iotype = UPIO_MEM; in mpsc_drv_get_platform_data()
2031 pi->port.line = num; in mpsc_drv_get_platform_data()
2032 pi->port.type = PORT_MPSC; in mpsc_drv_get_platform_data()
2033 pi->port.fifosize = MPSC_TXBE_SIZE; in mpsc_drv_get_platform_data()
2034 pi->port.membase = pi->mpsc_base; in mpsc_drv_get_platform_data()
2035 pi->port.mapbase = (ulong)pi->mpsc_base; in mpsc_drv_get_platform_data()
2036 pi->port.ops = &mpsc_pops; in mpsc_drv_get_platform_data()
2038 pi->mirror_regs = pdata->mirror_regs; in mpsc_drv_get_platform_data()
2039 pi->cache_mgmt = pdata->cache_mgmt; in mpsc_drv_get_platform_data()
2040 pi->brg_can_tune = pdata->brg_can_tune; in mpsc_drv_get_platform_data()
2041 pi->brg_clk_src = pdata->brg_clk_src; in mpsc_drv_get_platform_data()
2042 pi->mpsc_max_idle = pdata->max_idle; in mpsc_drv_get_platform_data()
2043 pi->default_baud = pdata->default_baud; in mpsc_drv_get_platform_data()
2044 pi->default_bits = pdata->default_bits; in mpsc_drv_get_platform_data()
2045 pi->default_parity = pdata->default_parity; in mpsc_drv_get_platform_data()
2046 pi->default_flow = pdata->default_flow; in mpsc_drv_get_platform_data()
2049 pi->MPSC_CHR_1_m = pdata->chr_1_val; in mpsc_drv_get_platform_data()
2050 pi->MPSC_CHR_2_m = pdata->chr_2_val; in mpsc_drv_get_platform_data()
2051 pi->MPSC_CHR_10_m = pdata->chr_10_val; in mpsc_drv_get_platform_data()
2052 pi->MPSC_MPCR_m = pdata->mpcr_val; in mpsc_drv_get_platform_data()
2053 pi->BRG_BCR_m = pdata->bcr_val; in mpsc_drv_get_platform_data()
2055 pi->shared_regs = &mpsc_shared_regs; in mpsc_drv_get_platform_data()
2057 pi->port.irq = platform_get_irq(pd, 0); in mpsc_drv_get_platform_data()
2062 struct mpsc_port_info *pi; in mpsc_drv_probe() local
2070 pi = &mpsc_ports[dev->id]; in mpsc_drv_probe()
2072 rc = mpsc_drv_map_regs(pi, dev); in mpsc_drv_probe()
2076 mpsc_drv_get_platform_data(pi, dev, dev->id); in mpsc_drv_probe()
2077 pi->port.dev = &dev->dev; in mpsc_drv_probe()
2079 rc = mpsc_make_ready(pi); in mpsc_drv_probe()
2083 spin_lock_init(&pi->tx_lock); in mpsc_drv_probe()
2084 rc = uart_add_one_port(&mpsc_reg, &pi->port); in mpsc_drv_probe()
2090 mpsc_release_port(&pi->port); in mpsc_drv_probe()
2092 mpsc_drv_unmap_regs(pi); in mpsc_drv_probe()