Lines Matching +full:stm32 +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 * Inspired by st-asc.c from STMicroelectronics (c)
18 #include <linux/dma-direction.h>
20 #include <linux/dma-mapping.h>
37 #include "stm32-usart.h"
51 val = readl_relaxed(port->membase + reg); in stm32_set_bits()
53 writel_relaxed(val, port->membase + reg); in stm32_set_bits()
60 val = readl_relaxed(port->membase + reg); in stm32_clr_bits()
62 writel_relaxed(val, port->membase + reg); in stm32_clr_bits()
104 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_config_rs485()
105 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_config_rs485()
109 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_config_rs485()
111 port->rs485 = *rs485conf; in stm32_config_rs485()
113 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_config_rs485()
115 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_config_rs485()
116 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_config_rs485()
117 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_config_rs485()
118 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_config_rs485()
126 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_config_rs485()
128 rs485conf->delay_rts_before_send, in stm32_config_rs485()
129 rs485conf->delay_rts_after_send, baud); in stm32_config_rs485()
131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_config_rs485()
133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_config_rs485()
136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_config_rs485()
139 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_config_rs485()
140 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_config_rs485()
142 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP); in stm32_config_rs485()
143 stm32_clr_bits(port, ofs->cr1, in stm32_config_rs485()
147 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_config_rs485()
155 struct serial_rs485 *rs485conf = &port->rs485; in stm32_init_rs485()
157 rs485conf->flags = 0; in stm32_init_rs485()
158 rs485conf->delay_rts_before_send = 0; in stm32_init_rs485()
159 rs485conf->delay_rts_after_send = 0; in stm32_init_rs485()
161 if (!pdev->dev.of_node) in stm32_init_rs485()
162 return -ENODEV; in stm32_init_rs485()
164 uart_get_rs485_mode(&pdev->dev, rs485conf); in stm32_init_rs485()
173 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_pending_rx()
177 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_pending_rx()
179 if (threaded && stm32_port->rx_ch) { in stm32_pending_rx()
180 status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_pending_rx()
181 stm32_port->rx_ch->cookie, in stm32_pending_rx()
198 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_get_char()
201 if (stm32_port->rx_ch) { in stm32_get_char()
202 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; in stm32_get_char()
206 c = readl_relaxed(port->membase + ofs->rdr); in stm32_get_char()
208 c &= stm32_port->rdr_mask; in stm32_get_char()
216 struct tty_port *tport = &port->state->port; in stm32_receive_chars()
218 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_receive_chars()
223 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_receive_chars()
224 pm_wakeup_event(tport->tty->dev, 0); in stm32_receive_chars()
226 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { in stm32_receive_chars()
239 * cleared by the sequence [read SR - read DR]. in stm32_receive_chars()
241 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_receive_chars()
243 port->membase + ofs->icr); in stm32_receive_chars()
245 c = stm32_get_char(port, &sr, &stm32_port->last_res); in stm32_receive_chars()
246 port->icount.rx++; in stm32_receive_chars()
249 port->icount.overrun++; in stm32_receive_chars()
251 port->icount.parity++; in stm32_receive_chars()
255 port->icount.brk++; in stm32_receive_chars()
259 port->icount.frame++; in stm32_receive_chars()
263 sr &= port->read_status_mask; in stm32_receive_chars()
280 spin_unlock(&port->lock); in stm32_receive_chars()
282 spin_lock(&port->lock); in stm32_receive_chars()
289 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_tx_dma_complete()
291 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_tx_dma_complete()
292 stm32port->tx_dma_busy = false; in stm32_tx_dma_complete()
301 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_transmit_chars_pio()
302 struct circ_buf *xmit = &port->state->xmit; in stm32_transmit_chars_pio()
306 if (stm32_port->tx_dma_busy) { in stm32_transmit_chars_pio()
307 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_transmit_chars_pio()
308 stm32_port->tx_dma_busy = false; in stm32_transmit_chars_pio()
311 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_transmit_chars_pio()
317 dev_err(port->dev, "tx empty not set\n"); in stm32_transmit_chars_pio()
319 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_transmit_chars_pio()
321 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_transmit_chars_pio()
322 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in stm32_transmit_chars_pio()
323 port->icount.tx++; in stm32_transmit_chars_pio()
329 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_transmit_chars_dma()
330 struct circ_buf *xmit = &port->state->xmit; in stm32_transmit_chars_dma()
335 if (stm32port->tx_dma_busy) in stm32_transmit_chars_dma()
338 stm32port->tx_dma_busy = true; in stm32_transmit_chars_dma()
345 if (xmit->tail < xmit->head) { in stm32_transmit_chars_dma()
346 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_transmit_chars_dma()
348 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_transmit_chars_dma()
353 two = count - one; in stm32_transmit_chars_dma()
355 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_transmit_chars_dma()
357 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_transmit_chars_dma()
360 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_transmit_chars_dma()
361 stm32port->tx_dma_buf, in stm32_transmit_chars_dma()
367 for (i = count; i > 0; i--) in stm32_transmit_chars_dma()
372 desc->callback = stm32_tx_dma_complete; in stm32_transmit_chars_dma()
373 desc->callback_param = port; in stm32_transmit_chars_dma()
379 dma_async_issue_pending(stm32port->tx_ch); in stm32_transmit_chars_dma()
381 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_transmit_chars_dma()
383 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in stm32_transmit_chars_dma()
384 port->icount.tx += count; in stm32_transmit_chars_dma()
390 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_transmit_chars()
391 struct circ_buf *xmit = &port->state->xmit; in stm32_transmit_chars()
393 if (port->x_char) { in stm32_transmit_chars()
394 if (stm32_port->tx_dma_busy) in stm32_transmit_chars()
395 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_transmit_chars()
396 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_transmit_chars()
397 port->x_char = 0; in stm32_transmit_chars()
398 port->icount.tx++; in stm32_transmit_chars()
399 if (stm32_port->tx_dma_busy) in stm32_transmit_chars()
400 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_transmit_chars()
405 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_transmit_chars()
409 if (ofs->icr == UNDEF_REG) in stm32_transmit_chars()
410 stm32_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_transmit_chars()
412 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_transmit_chars()
414 if (stm32_port->tx_ch) in stm32_transmit_chars()
423 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_transmit_chars()
430 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_interrupt()
433 spin_lock(&port->lock); in stm32_interrupt()
435 sr = readl_relaxed(port->membase + ofs->isr); in stm32_interrupt()
437 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) in stm32_interrupt()
439 port->membase + ofs->icr); in stm32_interrupt()
441 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) in stm32_interrupt()
444 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) in stm32_interrupt()
447 spin_unlock(&port->lock); in stm32_interrupt()
449 if (stm32_port->rx_ch) in stm32_interrupt()
460 spin_lock(&port->lock); in stm32_threaded_interrupt()
462 if (stm32_port->rx_ch) in stm32_threaded_interrupt()
465 spin_unlock(&port->lock); in stm32_threaded_interrupt()
473 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_tx_empty()
475 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; in stm32_tx_empty()
481 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_set_mctrl()
483 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_set_mctrl()
484 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_set_mctrl()
486 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_set_mctrl()
499 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_stop_tx()
501 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_stop_tx()
507 struct circ_buf *xmit = &port->state->xmit; in stm32_start_tx()
519 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_throttle()
522 spin_lock_irqsave(&port->lock, flags); in stm32_throttle()
523 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); in stm32_throttle()
524 spin_unlock_irqrestore(&port->lock, flags); in stm32_throttle()
531 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_unthrottle()
534 spin_lock_irqsave(&port->lock, flags); in stm32_unthrottle()
535 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); in stm32_unthrottle()
536 spin_unlock_irqrestore(&port->lock, flags); in stm32_unthrottle()
543 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_stop_rx()
545 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); in stm32_stop_rx()
548 /* Handle breaks - ignored by us */
556 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_startup()
557 const char *name = to_platform_device(port->dev)->name; in stm32_startup()
561 ret = request_threaded_irq(port->irq, stm32_interrupt, in stm32_startup()
568 if (stm32_port->fifoen) in stm32_startup()
570 stm32_set_bits(port, ofs->cr1, val); in stm32_startup()
578 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_shutdown()
579 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_shutdown()
584 val |= BIT(cfg->uart_enable_bit); in stm32_shutdown()
585 if (stm32_port->fifoen) in stm32_shutdown()
588 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_shutdown()
593 dev_err(port->dev, "transmission complete not set\n"); in stm32_shutdown()
595 stm32_clr_bits(port, ofs->cr1, val); in stm32_shutdown()
597 free_irq(port->irq, port); in stm32_shutdown()
604 tcflag_t cflag = termios->c_cflag; in stm32_get_databits()
634 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_set_termios()
635 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_set_termios()
636 struct serial_rs485 *rs485conf = &port->rs485; in stm32_set_termios()
639 tcflag_t cflag = termios->c_cflag; in stm32_set_termios()
643 if (!stm32_port->hw_flow_control) in stm32_set_termios()
646 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_set_termios()
648 spin_lock_irqsave(&port->lock, flags); in stm32_set_termios()
651 writel_relaxed(0, port->membase + ofs->cr1); in stm32_set_termios()
655 if (stm32_port->fifoen) in stm32_set_termios()
664 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_set_termios()
680 else if ((bits == 7) && cfg->has_7bits_data) in stm32_set_termios()
683 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_set_termios()
689 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_set_termios()
691 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_set_termios()
695 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_set_termios()
706 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_set_termios()
710 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_set_termios()
715 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_set_termios()
719 port->read_status_mask = USART_SR_ORE; in stm32_set_termios()
720 if (termios->c_iflag & INPCK) in stm32_set_termios()
721 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_set_termios()
722 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_set_termios()
723 port->read_status_mask |= USART_SR_FE; in stm32_set_termios()
726 port->ignore_status_mask = 0; in stm32_set_termios()
727 if (termios->c_iflag & IGNPAR) in stm32_set_termios()
728 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_set_termios()
729 if (termios->c_iflag & IGNBRK) { in stm32_set_termios()
730 port->ignore_status_mask |= USART_SR_FE; in stm32_set_termios()
735 if (termios->c_iflag & IGNPAR) in stm32_set_termios()
736 port->ignore_status_mask |= USART_SR_ORE; in stm32_set_termios()
740 if ((termios->c_cflag & CREAD) == 0) in stm32_set_termios()
741 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_set_termios()
743 if (stm32_port->rx_ch) in stm32_set_termios()
746 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_set_termios()
748 rs485conf->delay_rts_before_send, in stm32_set_termios()
749 rs485conf->delay_rts_after_send, baud); in stm32_set_termios()
750 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_set_termios()
752 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_set_termios()
755 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_set_termios()
763 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_set_termios()
764 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_set_termios()
765 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_set_termios()
767 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_set_termios()
768 spin_unlock_irqrestore(&port->lock, flags); in stm32_set_termios()
773 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_type()
788 port->type = PORT_STM32; in stm32_config_port()
795 return -EINVAL; in stm32_verify_port()
803 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_pm()
804 struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_pm()
809 clk_prepare_enable(stm32port->clk); in stm32_pm()
812 spin_lock_irqsave(&port->lock, flags); in stm32_pm()
813 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_pm()
814 spin_unlock_irqrestore(&port->lock, flags); in stm32_pm()
815 clk_disable_unprepare(stm32port->clk); in stm32_pm()
844 struct uart_port *port = &stm32port->port; in stm32_init_port()
848 port->iotype = UPIO_MEM; in stm32_init_port()
849 port->flags = UPF_BOOT_AUTOCONF; in stm32_init_port()
850 port->ops = &stm32_uart_ops; in stm32_init_port()
851 port->dev = &pdev->dev; in stm32_init_port()
852 port->irq = platform_get_irq(pdev, 0); in stm32_init_port()
853 port->rs485_config = stm32_config_rs485; in stm32_init_port()
857 stm32port->wakeirq = platform_get_irq(pdev, 1); in stm32_init_port()
858 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_init_port()
861 port->membase = devm_ioremap_resource(&pdev->dev, res); in stm32_init_port()
862 if (IS_ERR(port->membase)) in stm32_init_port()
863 return PTR_ERR(port->membase); in stm32_init_port()
864 port->mapbase = res->start; in stm32_init_port()
866 spin_lock_init(&port->lock); in stm32_init_port()
868 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_init_port()
869 if (IS_ERR(stm32port->clk)) in stm32_init_port()
870 return PTR_ERR(stm32port->clk); in stm32_init_port()
873 ret = clk_prepare_enable(stm32port->clk); in stm32_init_port()
877 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_init_port()
878 if (!stm32port->port.uartclk) { in stm32_init_port()
879 clk_disable_unprepare(stm32port->clk); in stm32_init_port()
880 ret = -EINVAL; in stm32_init_port()
888 struct device_node *np = pdev->dev.of_node; in stm32_of_get_stm32_port()
896 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_of_get_stm32_port()
904 "st,hw-flow-ctrl"); in stm32_of_get_stm32_port()
912 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
913 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
914 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
924 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_of_dma_rx_probe()
925 struct uart_port *port = &stm32port->port; in stm32_of_dma_rx_probe()
926 struct device *dev = &pdev->dev; in stm32_of_dma_rx_probe()
933 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); in stm32_of_dma_rx_probe()
934 if (!stm32port->rx_ch) { in stm32_of_dma_rx_probe()
936 return -ENODEV; in stm32_of_dma_rx_probe()
938 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, in stm32_of_dma_rx_probe()
939 &stm32port->rx_dma_buf, in stm32_of_dma_rx_probe()
941 if (!stm32port->rx_buf) { in stm32_of_dma_rx_probe()
942 ret = -ENOMEM; in stm32_of_dma_rx_probe()
948 config.src_addr = port->mapbase + ofs->rdr; in stm32_of_dma_rx_probe()
951 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_of_dma_rx_probe()
954 ret = -ENODEV; in stm32_of_dma_rx_probe()
959 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, in stm32_of_dma_rx_probe()
960 stm32port->rx_dma_buf, in stm32_of_dma_rx_probe()
965 ret = -ENODEV; in stm32_of_dma_rx_probe()
970 desc->callback = NULL; in stm32_of_dma_rx_probe()
971 desc->callback_param = NULL; in stm32_of_dma_rx_probe()
977 dma_async_issue_pending(stm32port->rx_ch); in stm32_of_dma_rx_probe()
982 dma_free_coherent(&pdev->dev, in stm32_of_dma_rx_probe()
983 RX_BUF_L, stm32port->rx_buf, in stm32_of_dma_rx_probe()
984 stm32port->rx_dma_buf); in stm32_of_dma_rx_probe()
987 dma_release_channel(stm32port->rx_ch); in stm32_of_dma_rx_probe()
988 stm32port->rx_ch = NULL; in stm32_of_dma_rx_probe()
996 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_of_dma_tx_probe()
997 struct uart_port *port = &stm32port->port; in stm32_of_dma_tx_probe()
998 struct device *dev = &pdev->dev; in stm32_of_dma_tx_probe()
1002 stm32port->tx_dma_busy = false; in stm32_of_dma_tx_probe()
1005 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); in stm32_of_dma_tx_probe()
1006 if (!stm32port->tx_ch) { in stm32_of_dma_tx_probe()
1008 return -ENODEV; in stm32_of_dma_tx_probe()
1010 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, in stm32_of_dma_tx_probe()
1011 &stm32port->tx_dma_buf, in stm32_of_dma_tx_probe()
1013 if (!stm32port->tx_buf) { in stm32_of_dma_tx_probe()
1014 ret = -ENOMEM; in stm32_of_dma_tx_probe()
1020 config.dst_addr = port->mapbase + ofs->tdr; in stm32_of_dma_tx_probe()
1023 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_of_dma_tx_probe()
1026 ret = -ENODEV; in stm32_of_dma_tx_probe()
1033 dma_free_coherent(&pdev->dev, in stm32_of_dma_tx_probe()
1034 TX_BUF_L, stm32port->tx_buf, in stm32_of_dma_tx_probe()
1035 stm32port->tx_dma_buf); in stm32_of_dma_tx_probe()
1038 dma_release_channel(stm32port->tx_ch); in stm32_of_dma_tx_probe()
1039 stm32port->tx_ch = NULL; in stm32_of_dma_tx_probe()
1052 return -ENODEV; in stm32_serial_probe()
1054 match = of_match_device(stm32_match, &pdev->dev); in stm32_serial_probe()
1055 if (match && match->data) in stm32_serial_probe()
1056 stm32port->info = (struct stm32_usart_info *)match->data; in stm32_serial_probe()
1058 return -EINVAL; in stm32_serial_probe()
1064 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) { in stm32_serial_probe()
1065 ret = device_init_wakeup(&pdev->dev, true); in stm32_serial_probe()
1069 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, in stm32_serial_probe()
1070 stm32port->wakeirq); in stm32_serial_probe()
1074 device_set_wakeup_enable(&pdev->dev, false); in stm32_serial_probe()
1077 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_serial_probe()
1083 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); in stm32_serial_probe()
1087 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); in stm32_serial_probe()
1089 platform_set_drvdata(pdev, &stm32port->port); in stm32_serial_probe()
1094 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) in stm32_serial_probe()
1095 dev_pm_clear_wake_irq(&pdev->dev); in stm32_serial_probe()
1098 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) in stm32_serial_probe()
1099 device_init_wakeup(&pdev->dev, false); in stm32_serial_probe()
1102 clk_disable_unprepare(stm32port->clk); in stm32_serial_probe()
1111 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_serial_remove()
1112 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_serial_remove()
1114 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_serial_remove()
1116 if (stm32_port->rx_ch) in stm32_serial_remove()
1117 dma_release_channel(stm32_port->rx_ch); in stm32_serial_remove()
1119 if (stm32_port->rx_dma_buf) in stm32_serial_remove()
1120 dma_free_coherent(&pdev->dev, in stm32_serial_remove()
1121 RX_BUF_L, stm32_port->rx_buf, in stm32_serial_remove()
1122 stm32_port->rx_dma_buf); in stm32_serial_remove()
1124 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_serial_remove()
1126 if (stm32_port->tx_ch) in stm32_serial_remove()
1127 dma_release_channel(stm32_port->tx_ch); in stm32_serial_remove()
1129 if (stm32_port->tx_dma_buf) in stm32_serial_remove()
1130 dma_free_coherent(&pdev->dev, in stm32_serial_remove()
1131 TX_BUF_L, stm32_port->tx_buf, in stm32_serial_remove()
1132 stm32_port->tx_dma_buf); in stm32_serial_remove()
1134 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) { in stm32_serial_remove()
1135 dev_pm_clear_wake_irq(&pdev->dev); in stm32_serial_remove()
1136 device_init_wakeup(&pdev->dev, false); in stm32_serial_remove()
1139 clk_disable_unprepare(stm32_port->clk); in stm32_serial_remove()
1149 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_console_putchar()
1151 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_console_putchar()
1154 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_console_putchar()
1159 struct uart_port *port = &stm32_ports[co->index].port; in stm32_console_write()
1161 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_console_write()
1162 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_console_write()
1168 if (port->sysrq) in stm32_console_write()
1171 locked = spin_trylock(&port->lock); in stm32_console_write()
1173 spin_lock(&port->lock); in stm32_console_write()
1176 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_console_write()
1178 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_console_write()
1179 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_console_write()
1184 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_console_write()
1187 spin_unlock(&port->lock); in stm32_console_write()
1199 if (co->index >= STM32_MAX_PORTS) in stm32_console_setup()
1200 return -ENODEV; in stm32_console_setup()
1202 stm32port = &stm32_ports[co->index]; in stm32_console_setup()
1207 * this to be called during the uart port registration when the in stm32_console_setup()
1210 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) in stm32_console_setup()
1211 return -ENXIO; in stm32_console_setup()
1216 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_console_setup()
1225 .index = -1,
1248 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_serial_enable_wakeup()
1249 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_serial_enable_wakeup()
1252 if (!cfg->has_wakeup || stm32_port->wakeirq < 0) in stm32_serial_enable_wakeup()
1256 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_serial_enable_wakeup()
1257 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_serial_enable_wakeup()
1258 val = readl_relaxed(port->membase + ofs->cr3); in stm32_serial_enable_wakeup()
1262 writel_relaxed(val, port->membase + ofs->cr3); in stm32_serial_enable_wakeup()
1263 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_serial_enable_wakeup()
1265 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_serial_enable_wakeup()
1310 static char banner[] __initdata = "STM32 USART driver initialized"; in usart_init()
1336 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");