Lines Matching +full:buffer +full:- +full:enable
1 // SPDX-License-Identifier: GPL-1.0+
97 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
98 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
99 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
100 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
104 #define SCKE (1 << 10) /* USB Module Clock Enable */
105 #define HSE (1 << 7) /* High-Speed Operation Enable */
107 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
109 #define USBE (1 << 0) /* USB Module Operation Enable */
111 #define UPLLE (1 << 1) /* USB PLL Enable for RZ/A1 */
117 #define UACT (1 << 4) /* USB Bus Enable */
119 #define RHST_LOW_SPEED 1 /* Low-speed connection */
120 #define RHST_FULL_SPEED 2 /* Full-speed connection */
121 #define RHST_HIGH_SPEED 3 /* High-speed connection */
124 #define DREQE (1 << 12) /* DMA Transfer Request Enable */
128 #define BVAL (1 << 15) /* Buffer Memory Enable Flag */
129 #define BCLR (1 << 14) /* CPU buffer clear */
134 #define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
135 #define RSME (1 << 14) /* Enable IRQ Resume */
136 #define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
137 #define DVSE (1 << 12) /* Enable IRQ Device State Transition */
138 #define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
139 #define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
140 #define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
141 #define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
144 #define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
145 #define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
146 #define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
147 #define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
148 #define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
149 #define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
155 #define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
156 #define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
192 #define DBLB (1 << 9) /* Double Buffer Mode */
209 #define BSTS (1 << 15) /* Buffer Status */
211 #define INBUFM (1 << 14) /* (PIPEnCTR) Transfer Buffer Monitor */
213 #define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
224 #define CCPL (1 << 2) /* Control Transfer End Enable */
227 #define TRENB (1 << 9) /* Transaction Counter Enable */
297 void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
298 void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
299 void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
314 int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
336 #define usbhs_get_dparam(priv, param) (priv->dparam.param)
337 #define usbhs_priv_to_pdev(priv) (priv->pdev)
338 #define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
339 #define usbhs_priv_to_lock(priv) (&priv->lock)